JPH0831586B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0831586B2 JPH0831586B2 JP62028428A JP2842887A JPH0831586B2 JP H0831586 B2 JPH0831586 B2 JP H0831586B2 JP 62028428 A JP62028428 A JP 62028428A JP 2842887 A JP2842887 A JP 2842887A JP H0831586 B2 JPH0831586 B2 JP H0831586B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- gate
- semiconductor device
- ccd
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000001444 catalytic combustion detection Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 241000370685 Arge Species 0.000 description 1
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明は、特にハイブリッド型のIRCCD（Infrared Ch
arge Coupled Devicesの略）において、多画素化による
転送能力の低下を防止するため、IRCCDの１ビットに対
し、少なくとも２画素を対応させ、入力ゲートによるア
ドレスにより、高性能の多画素化を実現したものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention is particularly applicable to a hybrid type IRCCD (Infrared Ch
(Arge Coupled Devices), in order to prevent the transfer capacity from deteriorating due to the increase in the number of pixels, at least 2 pixels are made to correspond to 1 bit of IRCCD, and a high-performance multi-pixel is realized by the address by the input gate. It is a thing.
本発明は赤外線２次元センサ用の半導体装置に関する
ものである。The present invention relates to a semiconductor device for an infrared two-dimensional sensor.
赤外線２次元センサとして、ハイブリッド型IRCCDは
有望であるが、多画素化（大規模化）されるにつれ、１
ビット当たりのセル容量が減少し、性能が劣化する（セ
ル容量が減少すると、入力信号を有効に受け入れること
ができなくなり、入力信号中の多くの部分が放出されて
しまう）問題がある。Hybrid IRCCD is promising as a two-dimensional infrared sensor, but as the number of pixels increases (large scale), 1
There is a problem that the cell capacity per bit is reduced and the performance is deteriorated (when the cell capacity is reduced, the input signal cannot be effectively accepted and a large part of the input signal is emitted).
このため、セル容量を低下させることなく、多画素化
する方法が必要となる。Therefore, a method of increasing the number of pixels without reducing the cell capacity is needed.
〔従来の技術〕 第３図は従来のIRCCDの単位セルの構成図であって、1
0は４つの転送電極φ1,φ2,φ3,φ４より成る１ビット
のCCD、11は蓄積ゲート、12は入力ゲート、13は入力ダ
イオード、14はオーバーフローゲート、15はオーバーフ
ロードレイン、16は移送ゲートをそれぞれ示す。[Prior Art] FIG. 3 is a block diagram of a unit cell of a conventional IRCCD.
0 is a 1-bit CCD consisting of four transfer electrodes φ1, φ2, φ3, and φ4, 11 is a storage gate, 12 is an input gate, 13 is an input diode, 14 is an overflow gate, 15 is an overflow drain, and 16 is a transfer gate. Shown respectively.
従来の単位セルは第３図に示すように、単一の蓄積ゲ
ート11に対して入力ゲート12と入力ダイオード13を各１
個宛対応させた構成になっている。In the conventional unit cell, as shown in FIG. 3, one input gate 12 and one input diode 13 are provided for each single storage gate 11.
It is configured to correspond to individual items.
しかして例えばHgCdTe結晶等からなる赤外線検知素子
20によって検出された赤外線は、信号化されて入力ダイ
オード13に入力され、入力ゲート12を介して蓄積ゲート
11に入力される。そして蓄積ゲート11に入力された赤外
線信号は、移送ゲート16からCCD10の転送電極φ３に入
力され、図示しないCCDの出力部から取り出される。Therefore, for example, an infrared detector made of HgCdTe crystal or the like
The infrared light detected by 20 is converted into a signal and input to the input diode 13, and the storage gate is input through the input gate 12.
Entered in 11. The infrared signal input to the storage gate 11 is input from the transfer gate 16 to the transfer electrode φ3 of the CCD 10 and taken out from the output portion of the CCD (not shown).
しかしながら上記半導体装置は、多画素化のために単
位セルの寸法を微細化すると、セル容量が低下して転送
能力が劣化するなどの問題点があった。However, in the above semiconductor device, when the size of the unit cell is miniaturized to increase the number of pixels, there is a problem that the cell capacity is reduced and the transfer capability is deteriorated.
本発明の半導体装置は、入力ダイオードから蓄積ゲー
ト下に入力される信号電荷を入力ゲートによって制御
し、前記蓄積ゲート下の電荷を移送ゲートを介してCCD
へ入力する構成の半導体装置において、複数個の入力ダ
イオードを、それぞれ個別に制御可能な入力ゲートを介
して、単一の蓄積ゲートに接続し、前記入力ダイオード
が前記入力ゲートへのバイアスの有無によって時分割的
に選択される構成になっている。In the semiconductor device of the present invention, the signal charge input from the input diode to the storage gate is controlled by the input gate, and the charge below the storage gate is transferred to the CCD via the transfer gate.
In a semiconductor device configured to input to a plurality of input diodes, each input diode is connected to a single storage gate via an individually controllable input gate, and the input diode is biased to the input gate. It is configured to be selected in a time division manner.
このように構成された半導体装置は、入力ゲートをア
ドレスすることによってＮ個（Ｎは複数）の入力ダイオ
ードの内の１つを選択し、その出力信号をCCDに入力す
ることで、時分割的に、１ビットのCCDでＮ画素を読み
出すことができる。この場合、積分時間は通常の動作の
1/Nになるが、光電変換効率が高い場合は全く問題とな
らない。The semiconductor device configured as described above selects one of N (N is a plurality) input diodes by addressing the input gate and inputs the output signal to the CCD, thereby performing time-division In addition, N pixels can be read by a 1-bit CCD. In this case, the integration time is
It becomes 1 / N, but if the photoelectric conversion efficiency is high, there is no problem at all.
以下実施例図に基づいて本発明を詳細に説明する。 The present invention will be described in detail below with reference to the accompanying drawings.
第１図は本発明の一実施例を示す模式図であるが、前
記第３図と同一部分には同一符号を付している。FIG. 1 is a schematic diagram showing an embodiment of the present invention, in which the same parts as those in FIG. 3 are designated by the same reference numerals.
第１図に示すように、本発明にかかる単位セルは、蓄
積ゲート11を挟む形で配置された４個の入力ダイオード
3a,3b,3c,3dと、該入力ダイオードと前記単一の蓄積ゲ
ート11との間に配置された４個の第１の入力ゲート2a,2
b,2c,2dと、２個の第２の入力ゲート2A,2Bと、それを挟
む形で配置された各１対のオーバーフローゲート14A,14
Bおよびオーバーフロードレイン15A,15Bと、１ビットの
CCD10とによって構成され、前記４個の第１の入力ゲー
ト2a,2cおよび2b,2dは、母線X1,X2によって，また第２
の入力ゲート2A,2Bは、母線Y1,Y2によって時分割的に制
御される。As shown in FIG. 1, the unit cell according to the present invention has four input diodes arranged so as to sandwich the storage gate 11.
3a, 3b, 3c, 3d and four first input gates 2a, 2 arranged between the input diode and the single storage gate 11.
b, 2c, 2d, two second input gates 2A, 2B, and a pair of overflow gates 14A, 14 arranged so as to sandwich them.
B and overflow drain 15A, 15B and 1-bit
A CCD 10 and the four first input gates 2a, 2c and 2b, 2d are connected by bus lines X1, X2 and
The input gates 2A, 2B of are controlled by bus lines Y1, Y2 in a time division manner.
なお、図中の〜は赤外線検知素子を示している。
また１個の入力ダイオードが選択されている時は他の３
個の入力ダイオードはオーバーフローゲートを介してオ
ーバーフロードレインに電気的に接続されるよう制御さ
れる。In addition, in the figure, -indicates an infrared detection element.
When one input diode is selected, the other 3
The input diodes are controlled to be electrically connected to the overflow drain via the overflow gate.
このように構成された半導体装置によれば、前記入力
ダイオード3a,3b,3c,3dからの入力を４つに時分割してC
CD10に転送することができるため信号が重複せず、信号
の溢れ現象が無くなって半導体装置の効率化を実現でき
る。According to the semiconductor device having such a configuration, the inputs from the input diodes 3a, 3b, 3c, 3d are time-divided into four C
Since the signals can be transferred to the CD 10, the signals do not overlap, the signal overflow phenomenon disappears, and the efficiency of the semiconductor device can be improved.
第２図（ａ）と（ｂ）は本発明の一応用例を示す結線
図と信号形態の一例を示す図である。2 (a) and 2 (b) are a connection diagram showing an application example of the present invention and a diagram showing an example of a signal form.
第２図（ａ）に示すようにこの応用例は、３×３の９
ビット構成になっている。図中、点線内はCCDを示し、
２点鎖線内はCCDを除く入力部分を示している。As shown in FIG. 2 (a), this application example uses 3 × 3 9
It has a bit structure. In the figure, the dotted line shows the CCD
The two-dot chain line shows the input part excluding the CCD.
また丸印で示す符号１〜４は第１図に示した第１の入
力ゲート2a〜2dに対応し、丸印5,6は第２の入力ゲート2
A,2Bに対応している。第１の入力ゲート2a〜2dは母線X
1,X2に、第２の入力ゲート2A,2Bは母線Y1,Y2に接続され
ている。Further, reference numerals 1 to 4 indicated by circles correspond to the first input gates 2a to 2d shown in FIG. 1, and circles 5 and 6 indicate the second input gate 2
It corresponds to A and 2B. The first input gates 2a to 2d are bus X
The first input gates 2A and 2B are connected to the busbars Y1 and Y2.
母線X1,X2およびY1,Y2に第２図（ｂ）に示すパルスを
印加すれば、４つの入力ダイオード3a〜3dからの入力電
荷が時分割で順次蓄積ゲート11下へ注入され、移送ゲー
ト16とCCD10内を転送されて図示しない出力部から出力
される。When the pulses shown in FIG. 2B are applied to the bus lines X1, X2 and Y1, Y2, the input charges from the four input diodes 3a to 3d are sequentially injected under the storage gate 11 in a time division manner, and the transfer gate 16 Is transferred in the CCD 10 and is output from an output unit (not shown).
なお、本実施例では４画素を２重構造の入力ゲートで
選択するようにしたが、３重以上のゲート数にして、よ
り多くの画素を時分割で選択できることは勿論である。Although four pixels are selected by the input gate having a double structure in the present embodiment, it is a matter of course that more pixels can be selected by time division with a gate number of three or more.
本発明によれば、少ないビット数のCCDで多数の画素
からの信号を読み出せることから、セル容量の増大とあ
いまって、高性能，多画素化が容易に実現できる。According to the present invention, since signals from a large number of pixels can be read by a CCD having a small number of bits, it is possible to easily realize high performance and a large number of pixels together with an increase in cell capacity.
第１図は本発明の一実施例を示す模式図、 第２図（ａ）と（ｂ）は本発明の一応用例を示す結線図
と信号形態の一例を示す図、 第３図は従来の単位セルの構成を示す模式図である。 図中、2a,2b,2c,2dは第１の入力ゲート、 2A,2Bは第２の入力ゲート、 3a,3b,3c,3dは入力ダイオード、 10はCCD、 11は蓄積ゲート、 14A,14Bはオーバーフローゲート、 15A,15Bはオーバーフロードレイン、 16は移送ゲート、 をそれぞれ示す。1 is a schematic diagram showing an embodiment of the present invention, FIGS. 2 (a) and 2 (b) are diagrams showing an application example of the present invention and an example of a signal form, and FIG. 3 is a conventional diagram. It is a schematic diagram which shows the structure of a unit cell. In the figure, 2a, 2b, 2c, 2d are first input gates, 2A, 2B are second input gates, 3a, 3b, 3c, 3d are input diodes, 10 are CCDs, 11 are storage gates, 14A, 14B Is an overflow gate, 15A and 15B are overflow drains, and 16 is a transfer gate.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０４Ｎ 5/335 Ｆ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H04N 5/335 F
Claims (1)
れる信号電荷を入力ゲートによって制御し、前記蓄積ゲ
ート下の電荷を移送ゲートを介してCCDへ入力する構成
の半導体装置において、 複数個の前記入力ダイオードを、それぞれ個別に制御可
能な入力ゲートを介して、単一の蓄積ゲートに接続し、
前記入力ダイオードが前記入力ゲートへのバイアスの有
無によって時分割的に選択される構成としたことを特徴
とする半導体装置。1. A semiconductor device having a structure in which signal charges input from an input diode to a storage gate are controlled by an input gate, and charges below the storage gate are input to a CCD via a transfer gate. Connect the input diodes to a single storage gate via each individually controllable input gate,
A semiconductor device characterized in that the input diode is selected in a time division manner depending on whether or not a bias is applied to the input gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62028428A JPH0831586B2 (en) | 1987-02-09 | 1987-02-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62028428A JPH0831586B2 (en) | 1987-02-09 | 1987-02-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63194360A JPS63194360A (en) | 1988-08-11 |
| JPH0831586B2 true JPH0831586B2 (en) | 1996-03-27 |
Family
ID=12248387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62028428A Expired - Lifetime JPH0831586B2 (en) | 1987-02-09 | 1987-02-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0831586B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2641802B2 (en) * | 1990-12-27 | 1997-08-20 | 富士通株式会社 | Imaging device |
-
1987
- 1987-02-09 JP JP62028428A patent/JPH0831586B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63194360A (en) | 1988-08-11 |
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