JP2959279B2 - Signal readout circuit for charge integration type two-dimensional array photodetector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reading circuit for a charge storage type two-dimensional array photodetector.

[0002]

2. Description of the Related Art A two-dimensional array infrared detector comprises a signal detecting section and a circuit for reading out the signal to the outside.

As an example, the magazine IEEE Transa
actions on Electron Device
s vol. 38 NO. 5, Rockwell International, US, page 1104.
al uses 256 HgCdTe photodiodes
FIG. 3 shows a circuit diagram of a signal readout circuit developed for a x256 array intermediate infrared detector. In the two-dimensional array surface, the unit cell 1 includes a charge storage capacitor 2, a photodiode contact electrode (indicated by a photodiode 3 in the figure), a direct injection gate transistor 5, a reset transistor 6, and a readout transistor 7. It is composed of The gate inputs of the reset transistor and the read transistor are X
The charge controlled by the shift register 8 and integrated in the charge storage capacitor of each pixel is a Y-shift register 9
Is transferred to the read line 12 and output via the buffer amplifier 13.

[0004]

In order to improve the temperature resolution of a two-dimensional array infrared detector, it is necessary to increase the amount of accumulated charge as much as possible. On the other hand, due to the demand for the number of pixels and the miniaturization of the detector, the size of the unit pixel constituting the two-dimensional array is 5 × 128 × 128 array.
0 to 60 μm □, about 40 μm □ in a 256 × 256 array. The remaining three transistors and wiring portions included in the unit pixel are regions that can be used as charge storage capacitors. An important issue is how to effectively use the limited pixel area as the integration capacitance. The pixel size, the area utilization rate (the ratio of the capacitor area to the unit pixel area), and the surface capacitance were 40 μm □, 39%, and 8%, respectively.
If it is × 10 ⁻⁴ pF / μm ² , the capacitance is 0.5 pF.

Here, the light receiving wavelength band is 3-5 μm and 4.2.
Table 1 shows the estimation of the saturation integration time in the background state of ４4.8 μm, background temperatures of 300 K and 350 K.

[0006]

[Table 1]

In this calculation, the F value of the optical system: 2.0, the transmittance of the optical system: 0.68, the integral capacitance: 0.5 pF, the voltage swing: 3 V, the quantum efficiency: 0.5, the area of the light receiving section : 1.68 × 10 ^- it was ⁵ cm ^2. In the background state given in the table, it can be seen that the integration capacity has reached saturation before the maximum integration time of 8.33 ms (frame rate: 120 Hz). That is, the storage capacitance limits the temperature resolution.

An object of the present invention is to solve such problems of the conventional type and improve the temperature resolution.

[0009]

In order to achieve the above object, in a signal readout circuit for detecting electric charge of a charge storage type two-dimensional array according to the present invention, a unit cell in a two-dimensional array plane has a charge storage capacitor. One reset contact transistor, one read contact transistor, one direct injection gate transistor, one reset transistor, and one read transistor. comprising a shift register for controlling the gates of the transistors, a shift register for transferring the read line, and a gate control shift register of the photodiode selection transistors, and a signal read line and buffer amplifier, N pieces of follower
One-to-one correspondence with photodiode contact electrodes
The photodiode selection transistor is connected,
Any of the N photodiode selection transistors
One of the gate electrodes is connected to the photodiode selecting transistor.
In a time-sharing manner using a transistor shift register for gate control
By inserting, the N photodiode photodiodes
The contact electrode is time-divisionally and selectively
Charge storage via the application gate transistor
It is electrically connected to a capacitor for use. Here, N is an integer value other than 0 and 1 smaller than the total number of pixels.

[0010]

By detecting the signals of the N photodiodes in one unit cell, the unit cell area becomes N times as large as that of the conventional type, so that it is possible to realize N times or more the integrated capacity of the conventional type. As a result, the temperature resolution is improved at most N ^1/2 times. Further, since the number of readout transistors is smaller than that of the conventional type, the stray capacitance is reduced by that amount, and deterioration of the temperature resolution due to the capacitance division is reduced.

[0011]

An embodiment of the present invention will be described with reference to the drawings. N =
FIG. 1 schematically shows a signal readout circuit for the charge storage type two-dimensional array photodetector in the case of No. 4. The unit cells in the plane of the two-dimensional array are a charge storage capacitor 2 and a contact electrode for a photodiode (MCT photodiode 3 in the figure).
), The photodiode selecting transistor 4,
It comprises a direct injection gate transistor 5, a reset transistor 6, and a read transistor 7. The photodiode / selection transistor 4 operates with a shift register 10. The gates of the reset transistor 6 and the read transistor 7 are controlled by an X-shift register 8, and the transfer from the low bus 11 to the read line 12 is performed by a Y-shift register 9. The circuit of the present invention is characterized in that one unit cell sequentially outputs signals of four adjacent photodiodes in a time-division manner.
The driving method will be described with reference to the timing chart of FIG.

At the first quarter frame, that is, at the time indicated by A in FIG. 2, the signal of the upper left pixel (see FIG. 1) of the four adjacent photodiodes is detected. Similarly, the next 1
Signal detection is performed in the order of upper right in / 4 frame (B in FIG. 2), lower left in C, and lower right in D, and signal processing of all pixels is completed in one frame.

Next, paying attention to the unit cell (i, k),
The operation until a signal is output will be described. In each unit cell, one of the photodiodes is always selected by the photodiode selection transistor 4, and the photocurrent generated by the photodiode is integrated into the charge storage capacitor 2 via the direct injection gate transistor 5. You. The read transistor 7 is selected by the X-shift register 8 (XSi in FIG. 2),
The signal is transferred to a signal readout line by a Y-shift register 9 (Yk in FIG. 2) and output via a buffer amplifier 13.

According to the signal readout circuit for a charge storage type two-dimensional array photodetector of the present invention, the signal readout of four adjacent photodiodes (for four pixels) is performed by one unit cell, so that the conventional type is used. A four-fold integration capacity can be realized. Further, as compared with the conventional type, the area utilization ratio (the ratio of the capacitor area to the unit pixel area) is improved to less than half the number of transistors and the number of wirings per pixel as shown in Table 2. As a result, an integrated capacitance of 2.15 pF was realized using the same prototype process as before.
This is 4.3 times the integration capacity of the conventional type.

[0015]

[Table 2]

When the light receiving wavelength band is 4.2 to 4.8 μm, the background temperature is 350 K, the F value of the optical system is 2.0, the voltage swing is 3 V, and the integration capacitance is 0.5 pF, the integration time is 2.0.
A temperature resolution of 27.6 mK was obtained in 7 ms. The conventional type has a maximum temperature resolution of 41.3 mK under the same background radiation conditions.
(Saturation limit of integral capacity), about 50% improvement in temperature decomposition was observed. The charge accumulation amount at this time is 56% of the saturation.
Up to 210% under conditions of higher background radiation
A degree of improvement in temperature resolution can be expected.

[0017]

As described above, in the signal readout circuit for the charge storage type two-dimensional array photodetector of the present invention, N
By detecting the signals of the photodiodes with one unit cell, the unit cell area becomes N times as large as that of the conventional type, so that the integration capacity of N times or more of the conventional type can be realized. As a result, the temperature resolution is improved at most N ^1/2 times. In addition, since the number of read transistors is smaller than that of the conventional type, the stray capacitance of the low bus is reduced, and there is an effect that deterioration in temperature resolution due to capacitance division is suppressed.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a signal readout circuit for a charge storage type two-dimensional array photodetector of the present invention.

FIG. 2 is a timing chart of a signal readout circuit for a charge storage type two-dimensional array photodetector of the present invention.

FIG. 3 is an explanatory diagram of a signal readout circuit for a conventional charge storage type two-dimensional array photodetector.

[Explanation of symbols]

Reference Signs List 1 unit cell 2 charge storage capacitor 3 photodiode 4 photodiode selection transistor 5 direct injection gate transistor 6 reset transistor 7 readout transistor 8 X-shift transistor 9 Y-shift transistor 10 pixel selection shift register 11 low bus 12 signal Readout transistor 13 Buffer amplifier

Claims (1)

(57) [Claims] 1. A unit cell in a two-dimensional array plane of a signal read circuit includes one charge storage capacitor, N photodiode contact electrodes, N photodiode selection transistors, and direct injection gate transistor 1. Pcs, reset transistor 1
And one readout transistor (where N is an integer smaller than the total number of pixels, other than 0 and 1), and the gate control shift register of the photodiode selection transistor, the reset transistor, and the readout transistor a shift transistor for controlling the gate, comprises a shift register for transferring the read out signal lines, and a signal read line and buffer amplifier, a contact conductive for N photodiodes
Each pole has a corresponding one-to-one photodiode selection transformer.
A transistor is connected, and one of the gate electrodes of the N photodiode selection transistors is turned on in a time-division manner by a gate control shift register of the photodiode selection transistor, whereby the N photodiodes are connected. The contact electrode for the diode is selectively divided in a time-sharing manner through a direct injection gate transistor.
A signal readout circuit for a charge integration type two-dimensional array photodetector, which is electrically connected to a charge storage capacitor.