JPH08315588A - Semiconductor memory - Google Patents

Abstract

PURPOSE: To increase the number of times for erasing or writing information while reading out the information accurately by interposing a select transistor between a memory cell and a data line and between a memory cell and a power supply terminal. CONSTITUTION: When a word line WL is raised at the time of reading stored information, the level of a signal DDC goes low while the level of signals RPC, SID go high and a transistor Tr1 is turned on. When the potential of a data line DL is held at IV, for example, upon lapse of a time required for precharge, the level of signal SIS goes high to turn a transistor Tr2 on. Potential on the data line DL varys depending on the fact whether a selected memory cell MC is turned on or not, and the potential is detected by a sense amplifier. At the time of writing operation, a transistor Qp is turned on while turning transistors Qd , Tr2 to charge up the data line DL and a selected word line is set at about -10V, for example.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is particularly effective when applied to a semiconductor memory device as well as an electrically writable and erasable non-volatile memory. For example, the present invention is applied to a flash memory in which bit lines are hierarchized. And useful technology.

[0002]

2. Description of the Related Art An electrically erasable / writable memory (EEPROM) called a flash memory is capable of appropriately rewriting stored information, of which erasing is performed on all or part of memory cells on a memory chip. It is carried out in batch. In this flash memory, each memory cell is composed of a FAMOS (floating gate avalanche MOSFET) having a control gate and a floating gate.

The writing of information to the memory cell thus constructed is performed by injecting electrons into the floating gate. A memory cell having electrons stored in the floating gate has a high threshold voltage, while a memory cell having no electrons stored has a low threshold voltage. Therefore, when the information is read, the stored information is read by detecting the potential difference or the current difference generated in the data line due to the difference in the threshold voltage by the sense amplifier.

On the other hand, when erasing the stored information, a negative potential (for example, -10V) is applied to the control gate electrode and a positive potential (for example, 5V) is applied to the source or drain electrode, and the floating gate electrode is subjected to the tunnel effect. The threshold voltage is lowered by drawing out the stored electric charge.

[0005]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, in the flash memory having the above structure, when rewriting a part of the stored information,
A high voltage is applied even to a memory cell in which data is not written, the threshold value of the memory cell other than the target fluctuates, and the number of times information in the flash memory can be rewritten is limited.

Therefore, as shown in FIG. 5, the drain line L1 to which the drains of the plurality of memory cells MC1 ... MCm are commonly connected is connected to the data line D via the MOS switch Tr1.
The source line L2 connected to L and commonly connected to the source terminals of the memory cells can be connected to the power supply voltage Vdd such as the ground potential via the MOS switch Tr2, and
A flash memory in which data can be written and read by selectively turning on the S switches Tr1 and Tr2 was examined.

In the memory having the above structure, the data line DL is precharged at the time of reading information, and then the M
When the OS switch Tr1 is turned on, charge redistribution between the data line DL and the drain line L1 causes the data line DL to be distributed.
It has been found that there is a problem in that the precharge potential of 1 is lowered and the read sensitivity of data by the sense amplifier SA is lowered.

The present invention has been made in view of the above circumstances, and has a circuit configuration capable of increasing the number of times that erase / write processing of stored information in a flash memory is possible,
It is a main object of the present invention to provide a semiconductor memory device having a read circuit capable of accurately reading the stored information.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, according to the present invention, in a semiconductor memory device having a memory cell array in which a plurality of FAMOSs are connected in parallel as memory cells between a data line and a power supply voltage line, a common drain of memory cells in the same column is provided. A local drain line is provided between the data line and
The local drain line is connected to the data line via a first select transistor, and a local source line is provided between the common source of the memory cells in the same column and the power supply voltage terminal. A second selection transistor is provided between them and the power supply voltage terminal,
When the information stored in the memory cell is read, the first selection transistor is turned on earlier than the second selection transistor by a predetermined time.

[0011]

A memory cell that requires erasing / writing of information by turning on / off the first and second selection transistors interposed between the memory cell and the data line and between the memory cell and the power supply voltage terminal. Only the data can be erased / written to the memory cells selectively, and the threshold voltage fluctuates by avoiding application of a high voltage for erasing to memory cells other than the intended cells. To prevent
It is possible to increase the number of times that information can be erased / written in the flash memory. Moreover,
At the time of data reading, the first selection transistor on the local drain line side is turned on before the second selection transistor on the local source line side.
When the second select transistor is turned on, the local drain line is sufficiently charged by the time the select transistor of FIG. Amplification is possible.

[0012]

【Example】

(First Embodiment) An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an example of a flash memory to which the present invention is applied, FIG. 2 is a circuit diagram showing a configuration example of a memory array section, and FIG. 3 is a timing chart showing signal timing of each section in the memory. .

As shown in FIG. 1, the flash memory of this embodiment includes a memory cell array 11 in which a plurality of memory cells of 16 Mbits are arranged in a matrix, and an X-system address input from the outside. An X decoder 12a that takes in and decodes the signal AX, a Y decoder 12b that takes in and decodes a Y-system address signal AY input from the outside, and a selected in the memory cell array 11 selected by the decode output of the X decoder 12a. A sense amplifier 13 that amplifies and holds data read from a memory cell connected to a word line to a data line
And a Y gate circuit 14 for selecting one of the sense amplifiers 13 corresponding to the Y-system address signal by the decoding output of the Y decoder 12b, and data for outputting the data selected by the Y gate circuit 14 to the outside. An output buffer 15, a data input buffer 16 that supplies the input write data to the memory cell array 11 via the Y gate circuit 14, and an operation mode inside the memory that is determined according to the input command. A mode control circuit 17 for forming a control signal required for
A multiplexer 18 which selects write data or a command input from the data input / output terminals I / O0 to I / 07 and supplies it to the data input buffer 16 or the mode control circuit 17, and a chip selection signal CE supplied from the outside. Output control signal OE, write control signal W
E, a control signal input buffer 19 which takes in the system clock SC and supplies it to the mode control circuit 17 and the multiplexer 18, and generates various voltages necessary for the memory such as a write voltage based on the control signal from the mode control circuit 17. And a voltage generation circuit 20 that operates.

In this embodiment, the memory cell array 1 described above is used.
The memory cells constituting 1 are each made of FAMOS.

FIG. 2 shows a configuration example of the memory cell array 11. In the figure, two memory cell columns corresponding to two data lines in the memory cell array are shown.
Such memory cell columns are provided by the number of data lines in the direction orthogonal to the data lines DL. Although not particularly limited, the memory cell array 11 of this embodiment is composed of two mats, and a sense amplifier SA that amplifies the signal of each data line in the memory cell array between the mats.
Is provided. The sense amplifier SA is composed of, for example, a well-known CMOS differential type sense amplifier, and when a memory cell in one mat is selected at the time of data reading, the corresponding data line in the other mat is used for reference. The sense amplifier is connected to the sense amplifier SA as a circuit for applying a potential, and the sense amplifier amplifies the potential difference between the left and right data lines.

In FIG. 2, WL is a word line arranged in a direction orthogonal to the data line DL, MC1, MC2 ...
.. MCm is a memory cell made of FAMOS, and FAMOS control gates in the same row (in the direction orthogonal to the data line in the drawing) are connected to the same word line WL. In this embodiment, a local drain line L1 as a sub data line is extended in parallel with the data line DL, and the drains of FAMOSs in the same column are commonly connected to the local drain line L1.

This local drain line L1 is a selection MOS.
The data line DL is connectable via the transistor Tr1. On the other hand, memory cells in the same column (FAMOS)
The sources of MC1, MC2, ..., MCm are commonly connected to the local drain line L2. The local drain line L2 is connected to the selection MOS transistor Tr.
It is connectable via 2 to a power supply voltage terminal such as a ground point.

In the figure, selection M of the data line DL1
The OS transistors Tr1 and Tr2 and the selection MOS transistors Tr1 and Tr2 of the data line DL2 are configured to be turned on and off by the same selection signals SID and SIS, but other data lines and local drain lines, which are not shown, and local The selection MOS transistor between the source lines can be configured to be selectable by a similar signal corresponding to an address different from the selection signals SID and SIS.

The data lines DL1 and DL2 shown in FIG.
MOS transistors Qs1 and Qs2 provided between the sense amplifiers SA1 and SA2, respectively, can selectively connect to the sense amplifiers SA1 and SA2.
As a result, the simultaneous reading of the memory cells connected to the adjacent data lines is prohibited, which is effective in preventing the generation of noise.

Further, in FIG. 2, Qp and Qd are a precharge MOS transistor and a discharge MOS transistor connected to the data line DL, and the precharge MOS transistor Qp is a power supply voltage terminal V.
cc, the discharge MOS transistor Qd
Is connected to ground. Although not particularly limited, in this embodiment, the signal lines RPC1 and Qp2 for controlling the precharging MOS transistor Qp1 are supplied in order to enable the data lines DL1 and DL2 to be precharged and discharged separately. The control signal line DDC2 is provided separately from the signal lines DDC1 and Qd2 for controlling the discharge MOS transistor Qd1.

The signal line RPC1 is not particularly limited.
Are commonly connected to the gates of the precharge MOS transistors on the odd-numbered data lines, and the signal line RPC2 is commonly connected to the gates of the precharge MOS transistors on the even-numbered data lines.
Similarly, the signal line DDC1 is commonly connected to the gates of the discharge MOS transistors on the odd-numbered data lines, and the signal line DDC2 is commonly connected to the gates of the discharge MOS transistors on the even-numbered data lines. It is configured.

Similarly for the sense amplifiers SA1 and SA2,
Separate control signals SAP1, SAP2 and SAN
1, the precharge MOS transistors Qsp1 and Qsp2 operated in the SAN1 and the SAN2 are connected to the discharge MOS transistors Qsd1 and Qsd2. The precharge control signals (RPC1, RPC2;
SAP1, SAP2) and discharge control signal (DD
C1, DDC2; SAN1, SAN2) and the selection signals SID, SIS described above are supplied from the mode control control circuit 17 (see FIG. 1).

Further, in FIG. 2, the data lines DL1,
MOS transistors QyL1 and Qy connected to DL2
R1, QyL2, QyR2 are column switches that are turned on / off by a selection signal from the Y decoder 13a,
When this column switch is turned on, the potential of the corresponding data line is supplied to the Y gate circuit 14 (see FIG. 1) via the common data lines I / OL and I / OR, and after being further selected here, The data output buffer DOB outputs data in 8-bit units from the data input / output terminals I / O0 to I / O7.

Next, the data read operation in the flash memory of the above embodiment will be described with reference to the timing chart of FIG. In this embodiment, the word line W
When L rises (time t1), the signal DDC is changed to the low level, the discharge MOS transistor Qd of the data line DL is turned off, the signal RPC is changed to the high level, and the precharge MOS transistor Qp is turned on. At the same time, the signal SID changes to high level and the drain-side selection MOS transistor Tr1 is turned on. As a result, the data line DL starts to rise at time t1, and the local drain line L1 is precharged accordingly.

At a time point (t2) when a certain period required for precharge has elapsed, sufficient electric charge is stored in the local drain line L1 and the potential of the data line DL is held at 1.0V. The signal SIS changes to the high level and the source side selection MOS transistor Tr2 is turned on. At this time, the signal RPC changes to low level and the precharge MOS transistor Qp is turned off. When the selection transistor Tr2 is turned on, the amount of current flowing (potential of the data line DL) differs depending on whether the FAMOS forming the selected memory cell is in the on state or the off state. This is the sense amplifier SA
Detected (reading of stored information).

By the way, as described above, the source side selection MO
The drain side selection MOS transistor Tr1 is turned on before turning on the S transistor Tr2 for the following reason. That is, as described above, the local drain line L1
And a plurality of memory cells (1
(0 to 10 m) are connected, the data line DL is precharged to a constant potential (1.0 V), and then the drain-side selection transistor Tr1 and the source-side selection MOS transistor Tr2 are turned on at the same time. Stored charge flows into the local drain line L1,
The potential of the data line DL drops. As shown in Table 1, this potential decreases as the number of memory cells forming the cell group connected to the local drain line L1 increases.

[0027]

[Table 1]

This is because the local drain line L1 is usually constituted by means such as a diffusion layer or polysilicon having a relatively large parasitic capacitance, so that the drain side selection MOS transistor 1 is turned on at the time of reading the stored information. At this time, the electric charge of the data line DL changes to the local drain line L1.
This is because it flows into (is redistributed into).

Therefore, if the drain-side selection MOS transistor Tr1 is turned on at the same timing as the source-side selection MOS transistor Tr2, the detection by the sense amplifier SA will be performed while the potential of the data line DL remains low. Therefore, there is a risk that the stored information may be read incorrectly.

On the other hand, in this embodiment, the drain side selection MOS transistor Tr1 is turned on before the source side selection MOS transistor Tr2 is turned on, so that the local drain line L1 is also precharged. When the transistor Tr2 is turned on, the data line DL
Becomes a predetermined potential (1.0 V). As a result, when the transistor Tr2 is turned on, the information stored in the selected memory cell can be accurately amplified by the sense amplifier SA.

At the time of data writing, the discharge MOS transistor Qd and the source-side selection MO
2. With the S transistor Tr2 turned off, the precharge MOS transistor Qp is turned on to set the data line DL to 3.
This is performed by charging up to 5V to 4.5V and setting the selected word line to a voltage such as -10V. MO for discharging when writing is completed
The S transistor Qd is turned on, and the charge on the data line is extracted. For erasing, 10 to 12 V is applied to the selected word line and − is applied to the well region with the drain side and source side selection MOS transistors Tr1 and Tr2 turned off.
By applying a voltage such as 3 to -4 V, the data of the memory cell is erased in units of word lines that share a well. However, at this time, if a plurality of word lines are selected at the same time, the data in the memory cells can be erased in block units with a common well.

(Second Embodiment) Next, a second embodiment will be described. In the second embodiment, in order to prevent erroneous information reading due to the drop in the potential of the data line DL, the potential drop in the data line DL is expected in consideration of the decrease in the potential of the data line DL due to the turning on of the drain side selection MOS transistor Tr1. The potential is set to a value (for example, 1.15V) higher than the potential (for example, 1.0V) necessary for reading information by a constant value. 4. FIG. 4 is a timing chart showing how the signals change in each part of the flash memory to which the second embodiment is applied.

By setting the data line DL to a higher potential in advance as in the second embodiment, the drain side selection MOS transistor Tr1 is turned on and the data line DL is turned on.
Potential required for reading (1.0V) even if the potential of
The information written in the memory cell can be accurately amplified by the sense amplifier SA. Further, according to the second embodiment, the drain side selection M
Even if the OS transistor Tr1 and the source-side selection MOS transistor Tr2 are simultaneously turned on (at time t2) as shown in FIG. 4, a required data line potential can be obtained, and the precharge time can be shortened accordingly. is there.

As a method of precharging the potential of the data line to a value higher than the potential required for reading information in advance, for example, a precharge voltage or M for precharging is used.
A method of making the control signal RPC of the OS transistor higher than that of the first embodiment, a method of using a booster circuit, or the like can be considered.

As described above, in the above embodiment, a plurality of FAMOs are provided between the data line and the power supply voltage line.
In a semiconductor memory device having a memory cell array in which S are connected in parallel as memory cells, a local drain line is provided between the common drain of the memory cells in the same column and the data line, and the local drain line is the first drain. A local source line is provided between the common source of the memory cells in the same column and a power supply voltage terminal while being connected to the data line via a selection transistor, and between the local source line and the power supply voltage terminal. They are provided with a second selection transistor, and when the information stored in the memory cell is read, the first selection transistor is turned on earlier than the second selection transistor by a predetermined time. Turning on / off the first and second selection transistors interposed between the data line, the memory cell and the power supply voltage terminal By doing so, it is possible to selectively perform the erasing / writing process of the information only on the memory cells which need the erasing / writing of the information, and thereby the high voltage for erasing is applied to the memory cells other than the intended one. To prevent it from being applied and prevent its threshold from fluctuating,
It becomes possible to increase the number of times the information in the flash memory can be erased and written, and
When the data is read, the first selection transistor on the local drain line side is turned on before the second selection transistor on the local source line side. When the second selection transistor is turned on by being charged with various charges, the potential of the data line can be prevented from decreasing, and the read signal can be accurately amplified by the sense amplifier.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, an example in which the potential of the data line required for reading information is set to 1.0 V has been described, but the potential is different depending on the memory cell, the sense amplifier, etc., and is not particularly limited. .

Further, in the second embodiment, the source side selection MO
The example in which the potential of the global data line is charged to 1.15V before the S transistor Tr2 is turned on has been described, but the potential can be maintained at a predetermined value necessary for reading information after the drain side selection MOS transistor Tr1 is turned on. The value is not limited to 1.15V.
Further, as in the second embodiment, the global data line DL
Is set in advance to a high value, the two transistors Tr1 and Tr2 do not have to be turned on at the same time. For example, the transistor Tr1 may be turned on and then the transistor Tr1 may be turned on.

In the above description, the case where the invention made by the present inventor is mainly applied to the flash memory which is the background field of application has been described, but the present invention is not limited thereto and the data line is The semiconductor memory device can be generally used in hierarchical semiconductor memory devices.

[0039]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to increase the number of times the stored information in the flash memory can be erased / written, and it is possible to accurately read the stored information.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a flash memory to which the present invention is preferably applied.

FIG. 2 is a circuit diagram showing a main part of the memory cell array according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing how a signal changes in each part of the flash memory according to the embodiment.

FIG. 4 is a timing chart showing how a signal changes in each part of the flash memory according to the second embodiment.

FIG. 5 is a circuit diagram showing a configuration of a memory cell array of a flash memory examined prior to the present invention.

[Explanation of symbols]

 MC Memory cell (FAMOS) SA Sense amplifier DL Data line L1 Local drain line L2 Local source line Tr1 Drain side selection MOS transistor Tr2 Source side selection MOS transistor Qp Precharge transistor Qd Discharge transistor

Claims (4)

[Claims] 1. A FAMO of the same row, in which memory cells composed of MOS transistors are arranged in a matrix and word lines and data lines are arranged in directions orthogonal to each other.
A semiconductor memory device comprising a memory array in which a control gate of S is connected to the word line, and drains and sources of memory cells in the same column can be connected to corresponding data lines and power supply voltage terminals. Is connected to a precharge transistor, a local drain line is provided between the common drain of the memory cells in the same column and the data line, and the local drain line is connected to the data line via the first selection transistor. A local source line is provided between the common source of the plurality of memory cells and the power supply voltage terminal, and a second selection transistor is connected between the local source line and the power supply voltage terminal. When the information stored in the memory cell is read, the precharge transistor and the first selection transistor are provided. A semiconductor memory device characterized in that the transistor is turned on earlier than the second selection transistor by a predetermined time. 2. A FAMO in the same row, in which memory cells composed of MOS transistors are arranged in a matrix and word lines and data lines are arranged in directions orthogonal to each other.
A semiconductor memory device comprising a memory array in which a control gate of S is connected to the word line, and drains and sources of memory cells in the same column can be connected to corresponding data lines and power supply voltage terminals. Is connected to a precharge transistor, a local drain line is provided between the common drain of the memory cells in the same column and the data line, and the local drain line is connected to the data line via the first selection transistor. A local source line is provided between the common source of the plurality of memory cells and the power supply voltage terminal, and a second selection transistor is connected between the local source line and the power supply voltage terminal. When the information stored in the memory cell is read, the data line has a potential higher than that required for reading. A semiconductor memory device, which is configured to be precharged by. 3. The precharge transistor is turned on to precharge the data line, and then the first selection transistor and the second selection transistor are turned on at the same time. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 1, 2 or 3, wherein said memory cell is formed of FAMOS.