JPH0831050B2 - System switching method - Google Patents

Description

The present invention relates to a system switching system for switching a system active system to a standby system device in a dual built-in program control system device.

[Conventional technology]

Conventionally, regarding the system switching method from the active system to the standby system using a redundant configuration, NTT.
82), "Program structure of digital subscriber line exchange"
However, although this method has the advantage that the memory bus and the input / output bus can be switched individually,
The control of system switching becomes complicated and the amount of hardware increases, which is very effective.

[Problems to be solved by the invention]

The object of the present invention is to initialize a failed system completely independently of a new working system even if a system switchover occurs due to a temporary failure of the working system, and to promptly perform a normal standby operation when the failure is recovered. An object of the present invention is to provide a system switching method that can be incorporated into a system as a system and that ensures high reliability of the system at low cost.

[Means for solving problems]

In order to achieve the above object, the bus confounding controller switches between the active system and the standby system in response to a switching signal generated when the active system detects a failure, and the bus on the failed system side and the new active system are newly added. A means for separating the bus on the system side that has become a failure and a means for instructing the above fault system to load the initial program are provided, and when the system is switched due to a temporary failure, the new active system is not the failed system. The operation can be continued independently, and the failure system can be initialized by loading the initial program so that it can be incorporated into the system promptly after the failure recovery.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

In the dual processor system configuration of FIG. 1, the active and standby processor systems are respectively processors 10, 11, main memories 20, 21, file memories 30,
It is composed of 31, processor buses 40 and 41, and the active system and the standby system are entangled by the bus entanglement control device 100.

In normal system operation, the active processor 10
Is not only the active main memory 20 and the active file memory 30, but also the standby main memory 21 and the standby file memory 3.
1 is also accessible. On the other hand, a spare processor 1
1 cannot access the backup system memory 21 and the file memory 31.

FIG. 2 shows that in the configuration of the system shown in FIG.
The active processor system can access only the active main memory and the active file, and similarly, the standby processor system can access only the standby main memory and the standby file.

Next, the operation when system switching occurs while the system is operating in the state of FIG. 1 will be described. In the active processor system, when the active processor 10 detects a temporary failure of the active hardware and switches to the standby processor system, the active processor 10 is the processor bus 40.
A system switching order is sent to the bus confounding control device 100 via. Upon receiving the system switching order, the bus confounding control device 100 performs mode switching between the active system and the standby system, generates a system switching interrupt in the processor 11 which is newly the active system, and the processor which is newly the standby system. A reset signal is sent to 10 to separate the processor buses 40 and 41.

After the system switching, the active system processor 11 that received the system switching interrupt performs initial setting as the active system and then the active system memory 21.
And the operation is continued by the active file memory 31. On the other hand, since the processor bus 40 is separated from the active processor bus 41, the spare processor 10 receiving the reset signal performs the initial program load from the spare file memory 30 to the spare main memory 20 independently of the spare system. , Make initial settings.

When the initial setting of the spare processor system is completed normally, the spare main memory 20 and the spare file memory 30 are made accessible from the active processor 11 via the bus confounding controller 100.

Next, referring to FIG. 3, the bus confounding control device 10 at the time of system switching
The detailed operation of 0 will be described. The bus confounding control device 100 is composed of a system switching signal generating circuit 101, a working / standby control circuit 102, a switching pulse generating circuit 103, an interrupt signal generating circuit 104, a system mode setting circuit 105, and a reset pulse generating circuit 106. When the system switching order 6 is issued from the processor, the system switching signal generation circuit 101 causes the working / spare control circuit 102.
The system switching signal C is sent to the active system and the active system is switched to the standby system. At the same time, the system status signal d causes the active / spare control circuit 102 of the other system to switch from the standby system to the active system. Then, when the system switching between the active system and the standby system is carried out, the switching pulse generating circuit 103 is activated by the active / standby signal e, and the interrupt instruction signal f is sent to the interrupt signal generating circuit 104 in the active system.
The system switching interrupt signal g is sent to the active system processor, and in the standby system, the system mode setting circuit 105 is set to the separation mode by the switching pulse signal h, and when the system separation mode signal j is sent out, the active system is sent. By disconnecting the system entangled bus a that entangles the processor bus 41 and the faulty processor bus 40, the active system and the standby system can be operated independently.

At the same time as the separated operation mode, a reset signal i is generated by the reset pulse generation circuit 106 in the faulty system to load the standby system initial processor.

〔The invention's effect〕

As described above, according to the present invention, in a system in which a processor, a main memory, and a file memory are duplicated, a new active processor bus and a faulty processor bus are separated by a bus confounding controller at the time of system switching due to a temporary failure. However, the new active system can continue to operate independently of the faulty system, and the faulty system can be initialized by the initial program Rosa without adversely affecting the new active system. Can quickly integrate a backup system into the system.

This can be expected to have the effect of ensuring high system reliability.

[Brief description of drawings]

1 and 2 are block block diagrams of the embodiment of the present invention, and FIG. 3 is an example of a block configuration diagram of the system switching control unit in the bus confounding controller used in the embodiment of the present invention. . 10,11 …… Processor, 20,21 …… Main memory, 30,31
…… File memory, 40,41 …… Process bus, 100…
… Bus confounding control device, 101 …… System switching signal generation circuit, 102
...... Current / preliminary control circuit, 103 ...... Switching pulse generation circuit, 104 …… Interrupt signal generation circuit, 105 …… System mode setting circuit, 106 …… Reset pulse generation circuit, a ……
Confounding bus, b ... system switching order, c ... system switching signal, d
...... System status signal, e ... Current / spare signal, f ... Interrupt instruction signal, g ... System switching interrupt signal, h ... Switching pulse signal, i ... Reset signal, j ... Separation of both systems Mode signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Mizuno 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Totsuka Plant, Hitachi Ltd. (72) Hiroshi Tsurusaki 180, Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Stand Communication System Co., Ltd. (56) Reference JP-A-60-1995 (JP, A) JP-A-60-159902 (JP, A) JP-A-60-156146 (JP, A)

Claims (1)

[Claims] 1. A system comprising an active system and a standby system, each system comprising a processor interconnected by a bus, a memory and a file means, and the buses of both systems are connected via a bus confounding controller. And at normal times,
In a system switching system of a redundant system in which the buses of both systems are connected so that the active processor can access the memory and file means of the standby system, when a failure occurs in the active system, the active processor In response to the system switching signal generated from the above, the bus confounding control device gives an interrupt signal for system switching to the processor of the standby system, separates the buses of both systems, and causes the processor of the failed system to The processor on the standby system side, which receives the command signal for initial program load and receives the interrupt signal for system switching, starts operation as the active system based on the memory information of its own system and the file means. However, the processor on the faulty system side that received the command signal for the above initial program load , The initial program is loaded from the file means of the own system to the memory, and when the initial setting is normally completed, a bus switching signal is issued to the bus confounding control device, and the bus confounding control device outputs the bus switching signal to the bus switching signal. In response, the buses of both systems are connected so that the processor of the new active system can access the memory and file means of the new standby system.