JPH08306696A - Semiconductor integrated circuit device and supply of its power supply - Google Patents

Abstract

PURPOSE: To supply efficiently a power supply to I/O cells via few bumps without providing the bumps on the I/O cells. CONSTITUTION: A semiconductor integrated circuit device is provided with plural I/O cells 12 arranged side by side in the longitudinal direction or vertical direction of a semiconductor chip, plural I/O power bumps 13 arranged on the sides of either of the cells 12, logic power bumps arranged in opposition to the bumps 13 in such a way as to hold the cells 12 between the bumps 13 and the logic power bumps, I/O metal wirings 15 connected between the bumps 13 and the logic power bumps and branch wirings 16 connected between these wirings 15 and the cells 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to bumps arranged in a matrix on a semiconductor substrate (hereinafter referred to as area bumps).
The present invention relates to a semiconductor integrated circuit device for supplying power to internal circuits and I / O cells by using.

[0002]

2. Description of the Related Art Recently, a power supply method using area bumps has been proposed as a measure for increasing the number of pins in a semiconductor integrated circuit device. The merit of this power supply method is that power can be directly supplied to the internal circuits and I / O cells from directly above the chip, so that the main power supply line can be made thin. Also, if a package that combines bumps and multilayer wiring is used, LS
Power can be supplied to the internal circuits and I / O cells from any of the substrate surfaces of the I device.

By the way, Japanese Patent Laid-Open No. 5-218204 discloses a standard cell type semiconductor integrated circuit device to which area bumps are applied. According to this device, by arranging bumps one by one on the I / O cell, the bumps approach the I / O cell. Utilizing this fact, a thick wiring is used to connect these portions, and an attempt is made to pass a large current. However, in the standard cell type, the I / O cells are provided in the internal gate region, whereas in the gate array type, the I / O cells are often arranged in the chip peripheral region. This is because when the I / O cell is arranged in the internal gate region, the power supply line and the signal line have to be routed avoiding the memory cell and the logic cell.

FIG. 5 shows a plan view in which the area bump power supply method applied to a standard cell is applied to a gate array. In FIG. 5, 1 is a semiconductor substrate, 2 is an I / O cell arranged in the peripheral region of the semiconductor substrate 1 side by side in the horizontal and vertical directions, and 3 is a power source for I / O which supplies power to the I / O cell 2. Bumps 4 are internal circuits such as memories and logic circuits, and 5 is a power supply bump for logic that supplies power to the internal circuits.

The power supply bumps 3 and 5 are arranged in a matrix, and the pitch of the bumps 3 and 5 is Q1. The arrangement pitch of the I / O cells 2 is Q2, and for example,
Q1 is designed to have a relationship of 2 × Q2. In such a case, as shown in FIG. 5, two power supply bumps 3 are provided every other I / O cell 2, and one power supply bump 3 supplies power to the adjacent I / O cell 2. The other power bump 3 supplies power to the I / O cell directly below.

[0006]

[Problems to be Solved by the Invention] However, I / O
The method of arranging the bumps 3 on the cells 2 to supply power has the following problems. In order to increase the number of pins of the semiconductor integrated circuit device, it is necessary to arrange many I / O cells 2 in the peripheral region of the internal circuit 5. However, as many power bumps 3 as the number of I / O cells 2 are required. become. Further, the width of the I / O cell 2 can be narrowed to some extent by a fine processing technique, but there is a limit to reducing the bump diameter. Therefore, the arrangement pitch Q1 of the power supply bumps 3 cannot be narrowed in proportion to the arrangement pitch Q2 of the I / O cells 2. Therefore, it becomes difficult to arrange the power supply bump 3 for each I / O cell.

Further, when the semiconductor substrate 1 is tested in a wafer state, spherical power supply bumps 3 and 4 are formed.
It is very difficult to apply the probe pin to the. Therefore, a method of providing a test pad may be considered, but I / O
The method of arranging the power supply bumps 3 on the cells requires extra wiring for connecting the power supply bumps 3 and the test pads.

The present invention was created in view of the problems of the conventional example, and it is possible to efficiently supply power to a cell with a small number of bumps without providing bumps on the cell. An object of the present invention is to provide an apparatus and a power supply method thereof.

[0009]

As shown in FIG. 1, a first semiconductor integrated circuit device according to the present invention has an internal circuit, a peripheral circuit surrounding the internal circuit, and a region of the internal circuit. A plurality of first bumps, a plurality of second bumps provided outside the peripheral circuit, and a first wiring connecting the first bump and the second bump to each other. ,
It is characterized in that it is provided with a second wiring that connects between the first wiring and a peripheral circuit.

A second semiconductor integrated circuit device according to the present invention has an embodiment as shown in FIG.
A test pad is provided adjacent to the bump, and the bump is electrically connected to the test pad. In a third semiconductor integrated circuit device of the present invention, as shown in an embodiment thereof, the first wiring is connected to another first bump arranged in the area of the internal circuit. Is characterized by.

In the third semiconductor integrated circuit device of the present invention, preferably, the first wiring is arranged outside the peripheral circuit via another first bump arranged in the area of the internal circuit. It is characterized in that it is connected to the other second bumps. In the first to third semiconductor integrated circuit devices of the present invention, preferably, the first bump is a power supply bump that supplies power to an internal circuit, and the second bump is a power supply that supplies power to a peripheral circuit. It is a bump, and the first wiring and the second wiring are power supply lines.

According to a first power supply method of a semiconductor integrated circuit device of the present invention, an internal circuit is formed on a semiconductor substrate, the internal circuit is surrounded by peripheral circuits, and a plurality of first bumps are provided in a region of the internal circuit. Are arranged, a plurality of second bumps are arranged outside the peripheral circuit, the first bumps and the second bumps are connected by a first wiring, and the first wiring and the first wiring are connected to each other. A second wiring is connected to the peripheral circuit to supply power to the peripheral circuit.

In a second power supply method for a semiconductor integrated circuit device according to the present invention, the first bumps are connected by a third wiring, and the third wiring and an internal circuit are connected by a fourth wiring. Then, the power is supplied. And achieve the above objective.

[0014]

[Operation] In the first semiconductor integrated circuit device of the present invention, a plurality of second bumps are provided outside the peripheral circuit without providing bumps on the peripheral circuit (I / O cell) as in the conventional example. Therefore, power and signals are transmitted from the first wiring connecting the plurality of first bumps provided in the area of the internal circuit to the second bump outside the peripheral circuit to the peripheral circuit through the second wiring. Can be supplied.

For this reason, it is not necessary to dispose the power supply bumps for each peripheral circuit as in the conventional example, so that the disposition pitch of the second bumps does not depend on the disposition pitch of the peripheral circuits, and the disposition pitch of the peripheral circuits becomes smaller. It can be set freely. For example, the arrangement pitch of the peripheral circuits can be reduced to increase the number of peripheral circuits arranged around the area of the internal circuit. If the number of peripheral circuits can be increased, the number of pins of the semiconductor integrated circuit device can be increased.

In the second semiconductor integrated circuit device of the present invention,
Since the test pad is provided adjacent to the first bump or the second bump and the bump is electrically connected to the test pad, the probe pin can be attached to the test pad without touching the bump with the probe pin. The internal circuit and cell can be tested by applying the wafer. In the third semiconductor integrated circuit device of the present invention, since the first wiring is connected to the other first bumps, the power supply is shared between the peripheral circuit and the internal circuit and between the internal circuit and the internal circuit. Available. In addition, since the first wiring is connected to the other second bump via the other first bump, power is supplied to the peripheral circuit and the internal circuit from the two second bumps outside the peripheral circuit. Commonly available.

[0017]

Embodiments of the present invention will now be described with reference to the drawings. 1 to 5 are explanatory views of a semiconductor integrated circuit device and a power supply method thereof according to an embodiment of the present invention. (1) Description of First Embodiment FIG. 1 is a plan view of a gate array according to a first embodiment of the present invention. In FIG. 1, 11 is 15 m on a side
The semiconductor substrate has a square shape of about m and is divided into an internal gate region in which a memory circuit and a logic circuit are formed and a peripheral region in which I / O cells are formed. 12 is a substrate 11
Is an I / O cell arranged side by side in a row in the X and Y directions in a peripheral region surrounding the internal gate region, and is an example of a peripheral circuit. The I / O cell 12 is an interface between an internal circuit such as a memory circuit and a logic circuit and the outside, and in reality, several hundred I / Os are provided for one side of the substrate 11.
Although cells are arranged, in the present embodiment, for convenience of description, 11 I (11 in total) in the X and Y directions (44 in total).
The case where the / O cells are arranged will be described.

Reference numeral 13 is a power source bump for I / O arranged around the outside of the I / O cell 12, and is an example of a first bump. Five power supply bumps 13 are arranged on each side of the peripheral region of the semiconductor substrate 11. Reference numeral 14 is a power supply bump for logic which is arranged so as to face the power supply bump 13 with the I / O cell 12 interposed therebetween, and is an example of a second bump. Power bumps 14 are located within the internal gate region. In the internal gate area, a total of 25 power supply bumps 5 × 5 1
4 are arranged in a matrix form, the power supply bumps 14 near the I / O cells 12 are connected to the power supply bumps 13, and the inner 3 ×
A total of 9 power supply bumps 14 of 3 are separated. Each of the bumps 13 and 14 is formed of spherical Au (gold) or Pb (solder).

Reference numeral 15 is an I / O metal wiring connected between the power supply bumps 13 and 14, and is an example of a first wiring. The metal wiring 15 is formed of metal wiring such as aluminum or aluminum alloy. Metal wiring 15
Is formed, for example, on the uppermost layer of the semiconductor substrate. Reference numeral 16 is a branch wiring connected between the metal wiring 15 and the I / O cell 12, and is formed of a metal wiring like the wiring 14. The wiring 16 is branched from the wiring 15 and the I / O cell 12
In this embodiment, the power is supplied to the 11 I / O cells 12 from the five metal wirings.

For example, when a BGA (ball grid array) package in which power supply bumps 13 and 14 are combined with multilayer wiring is used, a total of 45 power supply bumps 13 and 14 are used.
Since the power is applied all at once, the power can be supplied to the internal circuit and the I / O cell 12 from any of the substrate surfaces of the LSI device. In addition, one I / O metal wiring 15 is
The I / O cell 12 that is connected to the I / O cell 12 directly below through a contact hole and is located above or below
Is connected via a branch wiring 16. The power supply is I through these contact holes and branch wiring 16.
/ O cells and internal circuits (first power supply method). Reference numeral 17 is a signal pad connected to the I / O cell 12 and is an electrode for inputting a signal and outputting a signal.

In FIG. 1, P1 is the arrangement pitch of the bumps 13 and 14, and P2 is the arrangement pitch of the I / O cells 2. In this embodiment, P1 is designed to have a relationship of 2 × P2, but P1 may be 3 × P2. As described above, according to the gate array of the first embodiment of the present invention, the I / O cell 12 is sandwiched between the I / O cells 12 without providing the power source bumps on the I / O cells 12 as in the conventional example. The power supply bump 1 for logic is provided at a position facing the power supply bump 13 for O.
4, the arrangement pitch P2 of the I / O cells 12 can be freely set without depending on the arrangement pitch P1 of the power supply bumps 13 and 14. Further, since power can be supplied from the I / O metal wiring 15 connected between the I / O power bump 13 and the logic power bump 14 to the I / O cell 12 via the branch wiring 16, It is not necessary to dispose a power supply bump for each I / O cell 12 as in the conventional example.
Therefore, compared with the arrangement pitch of the power supply bumps, the I / O cells 1
Since the arrangement pitch of 2 can be made small, the number of I / O cells 12 arranged in the X and Y directions can be increased. Therefore, the number of pins in the gate array can be increased.

As a result, the I / O cell 1 can be formed with a small number of bumps.
It is possible to efficiently supply power to the power supply 2. (2) Description of Second Embodiment FIG. 2 shows a block diagram of a gate array according to a second embodiment of the present invention. In the second embodiment, unlike the first embodiment, a test pad is provided adjacent to the power supply bump 13 for I / O. In FIG. 2, 21 is an I / O
The test pad is provided adjacent to the power supply bump 13 and is electrically connected to the power supply bump 13. The test pad 21 is for contacting the probe pin 22 during a wafer test, and is made of a metal electrode. For the test method in the wafer state, refer to the semiconductor integrated circuit device for which the patent applicant of the present invention has previously applied for a patent (Japanese Patent Laid-Open No. 2-117147).

The test pads 21 may be distributed and installed in each peripheral region of the semiconductor substrate, but in this embodiment, many test pads 21 are arranged in the Y direction as compared with the X direction. This will be described in the third embodiment. The other parts having the same symbols and names as those in the first embodiment have the same functions, and therefore their explanations are omitted. Thus, according to the gate array of the second embodiment of the present invention, as shown in FIG. 2, the test pad 21 is provided adjacent to the power supply bump 13 for I / O. 13 is a test pad 21
Since the probe pin 22 is not electrically applied to the spherical power supply bump, the probe pin 22 is applied to the test pad 21 to supply a voltage, so that the internal circuit and the I / O cell are connected in a wafer state. Twelve can be tested.

In the present embodiment, the case where the test pad 21 is provided adjacent to the power supply bump 13 has been described.
The pads 21 may be provided adjacent to the logic power supply bumps 14. (3) Description of Third Embodiment FIG. 3 shows a block diagram of a gate array according to a third embodiment of the present invention. In the third embodiment, unlike the first embodiment, the I / O power supply bumps 13A, the five logic power supply bumps 14 and the I / O power supply bumps 13B arranged in the X direction are connected to the metal wiring 15 and The metal wires 31 are continuously connected in the lateral direction. The present embodiment is also characterized in that the number of power supply pads 30 with test pads in the Y direction is larger than the number of power supply pads 30 with test pads in the X direction. The metal wires 15 and 31 have many internal circuits and I / Os.
Since the cells are connected, the number of pads 30 in the lateral direction is increased to enhance the power supply capability.

That is, in the gate array of this embodiment,
First, the internal circuit is arranged on the semiconductor substrate 11, and the power supply bump 14 for logic is arranged in the internal gate region. Also,
22 I / O cells 1 in the peripheral area surrounding the internal gate area
2 are arranged side by side, and 20 power supply bumps 13 for I / O are arranged in the peripheral region of the region of the I / O cell 12. Then, the I / O power supply bumps 13A and the logic power supply bumps 14A and the power supply bumps 13A and 14A which are opposed to each other with the I / O cell 12 in between are connected by I / O metal wirings 15, respectively. To do. Furthermore, power supply bump 14A for logic
And power supply bump 14 for 3 logics sandwiched between 14B
Are connected by metal wiring 31.

For example, when the BGA package is used as in the first embodiment, a total of 45 power supply bumps 13 and 1 are provided.
Since power is applied all at once from 4, power is supplied to the internal circuits directly below the power bumps 14 through the contact holes, and to the internal circuits distant from the power bumps 14 from the metal wiring 31. Power can be supplied through the branch wiring 32 (second power supply method).

Thus, according to the gate array of the third embodiment of the present invention, the I / O cell 12 is not provided on the I / O cell 12 unlike the conventional example.
Since the power supply bumps 14A for logic are provided at positions facing the power supply bumps 13A for I / O with the power supply bumps 13 and 14 arranged therebetween, as in the first embodiment.
It does not depend on the arrangement pitch of the / O cells 12. Further, since the power can be supplied from the metal wiring 31 connected to the metal wiring 15 to the internal circuit through the branch wiring 32, the pitch of the logic power supply bumps 14 to be arranged for each internal circuit can be relaxed.

In the third gate array of the present invention,
Since the power supply bumps 14 for logic are continuously connected in the lateral direction by the metal wiring 31, it is possible to commonly use the power supply between the I / O cell 12 and the internal circuit and between the internal circuit and the internal circuit. Compared to the case without metal wiring 31,
Since the wiring resistance of the entire LSI device seen from the substrate surface is reduced, the voltage drop is reduced. Further, by using the BGA package, power can be supplied to the internal circuit and the I / O cell 12 from any of the substrate surfaces of the gate array package.

(4) Description of Fourth Embodiment FIG. 4 shows a block diagram of an area bump bonding type gate array according to a fourth embodiment of the present invention. The fourth embodiment differs from the third embodiment in that the logic power supply bumps 14 arranged in the internal gate region are separated from the other logic power supply bumps 14. In FIG. 4, 40 is a power supply bump for logic, and 25 power supply bumps for logic 1 arranged in the internal gate region.
It is one of four. For example, the power supply bump 40 supplies power to a logic circuit or the like that operates by a high-speed clock signal.

As described above, in the gate array according to the fourth embodiment of the present invention, the power supply bump 40 for supplying power to the logic circuit operating at high speed and the power supply bump 13 for supplying power to the I / O cell 12 are provided. By separating, noise that may be transmitted from the logic circuit to the I / O cell 12 can be prevented. Also, noise that may be transmitted from the I / O cell 12 to the logic circuit can be prevented. This allows logic circuits and I
Since the malfunction of the / O cell 12 can be prevented, the reliability of the gate array can be improved.

[0031]

As described above, in the semiconductor integrated circuit device of the present invention, since the plurality of second bumps are provided outside the peripheral circuit, the plurality of first bumps provided in the area of the internal circuit are provided.
The power supply and the signal can be supplied to the peripheral circuit from the first wiring connecting the bump and the second bump outside the peripheral circuit through the second wiring.

Therefore, it is not necessary to dispose the power supply bumps for each peripheral circuit, and the arrangement pitch of the peripheral circuits can be set freely. Further, since the arrangement pitch of the peripheral circuits can be reduced, the number of peripheral circuits arranged around the internal circuit can be increased, which largely contributes to the increase in the number of pins of the semiconductor integrated circuit device such as the gate array.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a gate array of an area bump bonding system according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a gate array of an area bump bonding method according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a gate array of an area bump bonding method according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a gate array of an area bump bonding system according to a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of an area bump bonding type gate array according to a conventional example.

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... I / O cell, 13 ... I / O power supply bump (first bump), 14, 40 ... Logic power supply bump (second bump), 15 ... I / O use Metal wiring (first wiring), 16, 32 ... Branch wiring (second wiring), 17 ... Pad, 21 ... Test pad, 22 ... Probe pin, 30 ... Power bump with test pad, 31 ... Metal wiring.

Claims (7)

[Claims] 1. An internal circuit, a peripheral circuit surrounding the internal circuit, a plurality of first bumps provided in a region of the internal circuit, and a plurality of second bumps provided outside the peripheral circuit. And a first bump connecting the first bump and the second bump.
And a second wiring connecting the first wiring and a peripheral circuit. 2. The semiconductor integrated device according to claim 1, wherein a test pad is provided adjacent to the first bump or the second bump, and the bump is electrically connected to the test pad. Circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the first wiring is connected to another first bump arranged in the area of the internal circuit. 4. The first wiring is connected to another second bump arranged outside the peripheral circuit via another first bump arranged in the area of the internal circuit. The semiconductor integrated circuit device according to claim 1, wherein 5. The first bumps are power supply bumps for supplying power to an internal circuit, and the second bumps are power supply bumps for supplying power to a peripheral circuit. The wiring is a power supply line.
13. The semiconductor integrated circuit device according to claim 1. 6. An internal circuit is formed on a semiconductor substrate, the internal circuit is surrounded by a peripheral circuit, a plurality of first bumps are arranged in a region of the internal circuit, and a plurality of second bumps are arranged outside the peripheral circuit. Bumps are arranged, the first bump and the second bump are connected by a first wiring, and the first wiring and a peripheral circuit are connected by a second wiring. A method of supplying power to a semiconductor integrated circuit device, comprising supplying power to the peripheral circuit. 7. The power source is supplied by connecting the first bumps with a third wiring and connecting the third wiring with an internal circuit by a fourth wiring. A method for supplying power to the semiconductor integrated circuit device according to claim 1.