JPH08305660A - Data transfer device and programmable controller using this device - Google Patents

Abstract

PURPOSE: To transfer data between a fundamental base and an extended base regardless of the rise of the system clock frequency of the fundamental base. CONSTITUTION: An internal clock 101 outputs the same frequency as the system clock frequency of the fundamental base to a timer 102 and a signal extension circuit 103. The timer 102 has a measurement time corresponding to the rise of the system clock frequency of the fundamental base and starts to measure the time at the time of outputting an address signal (SA0 to SA15) from the fundamental base to the extended base by a CPU and outputs a measurement time end signal (SFA) to the signal extension circuit 103 at the time of elapse of the measurement time. The signal extension circuit 103 outputs the address signal (SA0 to SA15) from the CPU to the extended base as an address signal (ZA0 to ZA15) and stops output of this address signal at the time of receiving the measurement time end signal (SFA) from the timer 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device for transferring data between a basic base and an extension base, and a programmable controller using the data transfer device.

[0002]

2. Description of the Related Art Conventionally, a programmable controller having a multiplex bus structure for transferring an address and data is used as one means for specifying one bus cycle from the output of a read signal to the end of data reading, as a destination. There is one based on a data acknowledge signal (DACK) output from the CPU to the CPU.

That is, as the data acknowledge signal, as shown in FIG. 4, an address signal output in synchronization with the system clock is output to a receiving destination (for example, a memory), and data is read from the receiving destination. ,Also,
When the data is written to the receiving destination, the state of the high level H changes to the state of the low level L, which indicates that the receiving destination is currently reading or writing the data.

Thereafter, this data acknowledge signal is
When the reading or writing of the data from the receiving end is completed, the state of the low level L changes to the high level H again, indicating that the reading or writing of the data at the receiving end is completed. 1 bus cycle of is specified.

[0005]

However, in such a conventional programmable controller having a multiplexed bus structure, the address transmission time is defined by the system clock. Therefore, when the system clock becomes faster, the address time becomes longer. However, there was a problem that the data could not be transferred to the extension destination when the bus was shortened and the bus was extended with a cable.

Explaining the above in detail, as shown in FIG. 5, the extension base 2 has a maximum allowable transmission frequency of 20M.
When the frequency of the system clock in the basic base 1 is increased from 20 MHz to 50 MHz when the cable 3 of Hz is connected to the basic base 1, for example, when the cable 3 can only transmit a signal with a frequency up to 20 MHz. Cannot transmit a signal from the basic base 1 to the extension base 2.

Therefore, the present invention has been made in view of the above problems.
An object of the present invention is to provide a data transfer device that enables data transfer between the basic base and the extension base even if the system clock of the basic base increases, and a programmable controller using the data transfer device.

[0008]

In order to achieve the above object, the invention according to claim 1 is a data transfer apparatus for transferring data between a basic base and an extension base, wherein a system clock frequency of the basic base is set. Against the increase
It is characterized by further comprising holding means for holding the transfer time of the address signal output to the extension base at a fixed time.

According to a second aspect of the present invention, in the first aspect of the present invention, the holding means is provided on the basic base and has a measurement time based on an increase in the system clock frequency of the basic base. When an address signal is output from the basic base to the extension base, the measuring time is started after a predetermined time, and when the measuring time elapses, a measuring means for outputting a measuring time end signal and the address signal are input. And an address signal extension means for extending and outputting the address signal to the extension base until receiving the measurement time end signal from the measurement means.

The invention according to claim 3 is the invention according to claim 1 or 2.
In the invention described above, the holding means is provided with an internal clock for outputting a frequency equivalent to the system clock frequency of the basic base to the measuring means and the address signal extending means.

According to a fourth aspect of the invention, the programmable controller is provided with the data transfer device according to the first to third aspects.

A fifth aspect of the present invention is characterized in that, in the fourth aspect of the invention, there is provided a multiplex bus used as an address bus and a data bus.

[0013]

According to the present invention, since the transfer time of the address signal output to the extension base is held constant by the holding means with respect to the increase of the system clock frequency of the basic base, even with the increase of the system clock frequency Data transfer is possible.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data transfer device according to the present invention and a programmable controller using the data transfer device will be described below with reference to the drawings.

FIG. 1 is a diagram showing the outline of an embodiment of a programmable controller using the data transfer device according to the present invention.

As shown in the figure, the programmable controller of this embodiment is constructed by connecting a base 1 and an extension base 2 with a cable 3. The basic base 1 is the data transfer device 1 according to the embodiment of the present invention.
0, a CPU 11, an address bus, and a multiplex bus 12 used as a data bus. The multiplex bus 12 has a data transfer device 1
0 and the CPU 11 are connected. In addition, cable 3
Cannot be transmitted above a predetermined limit transmission frequency.

As shown in FIG. 2, the data transfer device 10 comprises an internal clock 101, a timer 102, and a signal extension circuit 103.

Here, the internal clock 101 is the timer 1
02 and the signal extension circuit 103, a frequency equivalent to the system clock frequency of the basic base 1 is output.

The timer 102 is, for example, 20 MHz to 50 MHz when the limit transmission frequency of the cable 3 is exceeded.
When it is increased to MHz, the difference has a measurement time corresponding to the frequency of 30 MHz. Then, the timer 102
After a predetermined time elapses after the address signal is output from the basic base 1 to the extension base 2, the CPU 1
When receiving the strobe signal (SAS) (running the timer 102) from 1, the time starts to be measured in synchronization with the clock frequency of the internal clock 101, and when the above-mentioned measurement time elapses, the signal extension circuit 103 measures it. A time end signal (SFA) is output.

The signal extension circuit 103 is interposed between the multiplex bus 12 and the control line 13 connected to the CPU 11 and the extension base 2. Here, the control line 13
Is a read signal (/ SREAD) that is a strobe signal for reading data from a memory (not shown).
Also, a write signal (/ SWRITE), which is a strobe signal for writing data to a memory or the like, is transmitted.

The signal extension circuit 103 receives the address value of the data to be read from the data stored in the memory or the like as an address signal (SA0 to 15) via the multiplex bus 12, Until the measurement time end signal (SFA) is received from the timer 102, the address signals (SA0 to 15) are output to the extension base 2 as address signals (ZA0 to 15).

Next, the operation of the data transfer device and the programmable controller using the data transfer device will be described.

FIG. 3 is a timing chart for explaining the operation of data transfer between the memories connected to the basic base and the extension base 2.

When the CPU 11 of the basic base starts to output the read signal (/ SREAD) to the data transfer device 10 in order to read the data stored in the memory (not shown) connected to the extension base 2 (see FIG. 3), the signal extension circuit 103 constituting the data transfer device 10 sends a read signal (/ ZR) to the extension base 2.
EAD) is started to be output (see the part in FIG. 3).

Subsequently, the CPU 11 sends an address signal (SA0-SA0) indicating the address address of the data read from the memory.
15) is started to be output to the data transfer device 10 (see the part in FIG. 3).

Then, the data transfer device 10 starts to output the address signals (ZA0 to 15) in order to read the data recorded in the memory connected to the extension base 2 from the built-in signal extension circuit 103 (Fig. Refer to the section in 3).

Thereafter, the CPU 11 causes the address signal (S
Strobe signal (/ SA
S) is started to be output (see the part in FIG. 3).

When the data transfer device 10 receives a strobe signal (/ SAS) from the CPU 11, the data transfer device 1
The timer 102 built in 0 has an internal clock 10
Based on the synchronization of the clock frequency of 1, when the time starts to be measured and the above-described measurement time T1 elapses, a measurement time end signal (SFA) (not shown) is output to the signal extension circuit 103.

Upon receiving the measurement time end signal (SFA), the signal extension circuit 103 stops the output of the address signals (ZA0 to 15) output to the extension base 2 and outputs the read signal (/ ZREAD). Also stop.

Therefore, the output period of the address signal output from the basic base 1 to the extension base 2 is extended by the time T2.

The signal extension circuit 103 continues to output the strobe signal (/ ZAS) to the extension base 2 while outputting the address signals (/ ZA0 to 15) (FIG. 3).
See the section in).

The signal extension circuit 103 stops outputting the address signals (ZA0 to 15) output to the extension base 2 and the memory access time (M in FIG. 3) required for the memory to read the data. Data) is read from the memory connected to the extension base 2 via the extension base 2 as a data signal (ZD0 to 15) (see the location in FIG. 3).

The signal extension circuit 103 outputs the read data signals (ZD0 to 15) to the CPU 11 as data signals (SD0 to 15) (see the part in FIG. 3).

Here, the CPU 11 receives the data acknowledge signal (/ SACK) from the memory while it is receiving the data from the memory 11 (it is in the state of low level L) (the part in FIG. 3). reference).

When the data acknowledge signal (/ SACK) becomes high level H, the CPU 11 determines that one bus cycle is completed, and the strobe signal (/ S
The output of AS) is stopped, and the read signal (/ SREAD) is output to enter the next bus cycle. After that, when it becomes necessary to transfer data to the unit connected to the extension base again, the basic base 1 transfers data between the units in the same manner as described above.

[0036]

According to the invention described above, in the present invention, the transfer time of the address signal output to the extension base is held constant by the holding means with respect to the increase of the system clock frequency of the base. It is possible to enable data transfer between the base and the extension base even if the system clock frequency of the base is increased.

Therefore, when operating at the low speed system clock frequency, it operates at the same speed on the basic base, and when operating at the high speed system clock frequency, it operates at high speed on the basic base. , In the extension base, it is not necessary to be aware of speed switching at all, and it can operate at the same speed as at low speed.

If the architecture of the transfer destination is adapted to high speed, it can be used without distinction from low speed to high speed.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing an embodiment of a programmable controller according to the present invention.

FIG. 2 is a block diagram showing the configuration of a data transfer device in FIG.

FIG. 3 is a timing chart for data transfer between memories connected to the basic base and the extension base 2.

FIG. 4 is a timing chart on a multiplexer bus in a conventional data transfer device.

FIG. 5 is a schematic view of a conventional base and extension base.

[Explanation of symbols]

 1 Basic Base 2 Extension Base 3 Cable 10 Data Transfer Device 11 CPU 12 Multiplexer Bus 101 Internal Clock 102 Timer 103 Signal Extension Circuit

Claims (5)

[Claims] 1. A data transfer device for transferring data between a basic base and an extension base, wherein a transfer time of an address signal output to the extension base is constant with respect to an increase in the system clock frequency of the basic base. A data transfer device comprising a holding means for holding time. 2. The holding means is provided on the basic base, has a measurement time based on an increase in the system clock frequency of the basic base, and outputs an address signal from the basic base to the extension base. Then, after the predetermined time has elapsed, the measurement time starts to be measured, and when this measurement time elapses, a measurement means that outputs a measurement time end signal, and after the address signal is input, receive the measurement time end signal from the measurement means. 2. The data transfer apparatus according to claim 1, further comprising address signal extension means for extending and outputting the address signal to the extension base. 3. The holding means, with respect to the measuring means and the address signal extending means,
The data transfer apparatus according to claim 1 or 2, further comprising an internal clock that outputs a frequency equivalent to the system clock frequency of the basic base. 4. A programmable controller comprising the data transfer device according to claim 1. 5. The programmable controller according to claim 4, further comprising a multiplexed bus used as an address bus and a data bus.