JPH08305586A - Microcomputer - Google Patents

Abstract

PURPOSE: To provide the microcomputer in which a transition time to program processing based on an interrupt request can be reduced. CONSTITUTION: Operand data stored in a stack memory 10 are applied to one input of an arithmetic logic unit 13 and other operand data stored in a register 11 are fed to the other input of an arithmetic unit 13, and an arithmetic output of the arithmetic logic unit 13 is stored again in the register 11. Thus, even on the occurrence of an interruption request, only the content of the register 11 has only to be saved tentatively to the stack memory 10 and the time when interruption processing is transited can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer configuration suitable for efficiently executing interrupt processing.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a configuration of a conventional microcomputer. In FIG. 3, (1) is a ROM, and a plurality of program data DATA for controlling the operation of the microcomputer are stored in advance at a plurality of addresses assigned to the storage area of the ROM (1). Is. Reference numeral (2) is a control circuit, which outputs address data ADD for accessing the address of the ROM (1) corresponding to each case, and is read from the address of the ROM (1) corresponding to the address data ADD. The program data DATA is fetched and decoded, and the operation of the microcomputer is controlled based on the decoding result. (3) and (4) are n-bit registers,
The control output of the control circuit (2) controls the data holding operation. For example, it is assumed that the register (3) and the register (4) hold n-bit data of the counters CTR1 and CTR2, each of which has a predetermined count value, via the data bus (5). The data set in the registers (3) and (4) is the counter C.
Not limited to the count values of TR1 and CTR2, but two types of n-bit data to be operated are input ports (not shown)
Via the computer to the inside of the microcomputer,
The n-bit data of a kind may be held in the registers (3) and (4) via the data bus (5), that is, any data can be set in the registers (3) and (4). Even the target. (6) is an arithmetic logic unit, which performs a predetermined logical operation (addition, subtraction, etc.) on each n-bit data held in the registers (3) and (4),
The n-bit data obtained as a result is held in one register (3) again.

The microcomputer is generally constructed as described above. Here, if an interrupt request occurs due to some factor during the execution of the main program for performing a logical operation on the contents of the registers (3) and (4), Instead of executing the main program, a subroutine program based on the interrupt request must be executed. Therefore, it is necessary to suspend the processing of the main program until it is executed, and temporarily save the processing data based on the main program until the subroutine program ends. Specifically, a stack memory (7) is provided, and when the interrupt request occurs, the stack memory (7) is controlled by the control signal of the control circuit (2), and the stack area STACK1 of the stack memory (7) is controlled. In STACK2 and STACK2, the values of the registers (3) and (4) at the time of interruption of the main program are temporarily saved via the data bus (5). Thus, the registers (3) (4) and the arithmetic logic unit (6)
Subroutine processing can be executed using. The subroutine processing is executed by the control circuit (2) accessing the address of the ROM (1) specified by the interrupt request, that is, jumping from the address at the time of executing the main program to the address at which the subroutine program processing is performed. .

[0004]

However, it is necessary to temporarily save the contents of both the registers (3) and (4) in the stack area of the stack memory (7) at the time of transition from the main program to the subroutine program based on the interrupt request. Therefore, there is a problem that it takes a long time to temporarily save, and as a result, the interrupt processing time becomes long.

Therefore, an object of the present invention is to provide a microcomputer capable of shortening the transition time to program processing based on an interrupt request.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that a micro-processor for performing a predetermined operation on two operand data according to a program instruction. In a computer, a temporary save memory holding one operated data, a register holding the other operated data, and one operated data held in the temporary saved memory are applied to one input. Along with the other input, the other operated data held in the register is applied, and an arithmetic logic unit for holding again the result of performing a predetermined operation on both operated data in the register, When an interrupt request occurs, only the contents held in the register are temporarily saved in the temporary save memory, and the program processing based on the interrupt request can be executed. Was the point.

[0007]

According to the present invention, one input of the operation logic unit held in the temporary save memory is applied to one input of the operation logic unit, and the other input of the operation logic unit is held in the register. The other processed data is applied, and the operation output of the operation logic unit is held in the register again. Therefore, even if an interrupt request occurs, only the contents of the register need only be temporarily saved in the temporary save memory, and the time required to shift to interrupt processing can be shortened.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a first embodiment of the microcomputer of the present invention. In FIG. 1, (8) is a ROM (memory) in which program instructions for operating the microcomputer in a main routine or a subroutine are stored. (9) is a control circuit, ROM (8)
Between the control circuit (9) and the control circuit (9), when the control circuit (9) outputs the address data ADD, the corresponding address of the ROM (8) is accessed and read from the corresponding address of the ROM (9). The program data DATA is decoded by the control circuit (9), and the operation of the microcomputer is controlled based on the decoding result. Reference numeral (10) is a stack memory (temporary save memory), which has a function of holding one processed data to be operated by an operation logic unit described later. The stack memory (10) has a function of temporarily saving the temporary save operation by the control output of the control circuit (9) and temporarily saving the address information immediately after the main program is interrupted in a predetermined hierarchy of the stack area. There is. Reference numeral (11) is an n-bit register, which holds the other operated data to be operated by the operation logic unit. The register (11) is in a state where the data holding operation can be performed by the control output of the control circuit (9).

Here, in the stack area STACK1 of the stack memory (10) and the register (11), counters CTR1 and CTR2 having predetermined count values are provided.
It is assumed that the n-bit data of is held via the data bus (12). The data held in both are not limited to the count values of the counters CTR1 and CTR2, and two types of n-bit data to be calculated are fetched into the microcomputer via an input port (not shown), Data bus for two types of n-bit data (12)
May be held in both sides via, ie any data can be held as long as it can be held in both sides.

Numeral (13) is an arithmetic logic unit, one input of which is directly connected to the stack memory (10), that is, one operand data is directly applied to one input. Further, the other input of the arithmetic logic unit (13) is directly connected to the output of the register (11) so that the other operated data is directly applied. Further, the n-bit operation result (addition, subtraction, etc.) performed by the operation logic unit (13) on both operand data is held in the register (11) again.

In the microcomputer configured as described above, during execution of the main program, particularly during execution of arithmetic processing in the arithmetic logic unit (13) by using the value of the register (11), it is caused by some factor. When an interrupt request occurs, only the value of the register (11) is temporarily saved in the stack memory (10), the main program is temporarily interrupted, and execution of subroutine processing based on the interrupt request can be performed. Specifically, since one of the operated data has already been read from the stack memory (10), the operation result held in the register (11) is temporarily saved in the stack area STACK1 of the stack memory (10). Good. That is, only the value of one register (11) needs to be temporarily saved.

Even if a number of sub-routine processes based on interrupt requests are overlapped, only the value of the register (11) needs to be temporarily saved in the stack memory (10). It can run fast. 2 is a diagram showing a second embodiment of the present invention. 1 and 2, the same components are designated by the same reference numerals, and the description thereof will be omitted. A structural difference from FIG. 1 is that the arithmetic logic unit (14) has temporary registers T1 and T2 having a latch function at both inputs. As a result, the operation of FIGS. 1 and 2 differs in the following points. That is, in the case of FIG. 1, both the processed data held in the stack area STACK1 of the stack memory (10) and the register (11) are directly applied to the arithmetic logic unit (13), and further the arithmetic logic unit ( The calculation result of 13) is directly registered in the register (1
1), but the structure shown in FIG.
Then, the stack area STAC of the stack memory (10)
Both the data to be operated held in K1 and the register (11) are once held in the temporary registers T1 and T2 of the operation logic unit (14) via the data bus (12), and then the operation is performed to obtain the result. The calculation result thus obtained is again held in the register (11) via the data bus (12). In FIG. 1, the stack memory (10) and the register (11) are shown as arithmetic logic units (1
Since it is directly connected to 3), there is an advantage that the calculation speed is increased, and in FIG. 2, there is an advantage that the connection line between each configuration and the data bus (12) can be shortened.

[0013]

According to the present invention, one operated data is held in the temporary save memory and applied to the arithmetic logic unit. Therefore, even when an interrupt request occurs, the other operated data or operation is performed. Only the value of the one register that holds the processed data need only be saved in the temporary save memory, and there is an advantage that the transition time to the program processing based on the interrupt request can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a microcomputer of the present invention.

FIG. 2 is a diagram showing a second embodiment of the microcomputer of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional microcomputer.

[Explanation of symbols]

 (10) Stack memory (11) Register (13) Arithmetic logic unit

Claims (2)

[Claims] 1. A microcomputer for performing a predetermined operation on two operand data according to a program instruction, a temporary save memory for retaining one operand data, a register for retaining the other operand data, and One of the operated data held in the temporary saving memory is applied to the input of the other and the other operated data held in the register is applied to the other input, and a predetermined value is applied to both of the operated data. An arithmetic logic unit for holding the result of the operation again in the register, when an interrupt request occurs, only the contents held in the register are temporarily saved in the temporary save memory, and the program processing based on the interrupt request is executed. A microcomputer characterized in that it is possible. 2. A control circuit for accessing a memory storing a program command to decode the program command read from the memory, wherein the temporary save memory, the control circuit, based on the decoding result of the program command of the control circuit. 2. The microcomputer according to claim 1, which controls operations of a register and the arithmetic logic unit.