JPH0830240A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide a liquid crystal display device capable of improving display dignity by preventing the occurrence of a difference between potential of pixel electrodes due to a delay of a signal in a scanning line or a data line and realizing the prevention of the occurrence of the difference between the potential regardless of a structure of a switching element. CONSTITUTION:A scan driver circuit 5 outputs a scanning signal to respective scanning lines 9 successively. Further, a segment driver circuit 4 samples an inputted video data signal and outputs the video data signal by one horizontal scanning line to respective data lines 8. The video data signal is inputted to a signal processing circuit 12 for the segment driver circuit 4 of the poststage. The video data signal of which polarity is inverted at every one horizontal scanning is inputted to an addition circuit 28. The signal controlling a correction signal generation circuit 27, the segment driver circuit 4, the scan driver circuit 5 and a counter voltage impressing circuit 6 is formed in a driver output control circuit 13 to be inputted to respective circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device used for displaying television images and the like.

[0002]

2. Description of the Related Art FIG. 9 and FIG. 10 are block diagrams showing the structure of a liquid crystal display device according to a first prior art active matrix system. FIG. 9 is a block diagram showing the entire electrical configuration of the liquid crystal display device, and FIG. 10 is an equivalent circuit diagram of one pixel 15 in the display panel 14 of FIG. A liquid crystal panel 14 of this liquid crystal display device has a structure in which a liquid crystal layer 3 is arranged between a pixel electrode substrate 1 and a counter electrode substrate 2. A plurality of scan lines 9 parallel to each other and a plurality of data lines 8 parallel to each other extending in a direction perpendicular to the scan lines 9 are formed on the pixel electrode substrate 1. Furthermore, at the intersection of the plurality of scan lines 9 and the plurality of data lines 8,
Each TFT (thin film transistor) 7 is arranged, the scanning line 9 is connected to the gate of the TFT 7, and the data line 8 is connected to the input end of the TFT 7. Each scan line 9
The pixel electrodes 10 are connected to the respective data lines 8 via TFTs 7 in a matrix. A counter electrode 11 is formed on the entire surface of the counter electrode substrate 2 facing the pixel electrode substrate 1. The pixel electrode 1
0, the portion of the counter electrode 11 corresponding to the pixel electrode 10, and the liquid crystal layer 3 sandwiched between the pixel electrode 10 and the portion of the counter electrode 11, the pixel 15 is configured.

The pixel electrode 10 in the liquid crystal panel 14
Each upper scan line 9 is connected to the scan driver circuit 5. The scan driver circuit 5 includes a shift register, and the shift register sequentially outputs a scan signal to each scan line 9. Further, each data line 8 on the pixel electrode substrate 1 is connected to the segment driver circuit 4. The segment driver circuit 4 is a circuit that samples a video data signal input from the outside and outputs a video data signal for one horizontal scanning line to each data line 8. Then, a counter voltage serving as a reference of the signal potential of the video data signal is applied to the counter electrode 11 by a counter voltage application circuit 6.
Is always applied by.

A signal processing circuit 12 performs signal processing such as inversion of signal polarity on the video data signal of the NTSC system or the like input from the outside every horizontal scanning and vertical scanning of the video data signal. . The circuit operation of the segment driver circuit 4, the counter voltage applying circuit 6, and the scan driver circuit 5 is controlled by a driver output control circuit 13.

The scanning signal applied from the scanning driver circuit 5 to the gate of the TFT 7 through the scanning line 9 causes T
ON / OFF of FT7 is controlled. The scanning signal is a pulse signal, and when the signal level changes from the L (Low) level to the H (High) level, the TFT 7 is turned on and the video data signal is applied from the data line 8 to the pixel electrode 10 through the TFT 7. . After the video data signal is input, the potential of the pixel electrode 10 becomes the same as the signal potential of the video data signal supplied from the data line 8. After that, when the scanning signal changes from H level to L level, the TFT 7
Is turned off. When the TFT 7 is turned off, the pixel electrode 10
The electric potential of is decreased a little. This decrease in potential is called pull-in. As shown in FIG. 10, this phenomenon is caused by a part of the charges supplied based on the video data signal applied to the pixel electrode 10 in a portion corresponding to the pixel 15 in the liquid crystal layer.
This is because it is absorbed by the parasitic capacitance formed between the scan line 9 and the pixel electrode 10. The slightly lowered pixel electrode 10
The potential of is then held at a constant potential.

On the other hand, when the liquid crystal is driven by direct current, the life of the liquid crystal is shortened. Therefore, conventionally, the polarity of the video data signal is inverted every vertical scanning period, and the video data is also scanned every horizontal scanning period to make flicker hard to see. The polarity of the signal is reversed to drive the liquid crystal in an alternating current. The signal processing circuit 12 performs such video data signal processing.

However, as the liquid crystal display device becomes larger in size and higher in definition, the line lengths of the scanning lines 9 and the data lines 8 become longer, and the line resistance accordingly increases. In addition, the parasitic capacitance between the scanning line 9 and the data line 8 and the counter electrode 11 is increased with the liquid crystal layer 3 interposed therebetween. At this time, as the scanning signal progresses on the scanning line 9 or the video data signal progresses on the data line 8, the scanning line 9
And the line resistance of the data line 8 increases. Also,
The time constant of the parasitic capacitance for the scan line 9 and the data line 8 becomes large. As a result, the delay of the scan signal or the video data signal gradually increases. The increase of the delay of the scanning signal is caused by the pixel electrode 1 after the TFT 7 is turned off.
The amount of pulling in the potential of 0 is gradually decreased. That is, this pull-in amount gradually decreases in the range from the end of each scan line 9 closest to the scan driver circuit 5 to the end farthest from the scan driver circuit 5. Such a difference in the pull-in amount in the same horizontal scanning period causes a difference in image density, which causes a display defect as flicker.

As a countermeasure against the above-mentioned delay of the scanning signal which causes such a problem, a flat panel display 1992 (published by Nikkei BP, edited by Nikkei Microdevices, published on November 19, 1991), page 160 and after. A publicly known technology for manufacturing a liquid crystal display device by a self-alignment method is known.

Here, the scanning signal line is formed of a low resistance material such as aluminum, or the parasitic capacitance generated between the gate electrode and the drain electrode of the TFT is reduced.
That method is described.

In the method of forming the scanning signal line with a low resistance material, when manufacturing a large display panel of 8 inches or more, the effect of the low resistance is hardly obtained due to the phenomenon of the increase of the line resistance.

Further, as a method of reducing the parasitic capacitance generated in the TFT, an auxiliary capacitance is provided in order to absorb the adverse display effect of the parasitic capacitance on the display section. On the other hand, this auxiliary capacitance also causes another problem of reducing the aperture ratio of the liquid crystal display device. Therefore, in the above-mentioned document, in view of increasing the aperture ratio, it is said that the so-called self-aligned TFT using the gate electrode as a photomask can reduce the flicker. According to this, it is possible to reduce the overlap between the gate electrode and the drain electrode, and thus to reliably reduce the parasitic capacitance.

The second conventional technique will be described below.
FIG. 11 shows a partial sectional view of a liquid crystal display device of the second prior art active matrix system, and FIG. 12 shows a system diagram of the liquid crystal display device. The liquid crystal panel of this liquid crystal display device has a structure in which a liquid crystal layer 18 is arranged between a pixel electrode substrate 21 and a counter electrode substrate 22. Pixel electrode substrate 2
As shown in FIG. 11, 1 has a plurality of pixel electrodes 10 formed in a matrix on an insulating substrate 20. Further, as shown in FIG. 12, the pixel electrode substrate 21 has a plurality of scanning lines 9 and data lines 8 formed on the insulating substrate 20, and at each intersection of the plurality of scanning lines 9 and the plurality of data lines 8. The TFTs 7 are arranged in a matrix. Pixel electrodes 10 are arranged at the respective intersections. The counter electrode substrate 22 shown in FIG.
The counter electrode 11 is formed on the surface facing the pixel electrode substrate 21.

Each scanning line 9 of the pixel electrode 21 in the liquid crystal panel is connected to the scanning driver circuit 5 shown in FIG. The scan driver circuit 5 includes a shift register, and the shift register sequentially outputs a scan signal to each scan line 9. Further, each data line 8 of the pixel electrode substrate 21 is connected to the segment driver circuit 4. The segment driver circuit 4 is a circuit that samples a video data signal and outputs a video data signal for one horizontal scanning line to each data line 8. Then, a counter voltage as a reference of the video data signal is applied to the counter electrode substrate 22 by a counter voltage application circuit (not shown).

The timing of each operation of the segment driver circuit 4 is controlled by the segment driver control circuit 23 based on the sync signal separated from the video data signal by the sync separation circuit 25. The timing of each operation of the scan driver circuit 5 is as follows.
It is controlled by the scan driver control circuit 24 based on the synchronization signal.

Also in the second prior art, the signal delay due to the line resistance and the capacitance is increased when the signal travels through the data line 8 and the scanning line 9 as described in the first prior art. Phenomenon occurs.

[0016]

In the second prior art, there is a problem that the ON / OFF timing of the TFT 7 is shifted due to the signal delay and the potential of the pixel electrode 10 does not reach the potential that it should originally reach. . This defective phenomenon will be described with reference to FIGS. 12 and 14. 12
The scanning signal, the data signal, and the potential of the pixel electrode 10 when the signal delay does not occur at are the scanning signal potential V (Y1), the data signal potential V (X1), and the pixel electrode potential V (Y1, X1), respectively. And Here, the data signal potential V
(X1) and the pixel electrode potential V (Y1, X1) are, for example, a ground potential and a predetermined potential Vs at L level and H level, respectively. Further, the scanning signal, the data signal, and the potential of the pixel electrode 10 when the signal delay occurs are set to the scanning signal potential V (Ym) and the data signal potential V, respectively.
(Xn) and pixel electrode potential V (Ym, Xn). The ON / OFF timing of the TFT 7 is determined by the rising timing and the falling timing of the scanning signal.

When there is no signal delay, the scanning signal causes TF.
As T7 turns on, the potential of the pixel electrode 10 rises to the potential Vs of the data signal. When the TFT 7 is turned off, the potential of the pixel electrode 1 is maintained as it is. The signal potential V
When there is a signal delay in (Ym) and V (Xn), the pixel electrode potential V (Ym, Xn) starts to rise with the input of the scanning signal potential V (Ym) to the TFT 7. T
When the FT7 is turned off, the data signal potential V (Xn) does not rise to the potential Vs due to the signal delay, the above-mentioned voltage pull-in occurs, and the potential becomes Vs-ΔV. As a result, the potential of the pixel electrode 10 also becomes the potential (Vs-ΔV).

As described above, in the display panel, the potential difference −ΔV is generated in the pixel electrodes 10 at the positions distant from each other in the horizontal scanning direction, so that the display has a difference in brightness and darkness.
There is a problem that it causes a display defect that causes display unevenness. The potential difference −ΔV becomes larger as the video data signal advances along the data line 8.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a plurality of pixel electrodes connected to the same scan line or data line in a scan line or a data line. A liquid crystal display device capable of improving the display quality by preventing the occurrence of the potential difference of the pixel electrodes due to the delay of the signal, and realizing the prevention of the above potential difference regardless of the structure of the switching element. Is to provide.

[0020]

According to another aspect of the present invention, a liquid crystal display device has a plurality of pixel electrodes connected to a plurality of data lines through switching elements whose switching states are controlled by scanning signals through the scanning lines. A liquid crystal display device in which counter electrodes facing each other with a liquid crystal layer sandwiched between the plurality of pixel electrodes are provided, and a scan driving unit that sequentially outputs a scan signal to each scan line to make each switching element conductive. And a data driving means for sequentially outputting a video data signal to each pixel electrode through the plurality of data lines, and a decrease in the pixel electrode potential when the switching element is cut off due to a signal delay in the data line. A correction signal generator that generates a correction signal whose potential decreases by a predetermined potential difference over the vertical scanning period in order to correct the fluctuation of the amount. And a superimposing means for superimposing the video signal applied to the pixel electrode and the correction signal and outputting the superposed signal to the data driving means, whereby the above object can be achieved. it can.

According to the first aspect of the present invention, the predetermined potential difference of the correction signal generated by the correction signal generating means is the pixel electrode potential at a portion of the data line where the signal delay does not occur. The first potential decrease amount,
The second of the pixel electrode potential at the portion where the signal delay occurs
It may be defined as the difference from the potential decrease amount.

According to another aspect of the liquid crystal display device of the present invention, the plurality of pixel electrodes are connected to the plurality of data lines through the switching elements whose switching states are controlled by the scanning signals transmitted through the scanning lines. A liquid crystal display device in which opposite electrodes facing each other with a liquid crystal layer sandwiched between the pixel electrodes are provided with scan driving means for sequentially outputting a scan signal to each scan line to conduct each switching element, and the plurality of data. A data driving means for sequentially outputting a video data signal to each pixel electrode via a line, and a variation in a decrease amount of the pixel electrode potential when the switching element is cut off, which is generated based on a signal delay in the data line, is corrected. Therefore, a correction signal generating means for generating a correction signal whose potential increases by a predetermined potential difference over the vertical scanning period, and the pixel electrode Superimposes the video signal and the correction signal applied, the superimposed signal and a superimposing means for outputting to the data driving unit, it is possible to achieve the above object by its.

In the invention of claim 3, the potential difference of the correction signal for each data line may be selected to be equal to the amount of decrease in the pixel electrode potential when the switching element in the data line is shut off. is there.

In the liquid crystal display device according to any one of claims 1 and 3, a plurality of the correction signal generating means are provided, and a part of the correction signal generating means is one of a part of the plurality of data lines. The residual correction signal generating means is connected to the side end portion, and the residual correction signal generating means is connected to the other side end portions of the residual data lines of the plurality of data lines, respectively, and the partial correction signal generating means and the residual correction signal generating means are Data signals may be output to the respective data lines in mutually opposite directions.

[0025]

According to the first aspect of the present invention, the correction signal generating means generates a correction signal whose potential decreases by a predetermined potential difference over the vertical scanning period. The superimposing means superimposes the video signal applied to the pixel electrode and the correction signal on a horizontal scanning period basis, and the superimposed signal is output to the data driving means. The data driving unit sequentially outputs the video data signal to each pixel electrode via the plurality of data lines. A plurality of pixel electrodes are connected to each data line, and the plurality of pixel electrodes are connected to a plurality of data lines via switching elements, whereby the video data signal is output to each pixel electrode. The switching state of the switching element is controlled by the scanning signal from the scanning driving means via the scanning line.

Here, when the switching element is turned on, electric charges are accumulated in the structure including the pixel electrode, the counter electrode, and the liquid crystal layer sandwiched between these electrodes, and the electric charge is held when the switching element is cut off. When the switching element is cut off, a part of the accumulated charge moves to the parasitic capacitance formed by including the scan line and the pixel electrode, and the potential of the pixel electrode is different from the case where the parasitic capacitance does not exist. Will decrease. Also, when the signal gradually progresses through the scan line,
The line resistance of the scan line increases as the signal progresses. Therefore, the signal delay becomes progressively larger as the signal progressively progresses through the scan line. As a result, the decrease amount of the pixel electrode potential gradually decreases. That is, as the scan signal advances along the scan line, the potential when the switching elements of the plurality of pixel electrodes connected to the same scan line are cut off gradually increases.

According to the present invention, the potential of the correction signal to be superimposed on the video signal in the superimposing means is reduced by a predetermined potential difference over the vertical scanning period. Therefore, the potential of the superimposed signal is also vertically scanned. Decrease over time. As a result, the increase in the pixel electrode potential described above is suppressed. Accordingly, when a display is performed by a signal in which the video signal and the correction signal are superimposed, even if the scanning signal is delayed, the scanning signal is connected to the same scanning line as the scanning signal advances along the scanning line. A phenomenon in which the potentials when the switching elements of a plurality of pixel electrodes are cut off is gradually suppressed, flicker based on this phenomenon is prevented from occurring, and display quality is significantly improved.

According to the invention of claim 2, the predetermined potential difference of the correction signal in the invention of claim 1 is defined as a difference between the first potential decrease amount and the second potential decrease amount. Thus, by using the correction signal, the potential when the switching element of the pixel electrode is cut off can be made constant. Thereby, the display quality is further improved.

According to the third aspect of the invention, the correction signal generating means generates the correction signal whose potential increases by the predetermined potential difference over the vertical scanning period. The superimposing means superimposes the video signal applied to the pixel electrode and the correction signal on a horizontal scanning period basis, and the superimposed signal is output to the data driving means. The data driving unit sequentially outputs the video data signal to each pixel electrode via the plurality of data lines. A plurality of pixel electrodes are connected to each data line, and a plurality of pixel electrodes are connected to a plurality of data lines via switching elements, so that the video data signal is input to each pixel electrode. The switching state of the switching element is controlled by the scanning signal from the scanning driving means via the scanning line.

Here, when the switching element is conducting, electric charge is accumulated in the structure including the pixel electrode, the counter electrode and the liquid crystal layer sandwiched therebetween, and the electric charge is held when the switching element is cut off. When the switching element is turned on, the amount of charge accumulated in the capacitor including the scan line and the pixel electrode is reduced due to the signal delay in the scan line as compared with the case where there is no signal delay. To do. That is, the potential of the pixel electrode decreases due to the delay of the scanning signal. Also, the signal delay becomes progressively larger as the signal progressively advances through the scan line. As a result, the pixel electrode potential gradually decreases. That is, as the scan signal advances along the scan line, the potential when the switching elements of the plurality of pixel electrodes connected to the same scan line are cut off gradually.

In the present invention, the potential of the correction signal superimposed on the video signal by the superimposing means is increased by a predetermined potential difference over the vertical scanning period. As a result, the potential of the superimposed signal also increases over the vertical scanning period. As a result, the decrease in the pixel electrode potential described above is suppressed. Accordingly, when a display is performed by a signal in which the video signal and the correction signal are superimposed, even if the scanning signal is delayed, the scanning signal is connected to the same scanning line as the scanning signal advances along the scanning line. It is possible to suppress the deviation in the potential when the switching elements of the plurality of pixel electrodes are cut off, prevent the occurrence of flicker, and significantly improve the display quality.

In the invention of claim 4, the potential difference of the correction signal for each data line of the invention of claim 3 is the amount of decrease in the pixel electrode potential when the switching element in the data line is cut off. Is chosen equally. This allows
The potential when the switching elements of the plurality of pixel electrodes connected to the same scan line are cut off can be made constant, and the display quality can be further improved.

In the invention of claim 5, a plurality of the correction signal generating means of any one of claims 1 and 3 are provided. A part of the plurality of correction signal generating means is connected to one end of one of the plurality of data lines, and the remaining correction signal generating means is a part of the plurality of data lines. Are connected to the other ends of the data lines. The part of the correction signal generating means and the remaining correction signal generating means output data signals to the respective data lines corresponding to the respective correction signal generating means in mutually opposite directions. In the liquid crystal display device having such a structure,
As described above, the display quality can be improved in each stage even if the scanning signal is delayed in the scanning line.

[0034]

EXAMPLES Examples of the present invention will be described below. However, the present invention is not limited to the following examples.

(Embodiment 1) FIG. 1 is a block diagram of a liquid crystal display device according to Embodiment 1 of the present invention. The configuration of one pixel in the display panel of the liquid crystal display device of the present embodiment is the same as the configuration described with reference to FIG. The repeated description is omitted, and the above description with reference to FIGS. 10 and 10 is referred to when necessary. The liquid crystal panel 14 of this liquid crystal display device includes a pixel electrode substrate 1 and a counter electrode substrate 2
And the liquid crystal layer 3 is disposed between and. A plurality of scan lines 9 parallel to each other and a plurality of data lines 8 parallel to each other extending in a direction perpendicular to the scan lines 9 are formed on the pixel electrode substrate 1. Further, at the intersections of the plurality of scanning lines 9 and the plurality of data lines 8, TF
The T (thin film transistor) 7 is arranged, the scanning line 9 is connected to the gate of the TFT 7, and the data line 8 is the TFT.
7 is connected to the input terminal. Pixel electrodes 10 are connected to each scanning line 9 and each data line 8 in a matrix form via a TFT 7. In addition, the counter electrode 1 is formed on the entire surface of the counter electrode substrate 2 facing the pixel electrode substrate 1.
1 is formed. The pixel electrode 10 and the pixel electrode 10
And the liquid crystal layer 3 sandwiched between the pixel electrode 10 and the counter electrode 11 is included in the pixel 15.

The pixel electrode 10 in the liquid crystal panel 14
Each upper scan line 9 is connected to the scan driver circuit 5. The scan driver circuit 5 includes a shift register, and the shift register sequentially outputs a scan signal to each scan line 9. Further, each data line 8 on the pixel electrode substrate 1 is connected to the segment driver circuit 4. The segment driver circuit 4 is a circuit that samples the input video data signal and outputs a video data signal for one horizontal scanning line to each data line 8. Then, the counter voltage, which is a reference of the signal potential of the video data signal, is constantly applied to the counter electrode 11 by the counter voltage application circuit 6.

The video data signal of the NTSC system or the like input from the outside is a signal for the post-stage segment driver circuit 4 such as a process of inverting the signal polarity every horizontal scanning and every vertical scanning. It is input to the signal processing circuit 12 that performs processing. The video data signal whose polarity is inverted every horizontal scanning is input to the adding circuit 28. A sync signal obtained from the video data signal by a sync separation circuit (not shown) is a driver output control circuit 13
Is input to

In the driver output control circuit 13, signals for controlling the correction signal generating circuit 27, the segment driver circuit 4, the scan driver circuit 5 and the counter voltage applying circuit 6 are generated,
Input to each circuit. As shown in FIG. 2B, the correction signal generation circuit 27 generates a correction signal whose signal level linearly decreases by a predetermined potential difference over one horizontal scanning period, and inputs it to the addition circuit 28. A horizontal synchronizing signal is input to the correction signal generating circuit 27 to synchronize the correction signal with the video data signal shown in FIG. The adder circuit 28 adds the video data signal and the correction signal.
The added signals shown in FIG. 3C are input to the segment driver circuit 4. The added signal input to the segment driver circuit 4 is sampled for the data line in the signal for one horizontal scanning period, and is output to the plurality of data lines 8 every time the scanning signal is output from the scanning driver circuit 5.

As the liquid crystal panel becomes larger and the definition becomes higher, the line lengths of the scanning lines 9 and the data lines 8 are extended, and accordingly, the line resistance and the liquid crystal layer 3 are sandwiched between the data lines 8 and the scanning lines 9 and the counter electrodes. The capacity between 11 and 11 increases. As the scanning signal and the video data signal advance on the scanning line 9 and the data line 8, the time constants of the line resistance and the capacitance increase, and the signals are delayed. Scan signal delay is TF
This affects the amount of pulling in the potential of the pixel electrode 10 after T7 is turned off. This pull-in will be described with reference to FIGS. 3 and 4. 3 and 4 are waveform charts showing the video data signal, the scanning signal, and the pixel electrode potential in each case of the presence or absence of delay of the signal.

When there is no delay in the scanning signal as shown in FIG. 3B, the potential of the pixel electrode 10 becomes H of the video data signal when the TFT 7 is turned on as shown in FIG. 3C.
It rises to the level potential Vs. After that, the TFT7 becomes O
When FF is performed, the pixel electrode potential is the difference Δ in potential due to the parasitic capacitance formed between the pixel electrode 10 and the scanning line 9.
It decreases by V1 and becomes the potential Vs-ΔV1. This potential difference ΔV1 is calculated by the following mathematical expression 1.

[0041]

## EQU1 ## ΔV1 = Cgd / (Cgd + Clc) × (Vg
h-Vgl) where Cgd is the parasitic capacitance between the pixel electrode 10 and the scanning line 9, Clc is the capacitance between the pixel electrode 10 and the counter electrode 11,
Vgh is the H level voltage of the scanning signal, and Vgl is the L level voltage of the scanning signal.

Even when the scanning signal is delayed as shown in FIG. 4B, the potential of the pixel electrode 10 is 0 when the TFT 7 is O.
When N, the potential rises to the H level potential Vs of the video data signal. However, when the TFT 7 is turned off, a signal delay causes a slow change in the signal level at the time of rising and falling of the scanning signal, and the TFT 7 is turned on at a potential in the range between the voltages Vgh and Vgl. And OFF
Switch between and. TF at this intermediate potential Vgh '
When T7 switches between ON and OFF, the potential difference ΔV2, which is the amount of pull-in, is expressed by the following mathematical expression 2.

[0043]

[Formula 2] ΔV2 = Cgd / (Cgd + Clc) × (Vg
h′−Vgl) Regarding the potential difference ΔV1 and ΔV2,

[0044]

[Formula 3] ΔV1> ΔV2. Due to the difference in level between the potential difference ΔV1 and the potential difference ΔV2, flicker has conventionally been generated.

As the signal delay increases, the potential difference ΔV decreases. In the liquid crystal display device of FIG. 1, scanning signals are input to the liquid crystal panel 14 from the left side of FIG. Immediately after being input, there is almost no signal delay and the amount of pull-in is ΔV1. The scanning signal advances along the scanning line 9 from the left side to the right side in FIG. 1, and the signal delay becomes maximum at the right end of the liquid crystal panel. At this time, the pull-in amount becomes the maximum potential difference ΔV2. Figure 2
The potential difference ΔV over one horizontal scanning period in the correction signal having the waveform shown in (b) is defined as the potential difference ΔV1-ΔV2. 2 is input to the segmate driver circuit 4.
Regarding the added video data signal shown in (c),
The video data signal level applied to the pixel electrode 10 where there is no signal delay is Vs, and the video data signal level applied where the signal delay is greatest is Vs− (ΔV1−
ΔV2). If this video data signal is applied to each pixel electrode 10 connected to one scanning line 9, the above-mentioned amount of pulling in of the potential of the pixel electrode 10 where there is no scanning signal delay is the potential difference ΔV1, which is the maximum for the scanning signal. The pull-in amount of the pixel electrode 10 where there is a delay is also

[0046]

## EQU00004 ## Since Vs-.DELTA.V-.DELTA.V2 = Vs-.DELTA.V1, the potential becomes .DELTA.V1.

As a result, in the liquid crystal panel, there is no difference in the pull-in amount between the left end portion and the right end portion in FIG. 1, and flicker is prevented from occurring. As a result, the liquid crystal display device of the present embodiment can remarkably improve the display quality. Furthermore, in the present embodiment, the above-described structure used for preventing the occurrence of flicker is realized regardless of the type or structure of the TFT 7 used in the liquid crystal panel. Therefore, the present embodiment has the effect of being versatile because it is possible to prevent the occurrence of flicker regardless of the type and structure of the TFT 7.

(Second Embodiment) A second embodiment of the present invention will be described below.

In the liquid crystal display device of the present embodiment, the voltage applied to the pixel electrode where the potential of the pixel electrode becomes lower than the potential of the video data signal due to the signal delay is amplified by the correction circuit, and the potential of the pixel electrode is affected by the signal delay. The potential is the same as that of the pixel electrode not receiving the light. This prevents the occurrence of display defects such as display unevenness as described in the second prior art section.

FIG. 5 is a block diagram showing the electrical construction of the liquid crystal display device of this embodiment. Of the configuration of the liquid crystal display device of the present embodiment, the configuration of each part of the liquid crystal panel 14, the segment driver circuit 4, and the scan driver circuit 5 and the connection relationship thereof are the same as those of the first embodiment described with reference to FIG. The liquid crystal panel 14, the segment driver circuit 4, and the scan driver circuit 5 of the liquid crystal display device have the same configuration and mutual connection. The same reference numerals are given to the portions corresponding to the constituent elements of the liquid crystal display device of the first embodiment.

In the liquid crystal display device of the present embodiment, the video signal from the video data signal generator 29 such as an external computer is synchronized with the sync separation circuit 30 and the data correction circuit 32.
Are input to the amplifiers 33 and 34, respectively. The data correction circuit 32 includes an amplifier 3 to which the video signal is commonly input.
3, 34, a switch 35 that is turned on / off to turn on or off the signal from the amplifier 34, and an adder circuit 36 to which the output from the amplifier 33 and the output from the switch 35 are input, respectively. It is composed of. The output of the adder circuit 36 is input to the segment driver circuit 4.

The segment driver circuit 4 and the scan driver circuit 5 as described in the first embodiment are connected to the liquid crystal panel 14 described above. Further, the liquid crystal display device includes a segment driver control circuit 31 for controlling the operation of the segment driver circuit 4, and further, a scan driver control circuit 3 for controlling the operation of the scan driver circuit 5.
It is equipped with 4.

Sync signals such as a horizontal sync signal and a vertical sync signal separated from the video signal in the sync separation circuit 30 are input to the segment driver circuit 31 and the scan driver control circuit 39, respectively. A signal from the scan driver control circuit 39 is input to the scan driver circuit 5, and a data correction amount control circuit 37 for controlling the gain of the amplifier 34 and a data correction timing for controlling the switching operation of the switch 35. Each is input to the control circuit 38.

FIG. 6 is a plan view showing the connection relationship between the liquid crystal panel 14, the segment driver circuit 4 and the scan driver circuit 5 used in this embodiment. In the liquid crystal display device of the present embodiment, the scan driver circuit 5 is connected to one end of the liquid crystal panel 14 in the horizontal scanning direction, and the liquid crystal panel 14 is connected.
Of the segment driver circuit 4 at one end in the vertical scanning direction of
Is connected. Therefore, the scanning signal travels on the scanning line 9 from the left end to the right end in FIG. 6, and the video data signal travels on the data line 8 from the upper side to the lower side in FIG.

The operation of the liquid crystal display device of this embodiment will be described below. The video data signal from the video data signal generator 29 is input to the amplifier 33 and the amplifier 34 of the data correction circuit 32 and the sync separation circuit 30.
The video data signal input to the amplifier 33 is amplified by a predetermined amplification factor and input to the adding circuit 36. The video data signal input to the amplifier 34 is amplified by the amplification factor based on the control signal of the data correction amount control circuit 37, and is switched to the switch 35.
Is input to the adder circuit 36 at the ON / OFF timing of the switch 35 according to the control signal from the data correction timing control circuit 38.

The adder circuit 36 to which the respective signals from the amplifier 33 and the switch 35, which are input to the adder circuit 36, are input.
, The video data signals passed through the amplifier 33 and the amplifier 34 are added and output, or the amplifier 33
Only the video data signal that has passed through is output. The signal output from the adder circuit 36 is input to the segment driver circuit 4, and the segment driver circuit 4 outputs video data to the plurality of data lines 8 in response to a control signal from the segment driver control circuit 31.

A signal voltage of the video data signal sent via the data line 8 is applied to the pixel electrode 10 described with reference to FIG. 10 via the TFT 7, and the pixel electrode potential is the signal of the video data signal. It becomes the same potential as the potential. However, when the liquid crystal panel 14 becomes larger, the line lengths of the data line 8 and the scanning line 9 become longer. Along with that, lines 8 and 9
, The line resistance and capacitance of the device increase, and the time constant increases. Due to the increase in the time constant, the signal delay of the video data signal and the scanning signal traveling on the data line 8 and the scanning line 9 becomes large. Accordingly, in the conventional technique, as described above, the TFT connected to the pixel electrode 10 is
In order to control ON / OFF of 7, the timing of the scanning signal applied to the TFT 7 and the timing of the applied video data signal are deviated, and the potential of the pixel electrode 10 does not reach the signal potential of the video data signal. become. The mechanism by which this phenomenon occurs will be described with reference to FIGS.

In FIG. 12, the scanning signal, the data signal, and the potential of the pixel electrode 10 when the signal delay does not occur are
Scan signal potential V (Y1) and data signal potential V, respectively
(X1), and the pixel electrode potential V (Y1, X1). Here, the data signal potential V (X1) and the pixel electrode potential V
As an example, (Y1, X1) sets the ground potential and the predetermined potential Vs to the L level and the H level, respectively. Further, the scanning signal, the data signal, and the potential of the pixel electrode 10 when the signal delay occurs are set to the scanning signal potential V (Y
m), data signal potential V (Xn), pixel electrode potential V (Y
m, Xn). The ON / OFF timing of the TFT 7 is determined by the rising timing and the falling timing of the scanning signal.

When there is no signal delay, the scanning signal causes TF.
As T7 is turned on, the potential of the pixel electrode 10 rises to the potential of the data signal. When the TFT 7 is turned off, the potential of the pixel electrode 1 is maintained as it is. The signal potential V (Y
m) and V (Xn), when the scanning signal potential V (Ym) is input to the TFT 7, the pixel electrode potential V (Ym, Xn) starts to rise. When the TFT 7 is turned off, the data signal potential V (X
n) does not rise to the potential Vs, the above-mentioned voltage pull-in occurs, and the potential becomes Vs-ΔV. As a result, the potential of the pixel electrode 10 also becomes the potential (Vs-ΔV).

As described above, in the display panel, the potential difference −ΔV is generated in the pixel electrodes 10 located at the positions distant from each other in the horizontal scanning direction, so that the display has a difference in brightness and darkness.
There is a problem that it causes a display defect that causes display unevenness. The potential difference −ΔV becomes larger as the video data signal advances along the data line 8.

In the present embodiment, in order to prevent the occurrence of such a display defect, instead of the data signal potential V (Xn) supplied from the data line 8, the data signal potential V (X
The data signal potential is amplified by the data correction circuit 32 so that n) + ΔV is supplied. This allows the TFT
When 7 is turned off, the pixel electrode potential V (Ym, Xn) coincides with the data signal potential Vs, and the pixel electrode potential is maintained at this potential Vs. Therefore, the pixel electrodes 1 in the pixels affected by the above-mentioned signal delay and those not affected by the signal delay
The potential difference of 0 is eliminated, and the above-mentioned display unevenness is improved.

Regarding the data correction timing and the data correction amount used to realize the operation of the present embodiment,
This will be described below. In the liquid crystal panel 14 of FIG. 6,
When the video data signal is input to each data line 8 from the upper side of FIG. 6, the signal delay becomes larger from the upper side to the lower side, and in the related art, there is a brightness difference (display unevenness) in the display above and below the liquid crystal panel 14. appear.

The entire display area of the liquid crystal panel 14 is divided into a plurality of areas along the vertical scanning direction as shown in FIG. In the following description, it is assumed that the liquid crystal panel 14 has 200 scanning lines 9. Of course, the present invention is not limited to the number of scan lines 9.
The liquid crystal panel 14 includes an area A (first scanning line to 40th scanning line), an area B (41st scanning line to 80th scanning line), an area C (81st scanning line to 120th scanning line), and an area D ( The 121st scan line to the 160th scan line) and the region E (161st scan line to the 200th scan line).

The potential of the pixel electrode 10 in each of the areas A to E when focusing only on the signal delay is as follows. The potential of the pixel electrode 10 in the area A is the potential Vs, the potential of the pixel electrode 10 in the area B is the potential Vs−ΔV1, the potential of the pixel electrode 10 in the area C is the potential Vs−ΔV2, and the potential of the pixel electrode 10 in the area D. Is Vs-ΔV3, and the potential of the pixel electrode 10 in the region E is Vs-ΔV4. The display for each of the areas A to E gradually becomes brighter from the area A to the area E based on the difference in the potential. Here, regarding each of the potential differences ΔV1, ΔV2, ΔV3, and ΔV4,

[0065]

The relationship of ΔV1 <V2 <ΔV3 <ΔV4 is established.

The data correction in the data correction circuit 32 is performed when the video data signal is applied to each pixel electrode 10 in the areas B, C, D and E. In the data correction amount control circuit 37, the potential difference Δ with respect to each video data signal output to each of the areas B to E at each timing of outputting the video data signal to each of the areas B, C, D, and E.
The amplification amount of the amplifier 34 of the data correction circuit 32 is controlled so as to amplify V1, ΔV2, ΔV3, and ΔV4, respectively.

On the other hand, the control signal for turning on / off the switch 35, which is created by the data correction timing circuit 32, turns on the plurality of TFTs 7 connected to the scanning line 9.
The switch 35 is made to be turned ON / OFF so that the video data signal corrected by the data correction circuit 32 can be output from the segment driver circuit 4 during the period in which the scan signal N is output from the scan driver circuit 5. It The correction timing can be set or changed from the outside. The data correction circuit 32 controls the switch 35 by the control signal sent from the data correction timing control circuit 38.

When the data correction is performed at the above-mentioned timing, the video data signal amplified by the amplifier 34 is input to the adder 36 by turning on the switch 35. As a result, the video data signal amplified by the amplifier 33,
The video data signal amplified by the amplifier 34 is added to the adder 36.
And add to amplify the signal. By performing this signal amplification, the voltage applied to the pixel electrode 10 is increased by the amount of the potential difference that is reduced due to the signal delay. As a result, the potential of each pixel electrode 10 in each of the regions B to E is set to the same potential as the potential of the pixel that is not affected by the signal delay.
As a result, the display brightness becomes uniform over the entire surface of the display panel 14, and the display unevenness as described in the related art is eliminated.

At the timing when the video data signal is output to the area A where the data correction is not performed, the switch 35
Is turned off, and the video data signal input to the area A is input to the segment driver circuit 4 without correction. Therefore, the pixel electrode potential in the region A is also the same as the corrected pixel electrode potential Vs in the pixel electrode 10 in the regions B to E.

In the above embodiment, the correction is performed in the areas B, C, D,
Although there are four levels corresponding to E, if the display panel 14 is divided into smaller sections and data correction is performed in the same manner as described above, the display defect can be resolved with higher accuracy.

(Embodiment 3) FIG. 7 is a plan view showing the connection relationship of a liquid crystal panel 14, a segment driver circuit 4 and a scan driver circuit 5 of Embodiment 3 of the present invention, and FIG. 8 is a liquid crystal display of this embodiment. It is a block diagram which shows the electric constitution of an apparatus. Of the configuration of the liquid crystal display device of the present embodiment, the configuration of each part of the liquid crystal panel 14, the segment driver circuit 4, and the scan driver circuit 5 and the connection relationship thereof are the same as those of the first embodiment described with reference to FIG. The liquid crystal panel 14, the segment driver circuit 4, and the scan driver circuit 5 of the liquid crystal display device have the same configuration and mutual connection. The same reference numerals are given to the portions corresponding to the constituent elements of the liquid crystal display device of the first embodiment. The circuit configuration shown in FIG. 8 is similar to the circuit configuration shown in FIG. 5 of the second embodiment,
Corresponding parts are designated by the same reference numerals.

The third embodiment will be described below. In this embodiment, the liquid crystal panel 14a is divided into a region F (first scanning line to 40th scanning line), a region G (41st scanning line to 80th scanning line), and a region H (81st scanning line to 120th scanning line). ), A region I (121st scanning line to 160th scanning line), and a region J (161st scanning line to 200th scanning line). In the liquid crystal display device of the present embodiment, the scan driver circuit 5 is connected to one end of the liquid crystal panel 14 in the horizontal scanning direction, and the liquid crystal panel 1
Segment driver circuits 4 and 4a are connected to both ends of the vertical scanning direction 4, respectively. Here, as an example, the segment driver circuit 4 is connected to the odd-numbered data lines 8 from the left in FIG. 7, and the segment driver circuit 4a is connected to the even-numbered data lines 8 from the left in FIG. Therefore, the scanning signal proceeds from the left end to the right end of the scanning line 9 in FIG. 7, and the video data signal in the odd-numbered data line 8 moves down the even-numbered data line 8 from above in FIG. Proceed towards. The video data signal on the even-numbered data lines 8 travels on the even-numbered data lines 8 from the bottom to the top in FIG.

In the liquid crystal display device of this embodiment shown in FIG. 8, in addition to the circuit configuration shown in FIG. 5, a new segment driver circuit 4a is provided as shown in FIG.
In response to this, a new segment driver control circuit 3
1a is provided. In addition, the segment driver circuit 4
In order to control a similarly to the segment driver circuit 4 of the second embodiment, the data correction circuit 32 of the second embodiment is used.
Similarly, the data correction circuit 32a including the amplifiers 33a and 34a, the switch 35a, and the adder circuit 36a, the segment driver control circuit 31a, and the scan driver control circuit 34a, which are connected to each other, are provided in the liquid crystal display device of the present embodiment. ing. These circuits 31a, 32a, 34a
The mutual connection relationship is similar to that of the corresponding segment driver control circuit 31, data correction circuit 32, and scan driver control circuit 34 in the second embodiment. Further, the segment driver control circuits 31, 3
A control signal from the same scan driver control circuit 39 is input to the 1a and the scan driver control circuits 34, 34a.

The operation of this embodiment will be described below.

As shown in FIG. 7, the video data signals are transmitted from the vertical direction of the liquid crystal panel 14 to the segment driver circuits 4, 4a.
The video data signal input from the segment driver circuit 4 above the liquid crystal panel 14 when being input to the liquid crystal panel 14 via the liquid crystal panel 1 as described above.
From 4 to 4 the signal delay increases. on the other hand,
Regarding the video data signal input from the lower part of the liquid crystal panel 14, conversely, the signal delay increases as the liquid crystal panel 14 goes from the bottom to the top. At this time, in the liquid crystal panel of the conventional technique, the difference in brightness and darkness as described in the conventional technique occurs for each data line 8 to cause a display defect (display stripe).

The correction process of this embodiment is performed on the display panel 14 of FIG. 7 in four steps. First. LCD panel 14 5
It is divided into two areas. As an example, in the liquid crystal panel 14, the area F (first scanning line to 40th scanning line), the area G
(41st scan line to 80th scan line), region H (81st scan line to 120th scan line), region I (first scan line)
21st scanning line to 160th scanning line), and area J
(Sixteenth scan line to 200th scan line).

Regarding the potential of the pixel electrode 10 connected to the segment driver circuit 4 above the liquid crystal panel 14 via the data line 8, the pixel electrode for each of the regions F to J in the case where only the delay of the signal is focused. The potential is as follows. The pixel electrode potential in the region F is the potential Vs, the pixel electrode potential in the region G is the potential (Vs-ΔV5), the pixel electrode potential in the region H is the potential (Vs-ΔV6), and the region I. The pixel electrode potential in the region J is the potential (Vs-ΔV7), and the pixel electrode potential in the region J is the potential (Vs-ΔV8). The segment driver circuit 4 below the liquid crystal panel 14
Regarding the potentials of the plurality of pixel electrodes 10 connected to a through the data line 8, the pixel electrode potentials of the respective regions F to J when focusing only on the delay of the signal are as follows. The pixel electrode potential (Vs-ΔV8) in the region F,
Region G pixel electrode potential (Vs-ΔV7), Region H pixel electrode potential (Vs-ΔV6), Region I pixel electrode potential (V
s-ΔV5) and the pixel electrode potential Vs of the region J. Here, regarding the respective potential differences ΔV5, ΔV6, ΔV7, and ΔV8,

[0078]

The relationship of ΔV5 <ΔV6 <ΔV7 <ΔV8 is established.

Here, the video data signal input to the liquid crystal panel 14 from above using the segment driver circuit 4 is a scan signal for scanning the regions G, H, I and J, respectively. The period output from
The switch 35 of the data correction circuit 32 is turned on to perform the data correction as described in the second embodiment. The video data signal has potential differences ΔV5, ΔV6, and ΔV over the respective periods in which the regions G, H, I, and J are scanned.
7. Only .DELTA.V8 is corrected. Segment driver circuit 4
The video data signal input to the liquid crystal panel 14 from below by using a is a data correction circuit during the period when the scan driver circuit 5 outputs the scan signals for scanning the regions F, G, H, and I, respectively. Turn on the switch 35a of 32a
Then, the data correction as described in the second embodiment is performed. The correction amounts are the potential differences ΔV8 and ΔV, respectively, in the respective periods in which the regions F, G, H, and I are scanned.
Correct by 7, ΔV6, and ΔV5.

Such segment driver circuits 4, 4
By the correction processing of the video data signal for each a, the liquid crystal panel 1
The potentials of all pixel electrodes 10 of No. 4 are the same as the potential Vs of the pixel electrodes 10 having no signal delay, and the display stripes are improved. As a result, the display quality is significantly improved.

In the present embodiment, if the four stages of correction are performed based on the subdivided sections of the liquid crystal panel 14, the display stripes can be eliminated with higher accuracy.

[0082]

As described above, according to the first aspect of the invention, the video data signal applied to the pixel electrode affected by the signal delay is corrected at the video data signal stage, and the pixel is delayed by the scanning signal. Eliminates the difference in the decrease in electrode potential. Thereby, the display defect can be improved.

According to the second aspect of the invention, the potential when the switching element of the pixel electrode is cut off can be made constant by using the correction signal. Thereby, the display quality is further improved.

According to the third aspect of the present invention, when the display is performed by the signal in which the video signal and the correction signal are superimposed, even if the delay of the scanning signal occurs, the scanning signal advances as the scanning line advances. It is possible to suppress the deviation in the potential when the switching elements of the plurality of pixel electrodes connected to the same scanning line are cut off, and prevent flicker from occurring.
The display quality is significantly improved.

According to the fourth aspect of the invention, the potential when the switching elements of the plurality of pixel electrodes connected to the same scanning line are cut off can be made constant, and the display quality can be further improved.

According to the invention of claim 5, some of the correction signal generating means and the rest of the correction signal generating means output data signals to the respective data lines corresponding to the respective correction signal generating means in mutually opposite directions. I am trying. In the liquid crystal display device having such a configuration, the display quality can be improved in each stage even if the scanning signal is delayed in the scanning line.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the operation of the present embodiment.

FIG. 3 is a waveform diagram showing a potential of a pixel electrode when there is no signal delay.

FIG. 4 is a waveform diagram showing a potential of a pixel electrode when there is a signal delay.

FIG. 5 is a block diagram showing an electrical configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a plan view of a liquid crystal panel 14 of this embodiment.

FIG. 7 is a plan view showing the connection relationship between the constituent elements of the third embodiment of the present invention.

FIG. 8 is a block diagram showing an electrical configuration of the liquid crystal display device of the present embodiment.

FIG. 9 is a block diagram showing the overall electrical configuration of a conventional liquid crystal display device.

FIG. 10 is an equivalent circuit diagram of one pixel 15 in the liquid crystal panel 14.

FIG. 11 is a partial cross-sectional view of a liquid crystal display device according to a second prior art active matrix system.

FIG. 12 is a system diagram of a liquid crystal display device.

FIG. 13 is a block diagram showing an electrical configuration of a liquid crystal display device.

FIG. 14 is a waveform diagram illustrating a conventional operation.

[Explanation of symbols]

 1 Pixel Electrode Substrate 2 Counter Electrode Substrate 3 Liquid Crystal 4, 4a Segment Driver Circuit 5 Scan Driver Circuit 8 Data Line 9 Scan Line 12 Signal Processing Circuit 13 Driver Output Control Circuit 14 Liquid Crystal Panel 27, 32, 32a Correction Data Generation Circuit 28 Addition Circuit 31, 31a Segment driver control circuit 33, 34, 33a, 34a Amplifier 35, 35a Switch 36, 36a Adder 37, 37a Data correction amount control circuit 38, 38a Data correction timing control circuit 39 Scan driver control circuit

Claims (5)

[Claims] 1. A plurality of pixel electrodes are respectively connected to a plurality of data lines via a switching element whose switching state is controlled by a scanning signal via a scanning line, and a liquid crystal layer is sandwiched between the plurality of pixel electrodes. A liquid crystal display device provided with opposing electrodes facing each other, wherein a scanning driving unit that sequentially outputs a scanning signal to each scanning line to make each switching element conductive, and a scanning drive unit to each pixel electrode sequentially through the plurality of data lines. A data driving unit that outputs a video data signal, and a potential difference that is predetermined over a vertical scanning period in order to correct a variation in a decrease amount of the pixel electrode potential when the switching element is cut off, which is generated based on a signal delay in the data line. Correction signal generating means for generating a correction signal whose electric potential decreases only by the image signal applied to the pixel electrode and the correction signal Superimposing the items, a liquid crystal display device of the superimposed signal and a superimposing means for outputting to the data driving unit. 2. The predetermined potential difference of the correction signal generated by the correction signal generating means is a first potential decrease amount of the pixel electrode potential at a portion of the data line where the signal delay is not generated. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is defined as a difference between a second potential decrease amount of the pixel electrode potential at a portion where the signal delay occurs. 3. A plurality of pixel electrodes are respectively connected to a plurality of data lines via a switching element whose switching state is controlled by a scanning signal via a scanning line, and a liquid crystal layer is sandwiched between the plurality of pixel electrodes. A liquid crystal display device provided with opposing electrodes facing each other, wherein a scanning driving unit that sequentially outputs a scanning signal to each scanning line to make each switching element conductive, and a scanning drive unit to each pixel electrode sequentially through the plurality of data lines. A data driving unit that outputs a video data signal, and a potential difference that is predetermined over a vertical scanning period in order to correct a variation in a decrease amount of the pixel electrode potential when the switching element is cut off, which is generated based on a signal delay in the data line. Correction signal generating means for generating a correction signal whose potential increases only by the above, a video signal applied to the pixel electrode, and the correction signal. Superimposing the items, a liquid crystal display device of the superimposed signal and a superimposing means for outputting to the data driving unit. 4. The liquid crystal according to claim 3, wherein the potential difference of the correction signal for each data line is selected to be equal to the amount of decrease in the pixel electrode potential when the switching element is shut off in the data line. Display device. 5. A plurality of the correction signal generating means are provided,
Some of the correction signal generating means are connected to one end of one of the plurality of data lines, and the remaining correction signal generating means are connected to the other end of the remaining data lines of the plurality of data lines. 4. The liquid crystal display device according to claim 1, wherein each of the correction signal generating means and the rest of the correction signal generating means are connected to each other and output data signals to the respective data lines in mutually opposite directions.