JPH08298665A - Circuit and method for detecting motion vector - Google Patents

Abstract

PURPOSE: To optimize operation quantity and accuracy in the detection of a motion vector, the degree of compression of a moving image and the picture quality of a compressed moving image. CONSTITUTION: This system is provided with a circuit 36 for deleting the lower bits of each digital data indicating each picture element value in a current macro block, a circuit 38 for deleting the lower bits of each digital data indicating each picture element value in a reference picture, a detection circuit 40 for mutually comparing outputs from the circuits 36, 38, searching an area most similar to the current macro block from the reference picture and setting up the searched area as a reference macro block, and circuits 46, 48 for selecting an output from an intra-encoding circuit 52 and an output from an inter-encoding circuit 50 in accordance with the compression efficiency of respective circuits 52, 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture compression technique. In particular, predictive coding with motion compensation, detection of a motion vector indispensable in the predictive coding, reduction of the amount of calculation required for detection of the motion vector, optimization of compression by selecting intra-frame compression and inter-frame compression Regarding conversion.

[0002]

[Prior art]

(1) Moving picture compression technology In a method of compressing and coding data obtained by digitizing a moving picture signal, methods such as prediction with motion compensation, orthogonal transformation, quantization, and variable length coding are used. For example, MPE
In G, predictive coding with motion compensation, Discrete Cosine Transformation (DCT), adaptive quantization, and Huffman coding are adopted. MPEG is the name "Moving Picture Experts Gro" of the image compression standardization committee established under ISO (International Organization for Standardization).
Abbreviation for "up". The MPEG-1 standard is "ISO /
IEC 11172 ”and MPEG-2.
The draft standard is specified in "ISO / IEC 13818".

A conventional technique in this field is USP52.
31484 (JP-A-5-252507), USP52
93229 (JP-A-5-276502), USP53
25125 (JP-A-6-225284).

In the prediction with motion compensation, first, an area (= reference macroblock) most similar to an area (= current macroblock) to be data compressed in the current screen (= current frame) precedes in time. Is found in the reference screen and / or in the reference screen that follows in time, and the difference value between the found reference macroblock and the current macroblock is obtained. Here, a vector indicating the position of the reference macroblock from the position of the current macroblock is called a "motion vector", and finding the position of the reference macroblock is called "motion vector detection". In addition,
A macroblock is an area that is a unit of predictive coding, and at the time of data compression consisting of 16 × 16 pixels, DCT, quantization, and variable length coding are performed on the difference data between the current macroblock and the reference macroblock. Done. Also,
When decompressing the compressed difference data, the image of the reference macroblock (the macroblock specified by the motion vector in the reference screen) is compared with the difference data obtained by variable-length decoding, inverse quantization, and inverse DCT. The data is added to reproduce the image data of the current macroblock. Note that the image data of at least one screen that temporally precedes and at least one screen that temporally succeeds is MPE.
In the G method, it is stored in a predetermined memory.

In the DCT, each block divided into 8 × 8 pixels is decomposed into frequency components of a low frequency term to a high frequency term, and an 8 × 8 coefficient matrix [Cij is formed of coefficients Cij of each frequency term. ] Is converted to. Hereinafter, the subscripts i and j are i
Represents row j column. A block is a transform coding (DC
This is a region that is a unit of T, quantization). That is, the predictive coding is performed in units of macroblocks (16 × 16 pixels), but the transform coding is performed in units of blocks (8 × 8 pixels).

In the quantization, each coefficient Cij of the 8 × 8 coefficient matrix is divided by a certain divisor Qij (quantization step width q × constant Kij unique to each coefficient Cij) to round the remainder. Here, the constant Kij is given by the quantization matrix table. In the intra macroblock, a quantization matrix table in which a large value is prepared for a coefficient of a high frequency term and a small value is prepared for a coefficient of a low frequency term is generally used. In the inter macroblock, the values Kij are all the same. As the quantization matrix data Kij, it is allowed in the standard to load data for intra macroblock and for inter macroblock for each concept corresponding to a program called a sequence. In addition, it is said that at least 1 GOP (Group Of Picture) is included, and the minimum unit is 1
The quantization matrix can be changed for each GOP.
If the value of Kij and / or q is increased, the quantization circuit 118
The coefficient data C'ij output from the number "0" increases and the degree of compression increases. In the adaptive quantization, the bit rate of the output bit stream is monitored, and the quantization step width q is determined so that the value becomes a target value. That is, if the bit rate is smaller than the target value, the quantization step width q is controlled to be small, and if it is larger than the target value, the quantization step width q is controlled to be large. As a result, the bit rate is controlled near the target value.

In the Huffman coding, the codes are assigned according to the appearance frequencies of the quantized coefficient values C'ij (Cij ÷ Qij) so that the higher the appearance frequency is, the shorter the code becomes. That is, variable length coding is performed.

(2) Detection of Motion Vector The motion vector is, for example, as shown in FIG. 5, a region A in the reference screen that is temporally ahead and / or the reference screen that is temporally behind.
With 0 being the center (16 × 16 pixel area having the same coordinate position as the current macroblock A to be compressed in the current screen), the pixels in the area corresponding to the eight 16 × 16 pixel areas around it are searched. That is, 48 × 48 centered on the area A0
The inside of the pixel area is the target range of the motion vector search.
It is also possible to search for a motion vector beyond this area, but in that case, the circuit configuration becomes complicated and large, and the required memory capacity also becomes large. The case of searching for a motion vector beyond this area is, for example, when the inter-frame distance becomes large. In MPEG, when the inter-frame distance is 3 frames apart, the range of ± 48 pixels becomes the search range. .

A method for finding a motion vector from the search area, in other words, the current macroblock A in the search area.
As a method of finding an area (= reference macroblock) most similar to, there is the following method. * Full search method As shown in FIG. 5A, each pixel is moved one pixel at a time from the upper left corner area A1 within a predetermined search range centered on the area A0 in the reference screen corresponding to the current macroblock A. Area A2, A3,
... and the current macroblock A are compared. Although the number of regions to be compared is huge and the amount of calculation is huge, the accuracy of motion vector detection is high. * Logarithmic search method As shown in (b) of FIG. 5, within a predetermined search range centered on the area A0 in the reference screen corresponding to the current macroblock A, for example, upper left → upper → upper right → left → Center → right → lower left → lower → lower right, then the most similar region
It is a method of narrowing the search range, focusing on A3. In addition,
The comparison order may be another order. It is called a logarithmic search because the narrowing of the search range is logarithmic. * Telescopic search method As shown in FIG. 5 (c), the area A1 designated by the previously detected motion vector (the motion vector detected for the corresponding macroblock of the previous screen, the adjacent motion vector, etc.) is sequentially displayed from the area A1. This is a method of searching for nearby areas. Although the amount of calculation can be reduced because the area to be compared is limited, the accuracy of motion vector detection is slightly inferior.

Further, the areas A0, A1, A2 ...
Among the above, as a method for detecting the area most similar to the current macroblock, there is the following method. * Sum of absolute value (or squared value) of difference Calculate the difference value of the pixel values (values corresponding to the brightness) corresponding to the areas A0, A1, A2 ... And the current macroblock to be compared, Absolute value (or squared value) of the difference value of each pixel
Is a method of detecting the sum of the two as a reference macroblock. * Number of matching pixels The number of pixels in which the values of the corresponding pixels in the areas A0, A1, A2, ...
This is a method of detecting the area having the maximum number as a reference macroblock.

Regarding the detection of the motion vector, for example, Japanese Patent Laid-Open Nos. 4-145777 and 4-79.
No. 484, No. 3-40687, No. 4
It is disclosed in JP-A-207790, JP-A-4-234276, and JP-A-4-40193.

(3) Reduction of calculation amount of motion vector detection In the calculation of motion vector detection, as described above, a large number of 1
Since each pixel value of the 6 × 16 pixel area is compared with the pixel value of the current macro block, the amount of calculation becomes enormous. For this reason,
It is desired to reduce the amount of calculation without degrading the accuracy of the motion vector, and a binarization method has been proposed. The binarization method is the value of each pixel of the current macroblock to be compressed (each 8 bits) and each 16 × within the search range.
This is a method in which the values of pixels in the 16-pixel area (8 bits each) are binarized and compared. Regarding the binarization method, for example, JP-A-62-71580 and JP-A-4-87.
No. 4 and Japanese Patent Laid-Open No. 4-10176. The outline of the binarization method disclosed in Japanese Patent Laid-Open No. 62-71580 will be described below with reference to FIG.

To simplify the explanation, one screen has a size of 12 × 1.
It is assumed that there are two pixels and one macroblock is 4 × 4 pixels. In addition, as a matter of course, the following discussion can be similarly applied to the actual one screen and the actual macroblock (16 × 16 pixels). The frame memory 10 stores the digital video signal of the current screen of 12 × 12 pixels. The frame memory 12 stores a digital image signal of a 12 × 12 pixel front screen. The digital video data of the current screen of the frame memory 10 is blocked by the blocking circuit 14 into 4 × 4 pixel macroblocks.

Each macroblock output from the blocking circuit 14 is binarized by the binarization processing circuit 16. As the binarization threshold value at this time, an average value of each pixel value (each 8 bits) of the macro block is adopted. Thus, FIG.
As shown in (b) of FIG. 4, each 8-bit digital video data of 4 × 4 pixels is converted into 1-bit black-and-white digital video data of 4 × 4 pixels. In addition, the binarization processing circuit 16
The binarization processing circuit 18 sets the above threshold values for each macroblock.
To the standard value.

The binarization processing circuit 18 binarizes each pixel value of the previous screen using the reference value provided from the binarization processing circuit 16 as a threshold value. Thus, as shown in FIG. 1 (c),
8x digital image data of 12x12 pixels
It is converted into black and white digital image data of 1 × 12 × 12 pixels. The binarization process of the previous screen is performed for each macroblock.

The binarized macroblock (4
X4 pixels) and each area of the previous screen (12x12 pixels) (each 4x4 pixel area: areas A0, A1, A2 described above)
..) are compared by the motion vector detection circuit 20. Here, the number of matching output pixels is counted, and the region (4 × 4 pixel region) with the maximum matching number is detected as a reference macroblock.

[0017]

There is a demand to reduce the amount of calculation for motion vector detection (= reference macroblock detection) in order to simplify the circuit configuration and increase the processing speed. Also, without degrading the accuracy of the motion vector,
There is also a demand to reduce the calculation amount of motion vector detection. There is also a demand for optimizing the overall calculation amount and image quality of moving image compression so as not to deteriorate the image quality of a moving image compressed using the motion vector even when the accuracy of the motion vector is reduced. . There is also a demand to achieve the above optimization in accordance with the characteristics of a moving image, that is, the characteristics such as a scene with little motion, a scene with a uniform background movement, and a scene with random and intense motion. That is, there is also a demand for optimizing the processing in consideration of the accuracy of the motion vector, the degree of deterioration in image quality, the degree of reduction in the overall amount of calculation of moving image compression, and the like. The present invention aims to meet the above-mentioned needs.

[0018]

According to the present invention, the first screen of the first screen (current screen) is defined as in Claims 1, 23, and 44.
A first position in the second screen (reference screen) corresponding to the position of the region (current macroblock) and a second region (reference macroblock) in the second screen having a pixel value similar to that of the first region.
A circuit for detecting a motion vector indicating the difference between the second position and the second position by comparing the pixel value of the first region with the pixel value of each region in the second screen. Threshold selection means for selecting a pixel value having a predetermined rank as a threshold, and each pixel in the first region and each pixel in the second screen are binarized using the threshold and the comparison is performed. And a binarization circuit that outputs each for use in a motion vector detection circuit and method. The threshold value selecting means or step may be configured by means or step for selecting a pixel value in the order of half of the number of pixels in the first area as a threshold value. .

According to the present invention, the first position in the second screen corresponding to the position of the first region of the first screen and the pixel value of the first region are similar to each other. The motion vector indicating the difference from the second position of the second area in the second screen is
A circuit for detecting by comparing a pixel value of the first area with a pixel value of each area in the second screen, wherein each pixel in the first area is defined as an adjacent pixel in the first area. A first area binarization circuit that binarizes based on a comparison result of pixel values and outputs the result for comparison, and a pixel value comparison between each pixel in the second screen and an adjacent pixel in the second screen. And a second screen binarizing circuit which binarizes the image based on the result and outputs the binarized image for the comparison. The first region binarization circuit or function may be implemented by any one of claims 4, 26, and 4.
A first binarization of each pixel in the first screen based on a result of comparison of pixel values with adjacent pixels in the first screen as shown in FIG.
A screen binarization circuit and a block circuit or function for inputting the output of the first screen binarization circuit to cut out the first region from the first screen and output the binarized data of the corresponding pixel. You may comprise.

According to a fifth aspect of the present invention, the first position in the second screen corresponding to the position of the first area of the first screen, the first area and the pixel value are the same. Second approximation
A circuit for detecting a motion vector indicating a difference between a second position of a second area in the screen by comparing a pixel value of the first area with a pixel value of each area in the second screen,
A first screen binarization circuit that binarizes each pixel in the first screen and an output of the first screen binarization circuit are input, and the first region is cut out from the first screen to respond. 2 of pixels
A block circuit for outputting binarized data, a second screen binarization circuit for binarizing each pixel in the second screen, and inputs of the block circuit and the second screen binarization circuit And a comparison circuit for performing the comparison, and a motion vector detection circuit and method.

According to the present invention, the first position in the second screen corresponding to the position of the first area of the first screen and the pixel value of the first area are similar to each other. The motion vector indicating the difference from the second position of the second area in the second screen is
A circuit for detecting by comparing the pixel value of the first area and the pixel value of each area in the second screen, wherein the lower bit of each digital data indicating each pixel value of the first area is deleted. A motion vector detection circuit including a first deletion circuit used for the comparison, and a second deletion circuit used for the comparison by deleting the lower bit of each digital data indicating each pixel value of the second screen. Is the way.

According to a seventh aspect of the present invention, the first position in the second screen corresponding to the position of the first region of the first screen and the pixel value of the first region are similar to each other. The motion vector indicating the difference from the second position of the second area in the second screen is
A circuit for detecting by comparing the pixel value of the first area with the pixel value of each area in the second screen, wherein each pixel value of the first area and each of the areas sequentially cut out from the second screen A second region selection circuit that compares each pixel value of the region and selects the region having the maximum number of matching pixels as the second region, and further indicates each pixel value of the first region. A first deleting circuit for deleting the lower bits of the digital data and outputting it to the second area selecting circuit; and a second deleting circuit for deleting the lower bits of each digital data indicating each pixel value of the second screen 2 is a motion vector detection circuit and method having a second deletion circuit for outputting to.

According to the present invention, the first position in the second screen corresponding to the position of the first area of the first screen and the pixel value of the first area are similar to each other. The motion vector indicating the difference from the second position of the second area in the second screen is
A circuit for detecting by comparing a pixel value of the first area and a pixel value of each area in the second screen, by cutting out pixel data of the first area from the first screen,
According to a criterion determined by the characteristics of the cut-out first region, the data amount of each pixel data is reduced and provided for the comparison.
Reduction means, means for extracting a search area for searching for the motion vector from the second screen based on the first position corresponding to the cut-out first area, and pixel data of the extracted search area And a second reducing means for reducing the data amount according to the above criterion for use in the comparison, and a motion vector detecting circuit and method. Claims 9 and 3
1, 52, the threshold is a binarization threshold determined by the characteristics of the cut out first region, and the first and second reducing means binarize each pixel value based on the threshold. You may comprise.

According to a tenth, thirty-second and thirty-third aspect of the present invention, there is provided a moving picture compression circuit for compressing an input moving picture signal by transform coding including DCT and quantization, and the above lower bit is deleted. A circuit for detecting a motion vector, a designating circuit for designating a reference area in a reference screen in accordance with the output of the detection circuit, and differential data between pixel data in the compression target area in the compression target screen and pixel data in the reference area. And a predictive coding circuit that is operated and provided for the transform coding, and a moving picture compression circuit and method. Claims 11, 33,
54, the first deletion circuit in the detection circuit deletes the lower bits of each digital data indicating each pixel value of the first region and leaves the upper 4 bits, and the second in the detection circuit. The deletion circuit may delete the lower bits of each digital data indicating each pixel value of the second screen and leave the upper 4 bits.

The present invention provides a moving picture compression circuit for compressing an input moving picture signal by transform coding including DCT and quantization as described in claims 34 and 55, wherein the moving picture compression circuit operates by deleting the lower bits. A circuit for detecting a vector, the difference data between the pixel data of the reference area designated in the reference screen according to the output of the detection circuit and the pixel data of the compression target area in the compression target screen are operated to perform the transform coding. A predictive coding circuit provided for use, a compression degree when the transform coding is performed on the output data of the predictive coding circuit, and a compression degree when the transform coding is performed on the input moving image signal. A determination circuit that compares each target area and determines the size of the target area,
And a switching circuit that switches the conversion encoding processing for each of the compression target areas according to the determination result so that the compression degree of the conversion encoding becomes high. The code amount in the case of performing the transform coding on the output data of the predictive coding circuit, and the case of performing the transform coding in the input moving image signal as claimed in claim 12, 35, or 56. The determination may be performed by comparing the code amount. In addition, claims 13 and 3
6 and 57, the determination circuit may be configured to perform the determination by comparing the variance value of the compression target area and the variance value of the reference area. In addition, claim 1
4, 37, 58, the motion vector detection circuit has a minimum sum of absolute values of differences between pixel values output from the first deletion circuit and pixel values output from the second deletion circuit. It may be configured such that the area to be selected is selected as the reference area. Further, according to claims 15, 38, and 59, in the motion vector detection circuit, the maximum number of coincidence between each pixel value output from the first deletion circuit and each pixel value output from the second deletion circuit is maximum. It may be configured such that the area to be selected is selected as the reference area. In addition, claim 6
0, the motion vector detection circuit is referred to the area where the variance value of the difference between each pixel value output from the first deletion circuit and each pixel value output from the second deletion circuit is minimum. The area may be selected. Further, according to claim 16, the transform coding circuit quantizes the coefficient with a DCT circuit (62, 54, 62a) for transforming a block of pixel data into a coefficient matrix of a frequency term by discrete cosine transform. Quantization circuit (64,56,64a), and,
It may be configured as follows.

According to a seventeenth aspect of the present invention, there is provided a moving picture compression system for converting a moving picture into a bit stream, wherein each pixel data of the current macro block in the current screen is averaged for the macro block. A current macroblock binarization circuit (16a) for binarizing the reference macroblock, an extraction circuit (20) for extracting a search area in which a reference macroblock is to be searched based on the spatial position of the current macroblock, and each of the search areas. Search area binarization circuit (16b) for binarizing pixel data with an average value of the search area, and each binarized macro block cut out in a predetermined order from the binarized search area By comparing each of the current macroblocks, a detection circuit (20) for detecting pixels in a pair whose coordinates and data values in the macroblock are the same, and a counter (20) for counting the number of pixels in the pair,
An output circuit for extracting the macroblock having the maximum number of pixels of the pair as the reference macroblock and outputting the spatial position
(20) is a moving picture compression system having.

Further, the present invention is a moving picture compression system for converting a moving picture into a bit stream as claimed in claim 18, wherein each pixel data of the current macro block in the current screen is averaged by the average value of the macro block. The current macroblock binarization circuit (16a) that is binarized by the above, the extraction circuit (20) that extracts the search region where the reference macroblock is to be searched based on the spatial position of the current macroblock, and the binarized A reference selection macroblock binarization circuit (16c) for binarizing each pixel data of each macroblock cut out in a predetermined order from the search area, with an average value of the macroblocks;
A detection circuit for detecting, for each macroblock, a pair of pixels having the same coordinate and data value in the macroblock by comparing the binarized macroblock with the binarized current macroblock. ), A counter (20) for counting the number of pixels of the pair, an output circuit (20) for outputting the spatial position by extracting the macroblock with the maximum number of pixels of the pair as the reference macroblock, and the current A motion vector detection circuit (20) for detecting a motion vector indicating the spatial position of the reference macroblock from the spatial position of the macroblock,
It is a moving image compression system having. Moreover, claim 40
As described above, the adaptive coding circuit (46) is further provided with an entropy coding circuit (66, 58, 66a, 120) for entropy coding the output of the quantization circuit such as variable length coding. You may.

According to the present invention, the motion vector of the split screen is detected, the differential screen is obtained by using this motion vector, and the differential screen is compressed. When obtaining a vector, the motion vector detection circuit that detects the vector of the split screen with the small variance value of the difference screen as the motion vector instead of using the vector with the smallest cumulative total of the absolute values of the differences of the split screen as the motion vector (44a ) And a differential screen of the split screen using this motion vector, and an encoding circuit (46) for converting the differential screen into a spatial frequency and performing compression processing. is there. Further, as in claim 42, the motion vector detecting circuit (44a) divides the first screen and binarizes the divided screen using the average value of the images in the divided screen as a threshold value. Quantization circuit (16
a), a second binarization circuit (16b) for binarizing the screen in the motion vector search range using the average value of the images in the motion vector search range of the second screen as a threshold, and the first, A motion detection circuit (20) which receives the output of the second binarization circuit (16a, 16b), counts the number of coincidences of this binary data, and outputs the vector having the largest number of coincidences as a motion vector.
And may be provided. In addition, claim 43
As described above, the motion vector detecting circuit (44a) divides the first screen and binarizes the divided screen using the average value of the images in the divided screen as a threshold value (16a). )
And a second binarization circuit (16c) for binarizing each divided screen using the average value of the image in each divided screen within the motion vector search range of the second screen as a threshold, The output of the second binarization circuit (16a, 16c) is input, the number of coincidences of this binary data is counted, and the vector of the split screen with the largest number of coincidences is output as a motion vector (2
0) and may be configured.

According to a sixty-first aspect of the present invention, there is provided a moving picture compression circuit for compressing an input moving picture signal by transform coding including DCT and quantization, the mean value of pixel values of a compression target area. The binarized data of each pixel of the compression target area having a threshold value is compared with the binarized data of each pixel of the search area having an average value of pixel values of the motion vector search area in the reference screen as a threshold value. And a predictive code for calculating the difference data between the pixel data of the compression target area and the pixel data of the reference area and providing it for the transform coding. And a compression circuit.

According to a sixty-second aspect of the present invention, there is provided a moving image compression circuit for compressing an input moving image signal by transform coding including DCT and quantization, the average value of pixel values of a compression target area. Of the binarized data of each pixel of the compression target area having a threshold value and the average value of the pixel values of each divided area of the motion vector search area in the reference screen of each pixel of each divided area. The binarized data is compared with each other, and a selection circuit that selects a divided area having the maximum number of coincidences as a reference area, and difference data between pixel data of the compression target area and pixel data of the reference area is calculated. And a predictive coding circuit provided for the transform coding.

In the present invention, as in claims 19 and 63,
The first in the second screen corresponding to the position of the first area of the first screen
The motion vector indicating the difference between the position and the second position of the second area in the second screen having a pixel value similar to that of the first area is calculated as the pixel value of the first area and each area in the second screen. The lower bit of each digital data indicating each pixel value of the first area is deleted, and the lower bit of each digital data indicating each pixel value of the second screen is deleted by comparing the pixel values of The pixel data of the first area after the deletion and deletion of the lower bits and the pixel data of the areas in the second screen after the deletion of the lower bits are respectively compared to each other from the second screen to the second screen. The area is selected. Further, as set forth in claims 20 and 64, each pixel data of the first area after the lower bit is deleted is compared with each pixel data of the area in the second screen after the lower bit is deleted, and they match each other. The region having the maximum number of pixels is selected as the second region.

According to the present invention, the first position in the second screen corresponding to the position of the first area of the first screen and the pixel value of the first area are similar to each other. A method of detecting a motion vector indicating the difference between the second position of the second area in the second screen and the pixel value of the first area by comparing the pixel value of each area in the second screen, The pixel data of the first area is cut out from the first screen, each pixel data is binarized according to a binarization threshold determined by the characteristics of the cut out first area, and the cut-out first
A search area in which the motion vector is to be searched is extracted from the second screen based on the first position corresponding to the area, and the data amount of each pixel data of the extracted search area is the threshold for binarization. It is binarized according to the above and used for the comparison.

[0033]

【Example】

(1) MPEG Encoder First, an MPEG encoder will be described with reference to FIGS. In the system based on the MPEG standard, each screen of a moving image has 8 pixels vertically and 8 pixels horizontally (8 × 8 pixels).
Pixel) blocks are divided and cut out, and DCT, quantization, and variable length coding are performed in block units. In addition, motion compensation is performed in units of macroblocks of 4 blocks (16 × 16 pixels). In predictive coding with motion compensation, B shown in FIG.
Not only a screen that is ahead (past) in time like a picture but also a screen that is behind (future) in time is adopted as a reference screen. In addition, inter-frame compression with motion compensation and intra-frame compression are adaptively selected.

FIG. 2 shows the arrangement of I, P, and B pictures of MPEG and the prediction direction, and FIG. 3 shows a block diagram of an MPEG encoder. The image rearrangement circuit 110 rearranges the screen order of the input moving image data. That is, when a screen later in time is adopted as the reference screen, the latter screen needs to be stored in the memory first, so that the screens are rearranged so that the latter screen is processed first. .
Refer to the previous screen and select P
A screen that is interframe predictive coded by referring to a picture, a previous screen and / or a subsequent screen is called a B picture, and a screen on which interframe predictive coding is not performed by the reference screen is called an I picture. It should be noted that not all macroblocks of a B picture are interframe predictive coded by referring to the previous screen and / or the subsequent screen, but interframe predictive coding because there is no correlation with the previous screen and / or the subsequent screen. There are some macroblocks that are not used. Similarly, not all macroblocks of a P picture are interframe predictive coded with reference to the previous screen,
In some macroblocks, interframe predictive coding is not performed because there is no correlation with the previous screen. A macroblock that is interframe predictive coded using a reference screen is called an inter macroblock, and a macroblock that is not interframe predictive code is called an intra macroblock. Which type of macroblock is indicated by the macroblock type data MBT.

In the scan conversion macroblocking circuit 112,
Each screen is divided into blocks of 8 × 8 pixels. This is because motion vectors and the like are detected in macroblock units, and DCT, quantization, and the like are executed in block units.

The subtractor 114 subtracts each pixel data of the reference block of the reference screen from each pixel data of the current block of the current screen input from the scan conversion macroblocking circuit 112. Further, the difference data of each pixel, which is the subtraction result, is sent to the DCT 116 and DCT is performed. In the case of an intra macroblock, the output data of the scan conversion macroblocking circuit 112 is sent to the DCT 116 as it is.

In the DCT 116, discrete cosine transform is performed in block (8 × 8 pixel) units, and (a) → (b) in FIG.
As described above, each block of 8 × 8 pixels is converted into a coefficient matrix [Cij] of 8 rows × 8 columns of low frequency term to high frequency term. Further, each coefficient Cij is quantized by the quantization circuit 118 as shown in (b) → (c) of FIG. That is, FIG.
As in (d), each coefficient Cij is divided by Qij (= Kij × q), and the remainder is rounded. This significantly reduces the amount of data. The quantization step width q is given by the bit rate control circuit 124.

After quantization, the coefficient data C'ij output in the order shown in FIG. 4C (the order of the coefficient of the low frequency term to the coefficient of the high frequency term) is changed by the variable length coding circuit 120. It is long-coded to further reduce the data amount. The variable-length coded data is temporarily stored in the buffer memory 122, read at a predetermined bit rate, and output as a bit stream.

The difference value between the B picture and the P picture is DC.
The data amount is smaller than that of the I picture because the data is output after being subjected to T and the like. Therefore, in the MPEG system, different target bit amounts are assigned according to the picture type, and the data amount generated for each slice and each macroblock is monitored. The transition of the data amount is compared and evaluated with the target bit amount. For example, when the generated bit amount is larger than the target bit amount, the quantization step width q is increased to coarsely perform the quantization, and when it is smaller than the target bit amount, The quantization step width q is reduced to finely quantize. The buffer memory 122 alleviates fluctuations in the generated bit amount caused by the screen form, screen characteristics, and quantization step width values.

In the MPEG encoder, the storage amount in the buffer memory 122 is monitored and the storage amount in the buffer memory on the MPEG decoder side is simulated to obtain M
The quantization step width q is controlled so that the buffer memory on the PEG decoder side does not overflow. That is,
The quantization step width q is determined by also referring to the empty capacity of the buffer memory 122 and the change amount of the empty capacity of the buffer memory 122. The quantization step width q is usually 1 to 3.
A value of 1 has been adopted. Although not very common, the MPEG standard allows the transfer bit rate to be changed instead of being fixed. When the transfer bit rate is changed, the quantization step width is naturally changed accordingly.

The inverse quantization circuit 126 and the inverse DCT circuit 128 are
It is a local decoder for reproducing image data of a front screen and a rear screen to serve as a reference screen in the MPEG encoder. The reproduced screen is stored in the frame memory 132 and output to the subtractor 114 as described above. When the image data decoded by the local decoders 126 and 128 is difference data, the adder 130 is for adding the image data of the reference screen with motion compensation to the difference data to complete the image.

The image memory 132 stores image data for at least two screens. This screen is an I picture and an I picture, an I picture and a P picture, or a P picture and a P picture. From the terminal 132b of the image memory 132, reference image data is output in macroblock units. In addition, the image data for motion vector detection is output from the terminal 132a to the motion detection circuit 138. In the motion detection circuit 138, a region (reference macroblock) most similar to the current macroblock in the current screen is selected from the reference screen. The processing will be described in detail in a later example.

The motion compensation circuit 134 causes the terminal 132b of the image memory 132 to output the area (reference macroblock area) designated by the motion vector information. As a result, the image data of the reference macroblock is sent to the subtractor 114,
As described above, the difference between the current macroblock and the reference macroblock is calculated, and the difference data is sent to the DCT 116. In addition, the image data of the reference macroblock is added by the adder 13
Sent to the local decoder 126, 128 as described above.
The image is completed by being added to the difference data of the current macroblock decoded by. The processing of the motion compensation circuit 134 is performed with reference to the macroblock type information MBT sent from the mode determination circuit 136. That is, whether to output the front screen, the rear screen, the front screen and the rear screen, or not to output the front screen from the image memory 132 is performed according to the macroblock type information MBT.

The mode determination circuit 136 detects the correlation based on the difference between the current screen and the two screens in the image memory, and outputs the type having the highest compression degree as the macroblock type information MBT. That is, the variance value of the current macroblock (intra macroblock), the variance value of the difference between the current macroblock and the macroblock of the rear screen (backward prediction macroblock), the variance value of the current macroblock and the macroblock of the previous screen (forward prediction macroblock). Block) variance value,
Also, the variance value of the difference between the current macroblock and the preceding and following macroblocks (bidirectional prediction macroblock) is obtained, and the one having the minimum variance value is determined as the macroblock type.

(2) Embodiment of Motion Vector Detecting Circuit Next, the function of finding the region (reference macroblock) most similar to the current macroblock to be compressed from the front and / or rear reference screens is fulfilled. An embodiment of the motion vector detection circuit will be described with reference to FIGS.

(2-1) First Embodiment: FIG. 7 In FIG. 7, blocks having the same functions as in FIG. 1 are designated by the same reference numerals, and the description will be simplified. In addition, in FIG. 1, one screen is described as 12 × 12 pixels and one macroblock is described as 4 × 4 pixels, but the same applies in FIG. 7 for convenience of description. Actually, the number of pixels on one screen is much larger than 12 × 12 pixels, and one macroblock is 16 × 16.
It is a pixel.

Image data of the current screen is stored in the frame memory 10. Each pixel value, that is, the number of bits of each pixel is 8
It is a bit (256 gradations). In the frame memory 12,
The image data of the previous screen (or the subsequent screen may be stored) is stored. Each pixel value is the same as the current screen, 8 bits (256 gradations)
Is.

The binarization circuit 22 binarizes each pixel of the current screen. The binarization threshold is an intermediate value of pixel values of all pixels in the current screen. Here, since one screen has 12 × 12 pixels, an intermediate value of pixel values of 12 × 12 = 144 pixels,
That is, the 77th or 78th largest pixel value in the current screen is set as the threshold value. By using this pixel value (reference value = intermediate value) as a threshold value, all pixels in the current screen are binarized. That is, each pixel of 8 bits = 256 gradations has 1 bit =
It is binarized into two gradations (white / black) and sent to the blocking circuit 24. Further, the threshold value is sent to the binarization circuit 18.

In the binarization circuit 18, all the pixels in the front screen (or the rear screen, which is the reference screen) are binarized using the reference value sent from the binarization circuit 22 as a threshold value. .
All binarized pixels (here, 12 × 12 = 144 pixels) are sent to the motion vector detection circuit 20.

In the blocking circuit 24, the binarized current screen (here, 12 × 12 = 144 pixels) is divided into blocks (here, 4 × 4 = 16 pixels), and the motion vector detection circuit It is output to 20 in block units.

In the motion vector detection circuit 20, the area most similar to the current macroblock sent from the block formation circuit 24 is searched for in the reference screen sent from the binarization circuit 18, and this is found. It is a reference macroblock. For this search processing, any of the above-mentioned methods may be used. When the reference macroblock is searched, the current screen (first
From the coordinate position (first position) in the reference screen (second screen) corresponding to the coordinate position of the current macroblock (first region) in the screen) to the coordinate position (second position) in the reference macroblock (second region) ) Is sent to the motion vector correspondence blocking circuit 28 as motion vector information.

In the motion vector block circuit 28,
An area (here, 4 × 4 = 16 pixels) at the coordinate position designated by the motion vector is cut out from the reference screen as a reference macroblock and sent to the difference image output circuit 30. Here, as the reference screen, the frame memory 12
The screen sent from is adopted. That is, a screen of 8 bits = 256 gradations which is not binarized is adopted.

The difference image output circuit 30 calculates the difference between the reference macroblock and the current macroblock (here, 4 × 4 = 16 pixels) cut out by the blocking circuit 14 from the current screen. Here, the screen sent from the frame memory 10 is adopted as the current screen. That is, a screen of 8 bits = 256 gradations which is not binarized is adopted.

In the first embodiment, since the binarization circuit 22 performs the binarization before the blocking in the block formation circuit 24, the binarization processing in the binarization circuit 18 is There is no need to do this for each current macroblock. That is, one binarization process per screen is sufficient. Further, in the first embodiment, the intermediate value of the pixel values of the current screen is adopted as the binarization threshold value, but this can be obtained only by the comparison operation of the pixel values of each pixel, so the processing becomes simple. . That is, it is not necessary to calculate the average value. In addition, this effect is
It can also be enjoyed when the value conversion circuit 22 is provided. In this case, if the reference screen is binarized only within the motion vector search range, the amount of calculation in the binarization circuit 18 can be reduced.

(2-2) Second Embodiment: FIG. 8 The second embodiment has the configuration mentioned at the end of the first embodiment. That is, the blocking circuit 24 (in FIG. 8, the blocking circuit is
14 is also used), the binarization circuit 22 is provided in the subsequent stage, and the binarization of the reference screen is performed only within the motion vector search range. Hereinafter, parts different from those in FIG. 7 will be described, the same parts will be denoted by the same reference numerals, and description thereof will be omitted.

The motion vector detection circuit 21 is a binarization circuit 19
, The search range information indicating the search range of the motion vector is output. The binarization circuit 19 binarizes each pixel in the area designated in the reference screen by the search range information. A reference value (average value) sent from the binarization circuit 16 is adopted as the binarization threshold value.

In the binarization circuit 16, the average value of the pixel values of the pixels in the current macroblock cut out from the current screen by the blocking circuit 14 is obtained, and the current macroblock is binarized using this average value as a threshold. Be converted. Also, this average value is sent to the binarization circuit 19 and, as described above, the binary value in the binarization circuit 19 is changed.
Used for valuation processing.

Since the average value is calculated every time the current macroblock is cut out from the blocking circuit 14,
In the second embodiment, each pixel within the motion vector search range of the reference screen is binarized corresponding to each current macroblock. In the second embodiment, the motion vector search range is adopted as the binarization range in the reference screen, but it is not necessary to exactly match the binarization range with the motion vector search range, and the reference screen is not required. It suffices if it can be set so that the motion vector search range is included in the binarized range in the above.

(2-3) Third Embodiment: FIG. 9 In the third embodiment, a binarization circuit 32 is provided in place of the binarization circuit 22 in the first embodiment, and the binarization circuit 18 is provided. Instead of this, a binary circuit 34 is provided. Since the other structure is the same as that of the first embodiment, the description thereof will be omitted.

In the binarization circuit 32, each pixel in the current screen is binarized according to the size of the pixel on the right. For example, first, set the pixel value of the first pixel of the current screen to "1.
= Black ” For the next pixel (current pixel), its pixel value is compared with the pixel value of the previous pixel, and as a result, if the pixel value of the next pixel ≤ the pixel value of the previous pixel, the pixel value of the current pixel Is set to “1 = black”. On the contrary, if the pixel value of the next pixel> the pixel value of the immediately preceding pixel, the pixel value of the current pixel is set to “0 = white”. In addition,
The first pixel on the second line is compared to the last pixel on the first line.

In the binarization circuit 34, the binarization processing is performed on each pixel in the reference screen in the same manner as the binarization circuit 32. That is, in the third embodiment, unlike the first embodiment,
Although the threshold value based on the current screen is not used for the binarization process of the reference screen, the same logic is applied to the current screen and the reference screen as the binarization logic. in this way,
In the third embodiment, each pixel is set to 2 according to the size of the adjacent pixels.
Since it is digitized, it is not necessary to calculate the average value, and the amount of calculation can be reduced.

(2-4) Fourth Embodiment: FIG. 10 In the fourth embodiment, a lower bit deleting circuit 36 is provided in place of the binarizing circuit 16 in the second embodiment, and the binarizing circuit is provided. In this configuration, a lower bit deleting circuit 38 is provided instead of 19. Since the other configurations are the same as those of the second embodiment, the description thereof will be omitted.

In the lower bit deletion circuit 36, the lower 3 bits of each pixel (8 bits = 256 gradations) of the current macroblock are deleted, and the upper 5 bits = 32 gradations of pixel data, respectively, to obtain the motion vector detection circuit. Sent to 20. In the lower bit deletion circuit 38, each pixel in the reference screen (8 bits = 2
The lower 3 bits of (56 gradations) are deleted and the upper 5 bits = 32 gradations of pixel data are sent to the motion vector detection circuit 40.

In the motion vector detection circuit 40, each pixel is 5
Based on the current macroblock with 32 gradations and the reference screen with each pixel having 5 bits, the above-mentioned method (eg, a method for searching for an area where the sum of absolute differences or the sum of squared differences is minimized) Etc.) is used to find the area most similar to the current macroblock from the reference screen and set it as the reference macroblock. Further, the motion vector information designating this reference macroblock is sent to the motion vector correspondence block formation circuit 28.

As described above, in the fourth embodiment, since the number of bits of the image data for motion vector detection is reduced,
The calculation amount can be reduced without significantly lowering the motion vector detection accuracy. As a matter of course, if the number of lower bits to be reduced is increased, the circuit scale can be further downsized and reduced, but the motion vector detection accuracy also decreases. As a publicly known example of detecting the motion vector by deleting the lower bits, Japanese Patent Laid-Open No. 4-3
There is a 23781 publication. In this publication, 8-bit moving image data is made 10 bits by HPF, and then the lower 2 bits are deleted.

Further, in the motion vector detection circuit 40,
When the reference macroblock is detected by the “method of searching the area where the number of pixels whose pixel values match each other is maximum”,
Further, the circuit scale can be reduced. In this case, the detection accuracy is improved by increasing the number of bits to be deleted by the lower bit deleting circuits 36 and 38. However, the lower bit deletion circuit 3
If too many bits are deleted in 6,38, the detection accuracy deteriorates.

In the case of MPEG in which one macroblock is composed of 16 × 16 pixels, if the lower 6-4 bits of each pixel data are deleted and the upper 2-4 bits are left,
The amount of calculation can be reduced, and the degree of deterioration of image quality can be reduced. That is, it is possible to optimize the calculation amount reduction and the image quality deterioration prevention.

In each of the above embodiments, the processing relating to the current screen and the previous screen (or the subsequent screen may be performed) has been described, but the same applies to the processing relating to the current screen and the previous-second screen and the current screen and the subsequent-screen. . In such a case, the search range of the motion vector is generally changed according to the temporal distance between the screens.

Further, although the present invention has been described on the basis of the functional block diagram in each of the above-mentioned embodiments, it is naturally possible to realize the present invention by using software. Further, although the motion vector itself is detected in each of the above-described embodiments, the present invention can also be applied to one of so-called two-step search in which a motion vector is roughly detected and then finely detected. .

(3) Embodiment of Moving Image Compressing Circuit Next, an embodiment of a moving image compressing circuit for performing predictive coding using any one of the above motion vector detecting circuits will be described with reference to FIGS. Explain. In addition, the compression efficiency and the image quality of each circuit are evaluated with reference to FIGS.

(3-1) Fifth Embodiment: FIG. 11 The moving image data of 8 bits = 256 gradations is input from the input terminal 42. From this moving image data, the motion vector is detected by the prediction information detection circuit 44. The configuration in which the MV corresponding blocking circuit 28 and the difference image output circuit 30 are added to the prediction information detection circuit 44 is the same as that of the fourth embodiment (FIG. 10). Therefore, description of these circuits is omitted.

In the fourth embodiment (FIG. 10), 1
Although the screen is described as 12 × 12 pixels and one macroblock is 4 × 4 pixels, in the fifth embodiment, the number of pixels in one screen is much larger, and one macroblock is composed of 16 × 16 pixels. It As the number of pixels constituting one macroblock is larger than that of the fourth embodiment (FIG. 10), the lower 3 bits are deleted and the upper 5 bits are left in the lower bit deleting circuits 36 and 38 of FIG. The existing structure is changed to a structure in which the lower 4 bits are deleted and the upper 4 bits are left in the lower bit deleting circuits 36 and 38 of FIG.

In the adaptive coding circuit 46, interframe predictive coding with motion compensation (coding by the inter coding circuit 50) and intraframe coding (coding by the intra coding circuit 52) are selectively performed. To be done. This selection is controlled by the code amount comparison circuit 48. That is, the code amount by the inter-frame predictive coding with motion compensation and the code amount by the intra-frame coding are compared in the code amount comparison circuit 48 so that the output of the coding circuit with the smaller code amount is selected. Then, the switch 68 is switched.

In the inter coding circuit 50 for performing inter-frame predictive coding with motion compensation, the pixel data of the current macroblock cut out from the current screen and the pixel data of the reference macroblock cut out according to the motion vector data from the reference screen are used. For the difference data P, D in the DCT circuit 54
CT processing, quantization processing in the quantization circuit 56, and variable length coding processing in the variable length coding circuit 58 are performed. Further, the output of the variable length coding circuit 58 and the motion vector data are combined in the combining circuit 60. The combined output is sent to one terminal of the switch 68.

In the intra-coding circuit 52 for intra-frame coding, the DCT processing in the DCT circuit 62, the quantization processing in the quantization circuit 64, and the pixel data of the current macroblock cut out from the current screen are performed. The variable length coding circuit 66 performs the variable length coding process, and the output of the variable length coding circuit 66 is sent to the other terminal of the switch 68.

In the switch 68, as described above, one of the code by the inter-frame predictive coding with motion compensation and the code by the intra-frame coding sent as described above is
It is selected by a command from the code amount comparison circuit 48 and output to the outside.

FIG. 6 shows the relationship between the compression efficiency (code amount) of inter coding and intra coding and the characteristic of the screen.
Will be described with reference to. Also, how intra / inter coding is selected to improve the compression rate will be described. When the inter-picture correlation is small like the previous frame and the current frame in (a), intra-coding is selected because intra-coding has a higher compression rate. In the case of (a), the accuracy of the motion vector detected by the prediction information detection circuit 44 becomes low.

When the inter-picture correlation and the intra-picture correlation are large as in the previous frame and the current frame in (b), based on the upper 4-bit image data input to the motion vector detection circuit 40. It is difficult to accurately detect a motion vector. However, in such an image, since intra-frame correlation is large, it is possible to obtain data having a sufficiently high degree of compression by intra-frame coding. Therefore, regardless of which output is selected by the code amount comparison circuit 48, the reduction in compression is small.

When the inter-picture correlation is large but the intra-picture correlation is small as in the previous frame and the current frame in (c), based on the upper 4-bit image data input to the motion vector detection circuit 40. A motion vector with sufficiently high accuracy can be detected. Therefore, the code amount comparison circuit 48 selects the output of the inter encoding circuit 50, whereby it is possible to obtain data having a sufficiently high degree of compression. That is, the decrease in the degree of compression is small.

As described above, in the fifth embodiment, since the calculation amount is reduced by detecting the motion vector based on the image data in which the lower bits are deleted, the motion vector detection accuracy is slightly lowered. Since this decrease is compensated by adaptively switching between inter coding and intra coding, a high-quality image with a high degree of compression and a small amount of calculation is obtained as a whole. That is, the degree of compression and the image quality are optimized.

(3-2) Sixth Embodiment: FIG. 12 In the sixth embodiment, the prediction information detection circuit 44, the inter coding circuit 50, and the intra coding circuit 52 in the fifth embodiment are described. Each is provided with a frame memory.
That is, the prediction information detection circuit 44 is provided with the frame memory 10a for the current screen and the frame memory 12a for the previous screen, and the inter-encoding circuit 50 is provided with the frame memory 10b for the current screen.
The frame memory 12b for the previous screen is provided, and the intra-encoding circuit 52 is provided with the frame memory 10c for the current screen. Since the other structure is the same as that of the fifth embodiment, the same reference numerals are given to the same portions and the description thereof will be omitted.

Since each circuit is provided with a frame memory as described above, each circuit can be made independent. For example, in the prediction information detection circuit 44, the lower bit deletion circuit 36a can be arranged at the entrance, so that the total calculation amount can be reduced.

(3-3) Seventh Embodiment: FIG. 13 In the seventh embodiment, a variance value comparison circuit 70 is provided in place of the code amount comparison circuit 48 of the sixth embodiment. Since the other structure is the same as that of the sixth embodiment, the same reference numerals are given to the same portions and the description thereof will be omitted.

In the variance value comparison circuit 70, the variance value and the average value of the difference data output from the difference image output circuit 30 of the inter encoding circuit 50 and the image output from the blocking circuit 14c of the intra encoding circuit 52. The variance and average of the data are determined and compared. Further, as a result of the comparison, the output of the circuit having the smaller variance value is selected. The technique itself for selecting an encoding method with high compression efficiency based on the variance value is disclosed in JP-A-6-133301 and JP-A-5-137129 and is well known.

(3-4) Eighth Embodiment: FIG. 14 The eighth embodiment is the same as the seventh embodiment except that the DCT processing,
Each circuit for performing the quantization processing and the variable length coding processing is shared by the inter coding circuit and the intra coding circuit. Since the other structure is the same as that of the seventh embodiment, the same reference numerals are given to the same portions and the description thereof will be omitted.

As shown in the figure, in the code amount comparison circuit 70, the variance value and the average value of the difference data output from the difference image output circuit 30 and the variance value and the average value of the image data output from the blocking circuit 14c. Is calculated and compared, and as a result, the switch with the smaller variance value is input to the DCT circuit 62a, the switch provided in the preceding stage of the DCT circuit 62a.
68a is switched. Since the difference data output from the difference image output circuit 30 and the image data output from the blocking circuit 14c need to switch the characteristics of processing after DCT, the variance value comparison circuit 70 controls the difference data. , The characteristics of these circuits are switched. Also, in the combination circuit 60a, the motion vector data is combined with the output of the variable length encoding circuit 66a only when the difference data output from the difference image output circuit 30 is selected.

(3-5) Ninth Embodiment: FIG. 15 In the ninth embodiment, the lower bit deleting circuits 36 and 38 of the prediction information detecting circuit 44 of the fifth embodiment (FIG. 11) are replaced by binarization. A circuit provided with the circuits 16a and 16b is adopted as the prediction information detection circuit 44a, and the same circuit as the eighth embodiment (FIG. 14) is adopted as the inter coding circuit and the intra coding circuit. The selection of the inter coding circuit and the intra coding circuit is performed by the variance value comparison circuit 70 as in the eighth embodiment. Since the other structure is the same as that of the eighth embodiment, the same reference numerals are given to the same portions,
Description is omitted.

In the binarizing circuit 16a, the binarizing circuit 16a shown in FIG.
Similarly, the binarization is performed using the average value of the pixel values of the current macroblock (16 × 16 pixels) as a threshold value. In the binarization circuit 16b, for each pixel in the motion vector search range (48 × 48 pixels centered on the coordinate position corresponding to the current macroblock), the average value of the pixels in the range is set as a threshold value of 2 Value conversion is performed.

In the motion vector detection circuit 20, the outputs of the two binarization circuits 16a and 16b are compared, the number of matching pixels is counted, and the region having the largest matching number is selected as the reference macroblock. To be done. In this way, the prediction information detection circuit 44a detects, as a reference macroblock, an area in the reference screen where the variance value of the difference data with the current macroblock is the smallest. In this process, the data amount of the difference image output circuit 30 is more likely to increase, but the flatness of the difference image is higher (the variance value is smaller).
Since the possibility is increased, the compression efficiency by the DCT process is improved. Further, by performing such processing, the motion vector can be detected even when the image gradually fades in or fades out gradually.

(3-6) Tenth Embodiment: FIG. 16 In the tenth embodiment, the binarization circuit 16b of the ninth embodiment is
It is replaced with the binarization circuit 16c. This binarization circuit
In 16c, the average value of the pixels in the region is calculated for each region to be compared in the motion vector search range, and this average value is used as the threshold for binarizing the pixels in the region. Although the amount of calculation is larger than that in the ninth embodiment, it is possible to provide a better image at the time of fading in or fading out. Since the other structure is the same as that of the ninth embodiment, the same reference numerals are given to the same portions and the description thereof will be omitted.

(3-7) Evaluation of deletion of lower bits: FIGS. 17 to 22 Finally, when the amount of each image data of the current macroblock for motion vector detection and the reference screen is reduced by deleting the lower bits The image quality of is simulated and evaluated. As an encoder for this purpose, the MPEG encoder of FIG. 3 was used.

FIG. 18 shows that the compressed moving image coded according to the MPEG-2 standard is decoded and the SN of the decoded moving image is decoded.
The result of simulating the ratio is shown. Regarding BR and TM, the number of high-order bits after reduction is shown on the horizontal axis. As this moving image, a landscape (Flower Garden) moving laterally at a constant speed was used. The output bit rate was 4 Mbps. The search range is ± 16 × 16 pixels per frame as shown in FIG.

In FIG. 18, FS is an SN ratio of a decoded image when a motion vector is detected by a conventional full search method, and TS is a telescopic image which has been conventionally considered to be effective by examination in MPEG. SN ratio of decoded image when motion vector is detected by search method, AC
Is an SN ratio in the case where a motion vector is detected based on the number of matching pixels in the current macroblock and the reference screen, which is binarized using the average value of the pixel values of the current macroblock as a threshold value in the same manner as described in FIG. , BR is the SN when the lower bit is deleted and the motion vector is detected by the full search method.
The ratio TM indicates the SN ratio when the motion vector is detected based on the number of matching pixels of the current macroblock with the lower bits deleted and the reference screen.

As is apparent from FIG. 18, the SN ratio of BR in which the lower 4 bits are deleted and the motion vector is detected based on the number of matching pixels in the upper 4 bits is almost the same as that in the full search FS. Further, although the AC method does not reach the SN ratio of the full search FS, it has a better value than the TS method. Further, the TM method and the BR method can be made to have better values than the TS method by appropriately selecting the number of bits to be reduced.

FIG. 19 shows the same image as that of FIG. 18 when the bit rate is 9 Mbps, and FIG. 20 shows the case of a 4 Mbps image (Mobile & Calender) in which several objects move at low speed.
Fig. 21 shows 4 Mbps video with high speed and random movement
In the case of (Cheerleaders), FIG. 22 is a case of an image (Football) which is very high speed and has few high frequency components.

In the example of FIG. 21, the TS method is generally superior to the AC method, the TM method, and the BR method, but there is not much difference in practical use because the SN ratio is high in all the methods. Also,
In the example of FIG. 22, as compared with the AC method, the TM method, and the BR method, T
Although the S method is generally excellent, the S / N ratio is high in all the methods, so there is not much difference in practical use.

As is clear from FIGS. 18 to 22, the TM method for detecting the motion vector based on the number of matching pixels of each image data reduced to the upper 4 bits can obtain a practically sufficient image quality. Further, as is clear from FIGS. 18 to 22, the BR method in which the motion vector detection is performed by performing a full search of each image data reduced to the upper 4 bits can obtain a practically sufficient image quality.

[0098]

As described above, according to the present invention, the calculation amount of motion vector detection (= reference macroblock detection) can be reduced, so that the circuit configuration can be simplified. Further, since the selection of inter-coding and intra-coding is optimized by the combination with the motion vector detection method, the amount of calculation is small, the degree of compression is high, and compressed moving image data having a desired image quality is obtained. Obtainable. Further, by optimizing the deletion number of the lower bit of each image data of the current macroblock for motion vector detection and the reference screen, the characteristics of the moving image, that is, a scene with little motion, a scene in which the background moves uniformly,
It is possible to obtain compressed moving image data with a small amount of calculation with a simple circuit configuration, with an optimum image quality according to characteristics such as a scene of random intense motion.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing the configuration and function of a conventional motion vector detection circuit.

FIG. 2 is an explanatory diagram showing a prediction direction and a sequence of I, P, and B pictures of MPEG.

FIG. 3 is a block diagram showing an MPEG encoder of the embodiment.

FIG. 4 is an explanatory diagram showing DCT processing and quantization processing.

FIG. 5 is an explanatory diagram showing a motion vector detection method.

FIG. 6 is an explanatory diagram showing the magnitude of pixel value distribution and inter-screen / in-screen correlation.

FIG. 7 is a block diagram showing a circuit of the first embodiment.

FIG. 8 is a block diagram showing a circuit of a second embodiment.

FIG. 9 is a block diagram showing a circuit of a third embodiment.

FIG. 10 is a block diagram showing a circuit of a fourth embodiment.

FIG. 11 is a block diagram showing a circuit of a fifth embodiment.

FIG. 12 is a block diagram showing a circuit of a sixth embodiment.

FIG. 13 is a block diagram showing a circuit of a seventh embodiment.

FIG. 14 is a block diagram showing a circuit of an eighth embodiment.

FIG. 15 is a block diagram showing a circuit of a ninth embodiment.

FIG. 16 is a block diagram showing a circuit of a tenth embodiment.

FIG. 17 is an explanatory diagram showing each detection method of the characteristic diagrams shown in FIGS. 18 to 22.

FIG. 18: 4 Mbp where landscape moves laterally at constant speed
The characteristic view which shows the number of bits of the pixel value for a motion vector detection in a moving image of s, and SNR about each detection method.

FIG. 19: 9 Mbp where landscape moves laterally at a constant speed
The characteristic view which shows the number of bits of the pixel value for a motion vector detection in a moving image of s, and SNR about each detection method.

FIG. 20 is a characteristic diagram showing, for each detection method, the number of bits and SNR of a pixel value for motion vector detection in a 4 Mbps moving image in which several objects move at a constant speed.

FIG. 21 is the number of bits of a pixel value for motion vector detection and S in a high-speed 4 Mbps moving image with many random motions.
The characteristic view which shows NR about each detection method.

FIG. 22: 4 Mbp with extremely high speed and few high frequency components
The characteristic view which shows the number of bits of the pixel value for a motion vector detection in a moving image of s, and SNR about each detection method.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Anpachi Hamamoto 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Hideo Kodama 2-5 Keihanmoto, Moriguchi City, Osaka Prefecture No. 5 Sanyo Electric Co., Ltd.

Claims (65)

[Claims] 1. A circuit for detecting a motion vector indicating a spatial position of a reference area in a reference frame from a spatial position of a current area in a current frame, wherein gray scales in a predetermined order in the current area. Extraction means (22) for extracting pixel data in the and outputting as threshold data
A current area binarization circuit (22) for binarizing each pixel data in the current area with the threshold data; and comparing each pixel data in the reference area with the threshold data. The reference area binarization circuit (18) for binarizing the data with the reference area and the data of the reference area that has been binarized are compared to obtain the strongest correlation with the current area. A motion vector detection circuit having a search circuit (20) for searching for a reference area having the output and outputting a spatial position of the reference area. 2. The motion vector detection circuit according to claim 1, wherein the predetermined order is a center order. 3. A circuit for detecting a motion vector indicating a spatial position of a reference area in a reference frame from a spatial position of the current area in the current frame, wherein each pixel data in the current area is stored in the current area. Current region binarization circuit (32, and, 24) for binarizing by comparing with adjacent pixel data in the reference frame, and each pixel data in the reference frame adjacent pixel in the reference frame A current area binarization circuit (34) for binarizing by comparing with the data, and the current area by comparing the binarized data of the current area with the data of the binarized reference frame. And a search circuit (20) for finding a reference area having the strongest correlation with and outputting the spatial position of the reference area. 4. The current area binarization circuit (32, and 24) according to claim 3, wherein each pixel data in the current frame is compared with adjacent pixel data in the frame. A motion vector having a current frame binarization circuit (32) which binarizes the current frame, and a division circuit (24) which divides the binarized current frame into a plurality of areas and outputs the current area. Detection circuit. 5. A circuit for detecting a motion vector indicating a spatial position of a reference area in a reference frame from a spatial position of a current area in the current frame, wherein each pixel data in the current frame is binarized. A current frame binarization circuit (22, 32), a division circuit (24) for dividing the binarized current frame into a plurality of areas and outputting the current area, and pixel data in the reference frame A reference frame binarization circuit (18, 34) for binarizing the present region, and comparing the binarized data of the current region with the data of the binarized reference frame, A motion vector detection circuit having a search circuit (20) for finding a reference area having a correlation and outputting the spatial position of the reference area. 6. A circuit for detecting a motion vector indicating a spatial position of a reference area in a reference frame from a spatial position of a current area in a current frame, wherein upper bits are extracted from each pixel data in the current area. The first extraction circuit (3
6), a second extraction circuit (38) for outputting a reference frame in which gradation is reduced by extracting upper bits from each pixel data in the reference frame, and data in the current area in which gradation is reduced And a search circuit (40) for finding out a reference area having the strongest correlation with the current area by comparing the data of the reference frame whose gradation has been dropped and outputting the spatial position of the reference area, Vector detection circuit. 7. The exploration circuit (40) according to claim 6, wherein each region cut out in a predetermined order from the grayscale-removed reference frame is compared with each grayscale-removed current region. By doing so, a detection circuit that detects a pair of pixels having the same coordinate and data value in the area, a counter that counts the number of pixels of the pair, and an area having the maximum number of pixels of the pair is extracted as the reference area. And a motion vector detection circuit having an output circuit for outputting a spatial position. 8. A circuit for detecting a motion vector indicating a spatial position of a reference area in a reference frame from a spatial position of the current area in the current frame, the floor of the current area according to a criterion determined by a characteristic of the current area. A first gradation reduction circuit (16) for degrading the tone, an extraction circuit (21) for extracting an exploration region in which the reference region is to be searched for in the reference frame based on the spatial position of the current region; A second gradation reduction circuit (19) for decreasing the gradation according to the reference, and comparing the data of the current area of which the gradation has been decreased with the data of the exploration area of which the gradation has been decreased with the current area. A motion vector detection circuit having a search circuit (21) for finding a reference area having the strongest correlation and outputting the spatial position of the reference area. 9. The motion vector detection circuit according to claim 8, wherein the reference is threshold value data for binarization. 10. A system for compressing a moving image into a bit stream by sequentially using DCT, quantization, and entropy coding, wherein the reference frame is grayed out by extracting upper bits of each pixel data. , Comparing the current macroblocks whose gradations have been reduced by extracting the upper bits of each pixel data to find the macroblock having the strongest correlation with the current macroblock as a reference macroblock from the reference frame, A motion vector detection circuit that detects a motion vector indicating the spatial position of the searched reference macroblock in the reference frame from the spatial position of the current macroblock in the current frame (4
4), a subtraction circuit for calculating the difference between each pixel data of the current macroblock and the corresponding pixel data of the reference macroblock indicated by the motion vector, and outputting the difference to the circuit that executes the DCT ( 30), and a video compression system having. 11. The moving image compression system according to claim 10, wherein each of the pixel data is 8-bit data, and the extracted upper bits are 4 bits. 12. A moving picture compression system for converting a moving picture into a bit stream, wherein the reference frame having gradation reduced by extracting the upper bits of each pixel data and the upper bits of each pixel data are extracted. By comparing the current macroblocks whose gradations have been reduced, the macroblock having the strongest correlation with the current macroblock is searched for as a reference macroblock from the reference frame, and the current macroblock in the current frame is searched. A motion vector detection circuit that detects a motion vector indicating the spatial position of the reference macroblock found in the reference frame from the spatial position of
4) and a conversion coding circuit (62,
64, 66/54, 56, 58), calculating the difference between each pixel data of the current macroblock and the corresponding pixel data of the reference macroblock indicated by the motion vector, A subtraction circuit (30) for outputting as differential pixel data, a comparison circuit (48) for comparing the data amount obtained by transform coding the current macroblock and the data amount obtained by transform coding the difference macroblock, Of the compressed current macroblock and the compressed differential macroblock, a control circuit (48, 68) for controlling the transform coding circuit so that the one with a smaller data amount is output from the transform coding circuit, Video compression system having. 13. A moving picture compression system for converting a moving picture into a bit stream, wherein the reference frame in which gradation is reduced by extracting the upper bits of each pixel data and the upper bits of each pixel data are extracted. By comparing the current macroblocks whose gradations have been reduced, the macroblock having the strongest correlation with the current macroblock is searched for as a reference macroblock from the reference frame, and the current macroblock in the current frame is searched. A motion vector detection circuit that detects a motion vector indicating the spatial position of the reference macroblock found in the reference frame from the spatial position of
4) and a conversion coding circuit (62,
64, 66/54, 56, 58, or, 62a, 64a, 66a, 60a), each pixel data of the current macroblock, of each corresponding pixel data of the reference macroblock indicated by the motion vector A subtraction circuit (30) that calculates a difference and outputs it as difference pixel data of a difference macroblock, a comparison circuit (70) that compares the variance value of the current macroblock and the variance value of the difference macroblock, and the current Of the variance value of the macroblock and the variance value of the difference macroblock, the control circuit for controlling the transform coding circuit so that the one having the smaller variance value is compressed and output by the transform coding circuit (79, 68a). ), And a video compression system having. 14. The motion vector detection circuit according to claim 12, wherein the motion vector detection circuit (44) extracts a high-order bit from each pixel data in the current macroblock to reduce a gradation. A first extraction circuit (36) for outputting a macroblock, and a second extraction circuit (38) for outputting a reference frame whose gradation is reduced by extracting upper bits from each pixel data in the reference frame, Each pixel data of the current macroblock whose gradation has been dropped,
A subtraction circuit (40) for calculating the difference between each pixel data corresponding to each macroblock cut out in a predetermined order from the grayscale-removed reference frame, and the sum of absolute values of each difference data. A moving image compression system, comprising: an addition circuit (40) that calculates for each difference macroblock; and an output circuit (40) that extracts the macroblock with the smallest sum as a reference macroblock and outputs the spatial position. 15. The present invention according to claim 12 or 13, wherein the motion vector detection circuit (44) extracts a high-order bit from each pixel data in the current macroblock to reduce a gradation. A first extraction circuit (36) for outputting a macroblock, a second extraction circuit (38) for outputting a reference frame whose gradation is reduced by extracting upper bits from each pixel data in the reference frame, Detects a pair of pixels with the same coordinates and data value in the macroblock by comparing each macroblock cut out in a predetermined order from the out-of-sync reference frame with the current macroblock with the grayscale. Detection circuit (40)
A counter (40) for counting the number of pixels in the pair, and an output circuit for extracting the macroblock having the maximum number of pixels in the pair as the reference macroblock and outputting the spatial position
A video compression system having (40) and. 16. The DCT circuit (62, 54, 62a) according to claim 12, wherein the transform coding circuit transforms a block of pixel data into a coefficient matrix of frequency terms by discrete cosine transform. A moving picture compression system, comprising: a quantizing circuit (64, 56, 64a) for quantizing the coefficient. 17. A moving picture compression system for converting a moving picture into a bit stream, wherein binarization of each pixel data of a current macro block in a current screen is performed by an average value of the macro block. A circuit (16a) and an extraction circuit (20) for extracting a search area in which a reference macroblock is to be searched based on the spatial position of the current macroblock
And a search area binarization circuit (16b) for binarizing each pixel data of the search area with an average value of the search area, and each macro cut out from the binarized search area in a predetermined order. A detection circuit (20) for detecting a pair of pixels having the same coordinate and data value in the macroblock by comparing the block and the binarized current macroblock, and a counter (20) for counting the number of pixels of the pair. 20), and an output circuit for extracting the macroblock having the maximum number of pixels of the pair as the reference macroblock and outputting the spatial position
(20) A moving image compression system including: 18. A moving picture compression system for converting a moving picture into a bit stream, wherein binarization is performed on each pixel data of a current macro block in a current screen with an average value of the macro block. A circuit (16a) and an extraction circuit (20) for extracting a search area in which a reference macroblock is to be searched based on the spatial position of the current macroblock
And a reference selection macroblock binarization circuit (16c) that binarizes each pixel data of each macroblock cut out in a predetermined order from the binarized search area with an average value of each macroblock. ) And each of the binarized macroblocks and the binarized current macroblock are compared with each other, thereby detecting a pair of pixels having the same coordinates and data values in each macroblock for each macroblock. A circuit (20), a counter (20) that counts the number of pixels of the pair, and an output circuit that outputs a spatial position by extracting the macroblock having the maximum number of pixels of the pair as the reference macroblock.
A moving picture compression system comprising: (20); and a motion vector detection circuit (20) for detecting a motion vector indicating the spatial position of the reference macroblock from the spatial position of the current macroblock. 19. A method of detecting a motion vector indicating a spatial position of a reference macroblock in a reference frame from a spatial position of a current macroblock in a current frame, the method comprising: Extract the bits, extract the upper bits from each pixel data in the reference frame, and refer to the macroblock that has the strongest correlation with the current macroblock that has been grayed from the grayed-down reference frame. A motion vector detection method to search for. 20. The step of locating the reference macroblock according to claim 19, wherein each of the macroblocks cut out in a predetermined order from the grayscaled reference frame and the current grayscaled macroblock are extracted. By detecting each pair of pixels having the same coordinate and data value in the macroblock by comparing, the number of pixels in the pair is counted, and the macroblock with the largest number of pixels in the pair is extracted as the reference macroblock. A motion vector detection method that outputs the spatial position as a result. 21. A method of detecting a motion vector indicating a spatial position of a reference macroblock in a reference frame from a spatial position of a current macroblock in a current frame, the method being based on a criterion determined by a characteristic of the current macroblock. Lowering the gradation of the macroblock, extracting a search area in which the reference macroblock should be searched from the reference frame based on the spatial position of the current macroblock, lowering the gradation of the search area according to the reference, A motion vector detecting method, wherein a reference macroblock having the strongest correlation with the dropped current macroblock is searched from within the search region having the grayscale dropped, and the spatial position of the reference macroblock is output. 22. The motion vector detecting method according to claim 21, wherein the reference is threshold value data for binarization. 23. A binarization method of binarizing a digital video signal with a reference value as a boundary in order to detect a motion vector, wherein the reference values are arranged in order of magnitude of the digital video signal. A binarization method, wherein the values of pixels having a predetermined rank are used. 24. The binarization method according to claim 23, wherein the predetermined rank is a value that is half the number of pixels of the digital video signal. 25. A binarizing method for binarizing a digital video signal in order to detect a motion vector, which is binarized by a result of comparison with a pixel next to the same screen. 26. The binarization method according to claim 25, wherein the binarization is performed as a pre-processing for block division. 27. A motion vector detecting method for detecting a motion vector by dividing a screen into blocks and detecting a motion vector for each block, wherein a binarization process of a digital video signal for detecting a motion vector is performed. A motion vector detecting method performed as a pre-process of the block division. 28. A multi-bit digital video signal creating method for creating a multi-bit digital video signal in order to detect a motion vector by comparing multi-bit digital video signals of a plurality of screens. A method for creating a multi-bit digital video signal, wherein the lower bits of the signal are deleted to create the multi-bit digital video signal for motion vector detection. 29. A motion vector detecting method for detecting a motion vector by comparing multi-bit digital video signals of a plurality of screens, wherein a lower bit of each input multi-bit digital video signal is deleted to detect a motion vector. A motion vector detecting method in which a multi-bit digital video signal is created and a motion vector is detected from the number of pixels having the same values of the multi-bit digital video signals of a plurality of screens. 30. A motion vector detecting method in which the first screen is divided into blocks, different data is detected for each block, and the second screen is processed based on the detected data. The vector detection method is characterized in that the range of the above process is limited according to the motion vector search range. 31. The first screen is divided into blocks, reference value data for binarization processing is detected for each block, and the second screen is binarized based on the reference value data. 31. The motion vector detecting method according to claim 30, wherein the range of the binarization process on the second screen is limited according to a motion vector search range. 32. An MPEG encoder, comprising: a motion vector detection circuit for deleting a lower bit of a digital video signal and detecting a motion vector in the digital video signal of an upper bit. 33. An MPEG encoder, comprising: a motion vector detection circuit for deleting a lower bit of a digital video signal and detecting a motion vector with a higher 4-bit digital video signal. 34. A motion vector detection circuit (44,138) for deleting a lower bit of a digital video signal and detecting a motion vector for each divided screen by an upper bit, and a difference screen of the divided screen by using this motion vector. Then, an inter-coded signal obtained by compressing the difference screen, an adaptive coding circuit (46) that selectively outputs the intra-coded signal obtained by compressing the divided screen, and an inter-code of the same divided screen. And a selection control circuit (48, 70, 136) for controlling the output of the adaptive encoding circuit by comparing the compression efficiency by the encoding with the compression efficiency by the intra encoding. 35. The code amount comparing circuit (48) according to claim 34, wherein the selection control circuit compares compression efficiency by comparing a code amount by the inter encoding and a code amount by the intra encoding. ). 36. The dispersion output comparing circuit (70, 136) according to claim 34, wherein the selection output circuit compares a dispersion value of the divided screen and a dispersion value of the difference screen to compare compression efficiency. A moving image compression apparatus characterized by the following. 37. The motion vector detection circuit according to claim 34, wherein the motion vector detection circuit cumulatively integrates absolute values of differences between upper bits of the digital video signal in the search range,
A moving image compression apparatus characterized by detecting a vector having the smallest cumulative total as a motion vector. 38. The motion vector detection circuit according to claim 34, wherein the motion vector detection circuit counts the number of matching high-order bits of the digital video signal in the search range, and the vector having the largest count value. Is a motion vector, and is detected. 39. The adaptive encoding circuit according to any one of claims 34 to 36, wherein the adaptive encoding circuit (46) sets the divided screen and the difference screen to DC.
A conversion circuit (62, 54, 62a, 116) to a value representing a spatial frequency component such as T conversion and wavelet conversion, and a quantization circuit (64, 56, 64) for quantizing the output of this conversion circuit.
a, 118), and a moving picture compression device. 40. The adaptive coding circuit (46) according to claim 39, further comprising an entropy coding circuit (66, 58, 66a) for performing entropy coding such as variable length coding on the output of the quantization circuit. , 120). 41. A moving image compression apparatus for detecting a motion vector of a split screen, obtaining a difference screen using this motion vector, and compressing the difference screen, when obtaining the motion vector, the absolute difference between the split screens is calculated. A motion vector detection circuit that detects a vector of a divided screen with a small variance value of the difference screen as a motion vector instead of using the vector with the smallest cumulative value as the motion vector (44
and a coding circuit (46) for obtaining a differential screen of a split screen using this motion vector, converting the differential screen into a spatial frequency and performing compression processing (46). . 42. The motion vector detection circuit (44a) according to claim 41, wherein the motion vector detecting circuit (44a) divides the first screen and binarizes the divided screen with an average value of images in the divided screen as a threshold value. 1 binarization circuit (1
6a), a second binarization circuit (16b) for binarizing the screen in the motion vector search range using the average value of the images in the motion vector search range of the second screen as a threshold, and the first, The output of the second binarization circuit (16a, 16b) is input, the number of coincidences of this binary data is counted, and the motion detection circuit (20) that outputs the vector with the largest number of coincidences as a motion vector, A moving image compression apparatus comprising. 43. The motion vector detection circuit (44a) according to claim 41, wherein the motion vector detection circuit (44a) divides the first screen and binarizes the divided screen with an average value of images in the divided screen as a threshold value. 1 binarization circuit (1
6a), a second binarization circuit (16c) for binarizing each divided screen using the average value of the image in each divided screen within the motion vector search range of the second screen as a threshold, The output of the first and second binarization circuits (16a, 16c) is input, the number of coincidences of the binary data is counted, and the motion detection circuit which outputs the vector of the split screen having the largest number of coincidences as the motion vector ( 20), and a moving picture compression device comprising: 44. A first position in the second screen corresponding to the position of the first area of the first screen, and a second position of the second area in the second screen having a pixel value similar to that of the first area. A circuit for detecting a motion vector indicating the difference between the first area and the pixel value of each area in the second screen, the circuit having a predetermined size in the first area. Threshold value selecting means (22) for selecting a pixel value in the order as a threshold value, and each pixel in the first region and each pixel in the second screen are binarized by using the threshold value and are used for the comparison. A motion vector detection circuit having a binarization circuit (22, 18) for outputting respectively. 45. The motion vector detection circuit according to claim 44, wherein the threshold value selecting unit selects a pixel value in a rank that is half the number of pixels in the first area as a threshold value. 46. A first position in the second screen corresponding to the position of the first area of the first screen, and a second position of the second area in the second screen having a pixel value similar to that of the first area. A circuit for detecting a motion vector indicating the difference between the first area and the pixel value of each area in the second screen, A first area binarization circuit (32, and 24) for binarizing based on the result of comparison of pixel values with adjacent pixels in one area and outputting for comparison; and each pixel in the second screen And a second screen binarization circuit (34) for binarizing based on the result of comparison of pixel values with adjacent pixels in the second screen and outputting for comparison. 47. The first area binarization circuit (32, and 24) according to claim 46, wherein each pixel in the first screen is set to a pixel value with an adjacent pixel in the first screen. The first screen binarization circuit (32) that binarizes based on the comparison result of 1. and the output of the first screen binarization circuit are input, and the first region is cut out from the first screen to correspond. A motion vector detection circuit including a block circuit (24) that outputs binary data of pixels. 48. A first position in the second screen corresponding to the position of the first area of the first screen, and a second position of the second area in the second screen having a pixel value similar to that of the first area. Is a circuit for detecting a motion vector indicating the difference between the pixel values of the first area and the pixel values of each area in the second screen, wherein each pixel in the first screen is binary. A first screen binarization circuit (32) to be digitized and an output of the first screen binarization circuit are input, the first region is cut out from the first screen, and binarized data of a corresponding pixel is output. A block circuit (24), a second screen binarization circuit (34) for binarizing each pixel in the second screen, and an output of the block circuit and the second screen binarization circuit. A motion vector detection circuit comprising: a comparison circuit (20) for inputting and performing the comparison. 49. A first position in the second screen corresponding to the position of the first area of the first screen, and a second position of the second area in the second screen having a pixel value similar to that of the first area. Is a circuit for detecting a motion vector indicating the difference between the pixel values of the first area and the pixel values of each area in the second screen, each circuit indicating each pixel value of the first area. A first deletion circuit (36) for deleting the lower bit of digital data and using for comparison.
And a second deletion circuit (38) for deleting the lower bit of each digital data indicating each pixel value of the second screen and using it for the comparison.
And a motion vector detection circuit having: 50. A first position in the second screen corresponding to the position of the first area of the first screen, and a second position of the second area in the second screen having a pixel value similar to that of the first area. Is a circuit for detecting a motion vector indicating the difference between the pixel values of the first area and the pixel values of each area in the second screen, each circuit indicating each pixel value of the first area. A first bit that deletes the lower bits of digital data and outputs to the second area selection circuit
A deletion circuit (36), and a second circuit for deleting the lower bit of each digital data indicating each pixel value of the second screen and outputting to the second region selection circuit
The deletion circuit (38) compares each pixel value of the first area after the lower bit deletion with the pixel value of each area sequentially cut out from the second screen after the lower bit deletion, and finds a matching pixel. A second area selection circuit (40) for selecting the area having the maximum number as the second area
And a motion vector detection circuit having: 51. A first position in the second screen corresponding to the position of the first area of the first screen, and a second position of the second area in the second screen having a pixel value similar to that of the first area. A circuit for detecting a motion vector indicating the difference between the pixel values of the first area and the pixel values of each area in the second screen, First reducing means (14, and 16) for cutting out data, reducing the data amount of each pixel data according to a criterion determined by the characteristics of the cut out first area, and providing the same for the comparison; A means (21) for extracting a search area for searching the motion vector from the second screen based on the first position corresponding to the area; and a data amount of each pixel data of the extracted search area as the reference. Second reducing means for reducing according to the above and providing for the comparison
(19), and a motion vector detection circuit having: 52. The binarization threshold according to claim 51, wherein the reference is a binarization threshold determined by the characteristics of the cut-out first region, and the first and second reduction means each pixel value based on the threshold. A motion vector detection circuit for binarizing. 53. A moving picture compression circuit for compressing an input moving picture signal by subjecting it to transform coding including DCT and quantization, wherein a reference screen in which gradation is reduced by extracting upper bits of each pixel data. And comparing the current area of which the gradation is reduced by extracting the upper bits of each pixel data, the area having the strongest correlation with the current area is searched from the reference screen as a reference area, and the current area A motion vector detection circuit (44) that detects a motion vector indicating the spatial position of the searched reference area from the spatial position, and a specification circuit (28) that specifies the reference area in the reference screen according to the output of the detection circuit. And a prediction for calculating the difference data between the pixel data of the compression target area (current area) and the pixel data of the reference area in the compression target screen (current screen) for use in the transform coding. Moving picture compression circuit having a Goka circuit (30), the. 54. The high-order bit extraction circuit in the detection circuit (44) according to claim 53, wherein the low-order bit of each digital data indicating each pixel value of the current area is deleted and the high-order 4 bits are left, A high-order bit extraction circuit in the detection circuit (44) deletes the low-order bit of each digital data indicating each pixel value of the reference screen and leaves the high-order 4 bits. 55. A moving picture compression circuit for compressing an input moving picture signal by transform coding including DCT and quantization, wherein the gradation is reduced by extracting upper bits of each pixel data. By comparing the frame and the current macroblock whose gradation has been reduced by extracting the upper bits of each pixel data, the macroblock having the strongest correlation with the current macroblock from the reference frame is set as the reference macroblock. A motion vector detection circuit that detects a motion vector indicating the spatial position of the searched reference macroblock in the reference frame from the spatial position of the current macroblock in the current frame (4
4), the pixel data of the reference area (the second area) specified in the reference screen (the second screen) according to the output of the detection circuit (44), and the pixel data in the compression target screen (the first screen). A predictive coding circuit (30) that calculates difference data from pixel data of a compression target area (the first area) and provides the data for the transform coding, and the transform coding to output data of the predictive coding circuit. The degree of compression when applied, the degree of compression when applying the conversion coding to the input moving image signal, for each of the compression target region, a determination circuit (48, 70) for determining the magnitude, And a switching circuit (68) for switching the conversion encoding processing for each of the compression target areas according to the determination result so that the compression degree of the conversion encoding becomes high. 56. The determination circuit (48) according to claim 55, wherein the code amount when the transform coding is applied to the output data of the predictive coding circuit (30) and the input moving image signal A moving image compression circuit that makes the determination by comparing with a code amount when transform coding is performed. 57. The determination circuit (70) according to claim 55, wherein the variance value of the pixel data in the compression target region (the first region) is compared with the variance value of the difference data. A moving image compression circuit that performs the determination. 58. The motion vector detection circuit (44) according to any one of claims 55 to 57, wherein a sum of absolute values of differences between respective pixel values output from the respective two upper bit extracting circuits is calculated. A moving image compression circuit that selects the smallest area as the reference area (the second area). 59. The motion vector detection circuit according to claim 55, wherein the motion vector detection circuit (44) has an area where the number of matching pixel values output from each of the two upper bit extracting circuits is maximum. Is selected as the reference area (the second area). 60. The motion vector detection circuit according to claim 57, wherein the motion vector detection circuit (44) has a minimum variance value of the differences between the pixel values output from the two upper bit extraction circuits. A moving image compression circuit, which selects an area to be the reference area (the second area). 61. A moving picture compression circuit for compressing an input moving picture signal by transform coding including DCT and quantization, wherein the compression target area has a threshold value which is an average value of pixel values of the compression target area. The binarized data of each pixel is compared with the binarized data of each pixel in the search area with the average value of the pixel values of the motion vector search area in the reference screen as a threshold value, and the maximum number of coincidence is obtained Selection circuit for selecting a region as a reference region (20)
And a predictive encoding circuit (30) for calculating difference data between the pixel data of the compression target area and the pixel data of the reference area for use in the transform encoding. 62. A moving picture compression circuit for compressing an input moving picture signal by transform coding including DCT and quantization, the compression target area having an average value of pixel values of the compression target area as a threshold value. The binarized data of each pixel is compared with the binarized data of each pixel of each divided area with the average value of the pixel values of each divided area in the motion vector search area of the reference screen as a threshold value. A selection circuit (20) for selecting a divided area having the maximum number of coincidences as a reference area, and calculating difference data between pixel data of the compression target area and pixel data of the reference area for the conversion encoding. A predictive encoding circuit (30) to be provided, and a moving image compression circuit having: 63. A first position in the second screen corresponding to the position of the first area of the first screen, and a second position of the second area in the second screen having a pixel value similar to that of the first area. Is a method of detecting the motion vector indicating the difference between the pixel values of the first region and the pixel values of the respective regions in the second screen, The lower bits of the digital data are deleted, the lower bits of the digital data indicating the pixel values of the second screen are deleted, the pixel data of the first area after the lower bits are deleted, and the lower bits after the lower bits are deleted. A motion vector detecting method, wherein the second region is selected from within the second screen by comparing each pixel data of each region within the second screen. 64. The pixel data of the first area after the lower bits are deleted and the pixel data of the areas in the second screen after the lower bits are deleted are compared with each other according to claim 63. A method of detecting a motion vector, wherein an area having the maximum number of matching pixels is selected as the second area. 65. A first position in the second screen corresponding to the position of the first area of the first screen, and a second position of the second area in the second screen having a pixel value similar to that of the first area. Is a method of detecting a motion vector indicating the difference between the pixel values of the first area and the pixel values of each area in the second screen, wherein the pixels of the first area from the first screen are detected. Data is cut out, each pixel data is binarized according to a binarization threshold determined by the characteristics of the cut out first region, and within the second screen based on the first position corresponding to the cut out first region. A motion vector detecting method for extracting the motion vector from which the motion vector is searched, binarizing the data amount of each pixel data of the extracted motion vector according to the binarization threshold value, and using the binarized data for the comparison.