JPH08298451A - Output buffer circuit - Google Patents

Abstract

PURPOSE: To obtain an output buffer circuit for high speed transfer with low noise in which an output signal is not fully swung. CONSTITUTION: A 1st switch 101 and a 2nd switch 102 are arranged in series between a couple of power supply terminals, and an external output buffer 100 is configured by a voltage divider circuit 120 in which a coupling point between the 1st switch 101 and the 2nd switch 102 is connected to an output terminal X of an output circuit 110 and an external terminal Z as a voltage dividing point Y, the output circuit 110 and the external terminal Z. A 2nd control signal ϕOUT used to turn on the 1st switch 101 and the 2nd switch 102 is fed to the voltage divider circuit 120 for a prescribed period just before a 1st control signal D allowing the output operation of the output circuit 110 is fed to allow the voltage division circuit 120 to set a potential of the voltage dividing point Y to a desired level before the output signal OUT is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly, it reduces the noise caused by an undesired rise of the ground potential or an undesired fall of the power supply potential due to the full swing of the output signal and the logical value of the output signal. The present invention relates to a technique related to improvement of determination speed.

[0002]

2. Description of the Related Art A conventional output buffer circuit is, for example, a CM.
In a push-pull circuit such as an OS inverter, an output operation is performed by supplying or extracting electric charge to or from an external output terminal. In this output buffer circuit,
Immediately after the high-level output operation that is formed by supplying electric charge to the output terminal, when performing the low-level output operation that is formed by extracting electric charge from the output terminal, the potential of the output signal changes from high level to low level. Full swing. Similarly, the output signal of this output buffer is fully swung from low level to high level. Such an output buffer circuit is described in the LSI Handbook (November 30, 1984).
(Published by Ohmsha, Inc.), pages 139 to 149
Page.

[0003]

The occurrence of the full swing of the output signal causes the following inconveniences. When the output signals of a plurality of bits are simultaneously fully swung from the high level to the low level, the ground potential of the chip that outputs the output signal is temporarily raised. Due to this temporary rise in the ground potential, noise is superimposed on the output signal and delays low-level signalization. Further, the rise of the ground potential also causes the logic threshold voltage of each circuit included in the chip to be temporarily raised, which causes malfunction. Similarly, when the output signals of a plurality of bits are simultaneously changed from the low level to the high level, the power supply potential is temporarily lowered, and the signalization of the high level is delayed. The drop in the operating potential also causes the logic threshold voltage of each circuit included in the chip to be temporarily lowered and causes a malfunction. Therefore, the present inventors have found the need for a technique for suppressing the full swing of the output signal.

An object of the present invention is to suppress the generation of power supply noise accompanying the output operation, speed up the output inversion operation, and further speed up the logical value determination speed at the output destination of the output signal.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, the first control signal is placed between the output circuit of which the output operation is allowed by the activation level and the output terminal of the output circuit and the external terminal,
It has a first switch and a second switch which are arranged in series between a pair of power supply terminals, and the connection point between the first switch and the second switch serves as a voltage dividing point to form an output terminal of the output circuit and an external terminal. And the first switch and the second switch are both controlled to be turned on by the second control signal for a predetermined period immediately before the output operation of the output circuit is permitted by the first control signal. And a voltage divider circuit to form an output buffer. A resistance element may be provided between the voltage dividing point and the pair of power supply terminals. In addition, a diode-connected pass transistor may be provided between the voltage dividing point and the pair of power supply terminals.

[0008]

According to the above means, the first switch and the second switch of the output buffer circuit are turned on by the second control signal before the output signal is supplied from the output circuit. When turned on, the current path including the first switch and the second switch has a predetermined resistance component including the ON resistance of the switch. Therefore, the potential at the voltage dividing point is the resistance component. The voltage is set to a predetermined potential that can be formed by a pair of power supply voltages. When the first control signal is supplied to the output circuit and the output signal is output to the voltage dividing point, the second control signal is turned off. At that time, the potential of the voltage dividing point holds the above-mentioned predetermined potential, and the potential of the output signal transits from that potential to the potential of a predetermined logical value. Therefore, even in the output operation of inverting the logic value with respect to the immediately preceding output, the output signal is not fully swung between the pair of power supply potentials. Through-current can be reduced by using the resistance element in addition to the first switch and the second switch. The resistance element added here is effective in preventing electrostatic breakdown between the first switch and the second switch. Further, when the pass transistor is used, it also works to suppress the amount of through current flowing between the power supply terminals.

[0009]

1 is a circuit diagram of an output buffer circuit 100 of the present invention.
An example circuit diagram is shown. The output buffer circuit 100
Is not particularly limited, but the memory chip 10 formed on a semiconductor substrate such as, for example, one single crystal silicon substrate.
include. In the figure, the structure of one bit of the output buffer is shown as a representative. According to the figure, the output buffer circuit 100 comprises an output circuit 110 and a voltage dividing circuit 120. The voltage dividing circuit 120 is an N-channel MO
CMO in which the drain of the SFET and the source of the P-channel MOSFET and the source of the N-channel MOSFET and the drain of the P-channel MOSFET are connected
A CMO having the same element configuration as the S transfer gate 101
S transfer gate 102 and power supply voltage VDD and GN
It is configured by connecting in series with D. The CMOS transfer gates 101 and 102 have the same resistance value because they have the same element structure. Therefore, when the CMOS transfer gates 101 and 102 are turned on, the series connection point Y is the operating power supply potential VD of the voltage dividing circuit 120.
It is kept at 1/2 of D. The potential of VDD / 2 is also the intermediate value level of the output signal level. An output from the output circuit 110 of the memory chip 10 is supplied to the connection point Y. The memory chip 10 is, for example, a static RAM, and internally, a decoder circuit and a drive circuit are sequentially operated in synchronization by various internal signals formed by delaying the address transition detection signal ATD, etc. Has been converted. The output circuit 110 is supplied with an output enable signal D (high enable signal) for enabling the output circuit 110 to be driven according to a data read cycle and the read data R. The output enable signal D is a signal formed by delaying the address change detection signal ATD. The output circuit 110 receives the output enable signal D and the data R as input, and an output stage of a CMOS inverter configured by connecting a P-channel MOSFET 201 and an N-channel MOSFET 202 in series between power supply terminals via a logic circuit. The data R is inverted and output. The output point of the output circuit 110 is MO
It is a connection point X between the SFET 201 and the MOSFET 202, and the output signal OUT is output from the external terminal Z via the connection point Y.

The output enable signal D and the inverted data R are supplied as two inputs to the negative logical product circuit 203, and the output of the negative logical product circuit 203 is connected so as to be supplied to the gate of the MOSFET 201, and the output The enable signal D and the data R are supplied as two inputs to the AND circuit 204, and the output of the AND circuit 204 is the MOSF.
Connected to feed the gate of ET202. According to this connection relationship, when the output enable signal D is at high level and the data R is at high level, the negative AND circuit 2
03 outputs a high level, and the output stage MOSFET 20
1 is turned off. At this time, the MOSFET
202 is turned on. Therefore, the potential of the connection point X is set to low level. Further, when the output enable signal D is at high level and the data R is at low level, the negative AND circuit 203 outputs low level and the output stage MOSF.
The ET 201 is turned on. Also, at this time, MO
The SFET 202 is turned off. Therefore, the connection point X
Is set to a high level. On the other hand, when the output enable signal D is low level, the MOSFETs 201 and 202 are turned off regardless of the potential of the data R.
In this way, the output circuit 110 is enabled only when the output enable signal D is at high level.

In order to form the intermediate value level, the CMOS transfer gates 101 and 1 of the voltage dividing circuit 120 are formed.
A control signal φOUT for turning on 02 and 02 is required. The control signal φOUT is a signal formed in the memory chip 10 in the same manner as the output enable signal D. That is, the control signal φOUT is a signal formed by delaying the address transition detection signal ATD. However, for the control signal φOUT, the output enable signal D is the output circuit 11
It is supplied to the voltage dividing circuit 120 as a high level before being supplied to 0, and is set to a low level when the output of the output circuit 110 is supplied to the voltage dividing circuit 120. This is because the connection point Y is connected to the data bus and the potential on the data bus is not undesirably changed when the output circuit 110 is not outputting data. Control signal φOUT
Are CMOS transfer gates 1 connected in series.
01 and 102 are commonly connected to the gates of N-channel MOSFETs, and the inverted signal of the control signal φOUT is CM.
The OS transfer gates 101 and 102 are commonly connected to the gates of P-channel MOSFETs. When the control signal φOUT is set to the high level, the CMOS transfer gates 101 and 102 are turned on, and the voltage dividing circuit 120 changes the potential of the connection point Y to VD by the resistance voltage dividing action.
Set to D / 2.

A control mechanism of the voltage dividing circuit 120 when the memory chip performs a read operation will be described below.
When the memory access address in the memory chip 10 changes, the address change detection signal ATD
The signal is output. The address transition detection signal ATD forms the output enable signal D and the control signal φOUT by passing through a delay circuit. As described above, the output enable signal D is formed so as to be delayed from the control signal φOUT. It is necessary to delay control so that the output enable signal D is supplied to the output circuit 110 after the control signal φOUT is supplied to the voltage dividing circuit 120. Further, the control signal φOUT is supplied to the voltage dividing circuit 12
It is kept at the high level until the output of the output circuit 110 corresponding to the data R read to 0 is supplied. As described above, before the output signal OUT corresponding to the read data R is output from the output circuit 110, the voltage dividing circuit 120 that receives the output signal OUT divides the potential of the connection point Y that receives the signal by the resistance voltage dividing action. Preset to an intermediate value level of the operating potential of the voltage circuit 120. Next, when the output enable signal D is supplied to the output circuit 110, the output signal OUT corresponding to the data R is output. At that time, the control signal φ
OUT is at low level. Therefore, when the data R is at the high level, the potential of the output signal OUT is changed from the intermediate value level to the low level, and when the data R is at the low level, the potential of the output signal OUT is changed from the intermediate value level to the high level. To be done. That is, the output signal OUT is a signal that is not fully swung in any case. Since the output signal OUT is not fully swung, neither the ground potential rises nor the power supply potential falls.
Therefore, it is possible to suppress undesired superposition of noise on the output signal OUT. Further, since the potential of the output signal OUT transits from the intermediate value level to the desired logical value level,
The determination of the logical value of the signal in the circuit to which the output signal OUT is sent requires only the time from the transition of the intermediate value level to the desired logical value level. This is shorter than the time required to determine the logical value of the output signal that is fully swung.

FIG. 2 shows a time chart of the adjusted output signal OUT when the output signal S is inverted to the high level when the read operation is performed in the memory chip 10. The time chart shown in (i) is the case where the voltage dividing circuit 120 of the present invention is not provided, and the time chart shown in (ii) is the case where the voltage dividing circuit 120 is provided. (I)
In this case, since the voltage dividing circuit 120 is not provided, the output signal OUT is fully swung from the output circuit 110 and output as it is. Therefore, it is understood that the output signal OUT is fully swung and noise is generated due to the rise of the ground potential. In the case of (ii), the output signal O
Before the UT is supplied to the voltage dividing circuit 120, the control signal φOUT formed by the address change detection signal ATD is supplied to the voltage dividing circuit 120 until the read signal is supplied from the output circuit 110. The potential of the connection point Y is set to the above intermediate potential. Therefore, even if the data R which is the inverted output signal OUT is supplied to the output circuit 110, the output signal OUT is not fully swung from the high level to the low level as in the case of (i), and the control signal φOUT is not generated. The transition from the intermediate potential formed in step 1 to low level. Therefore, the rise of the ground potential can be suppressed, and the noise superimposed on the output signal OUT is reduced.

Further, in the time chart of the data R and the output signal OUT in the same figure, an arrow Q indicating the position at which the output signal OUT transits to the potential at which the logical value is determined is added. Since the time charts of the data R are exactly the same, it is possible to compare the times when the logical value judgment potential is reached from the position of the starting point of the arrow Q. The position of the starting point of arrow Q is
It is shown that the output signal output from the output buffer circuit 100 including the voltage dividing circuit 120 reaches the logical value determination potential earlier. That is, the data R is the output circuit 1
The output buffer circuit 100 of the present invention in which the output signal is already at the intermediate value level of the output signal before being supplied to 10.
It can be seen that the output signal OUT of 1 shortens the time until the potential changes to the potential required to determine the logical value.

A circuit diagram of another voltage dividing circuit 300 of the present invention is shown in FIG. According to (A) of the figure, the voltage dividing circuit 300 includes a series connection point Y and C of the voltage dividing circuit 120.
A resistance element 30 is provided between the MOS transfer gate 101 and the MOS transfer gate 101.
1 has the same circuit configuration as the voltage dividing circuit 100 except that the resistor element 302 having the same resistance value as the resistor element 301 is provided between the serial connection point Y and the CMOS transfer gate 102. The resistive element 30 is added to the voltage dividing circuit 120.
By providing 1 and 302, the undesired potential supply to the CMOS transfer gates 101 and 102 is suppressed, and the CMOS transfer gates 101 and 102 are provided.
And can be prevented from being electrostatically destroyed. Further, the amount of through current between the power supply terminals can be suppressed.

FIG. 3B is a circuit diagram of another voltage dividing circuit 400 according to the present invention. According to (B) of the figure, the voltage dividing circuit 400 is diode-connected (the gate is connected to the source) between the power supply terminal VDD of the voltage dividing circuit 120 and the CMOS transfer gate 101.
A channel type MOSFET 401 is provided and a power supply terminal VS is provided.
It has the same circuit configuration as the buffer 120 except that a diode-connected N-channel MOSFET 402 is provided between the S and the CMOS transfer gate 102.
The MOSFET 401 and the MOSFET 402 can suppress the through current between the power supply terminals.

According to the above embodiment, the following operational effects can be obtained. (1) Before the data is supplied to the connection point Y between the CMOS transfer gates 101 and 102, the CMOS transfer gates 101 and 102 are turned on by the control signal φOUT formed using the address transition detection signal ATD, The potential of the connection point Y can be set to an intermediate value level of the output signal level. In this way, even if the data R for inverting the output potential output previously is supplied,
Since the full swing of the output signal OUT does not occur, the generation of noise due to the full swing can be suppressed. Further, the inversion time of the signal can be shortened as compared with the case of full swing, and the determination time of the logical value of the data transmitted as the output signal OUT can also be speeded up. (2) The resistance element 301 is provided between the connection point Y and the CMOS transfer gate 101, and the resistance element 302 is provided between the connection point Y and the CMOS transfer gate 102.
This makes it possible to prevent electrostatic damage to the transfer gates 101 and 102. (3) Power supply terminal VDD and CMOS transfer gate 1
01 is provided with MOSFET 401, and the power supply terminal VSS
Between the CMOS transfer gate 102 and the CMOS transfer gate 102
By providing T401, the amount of through current between the power supply terminals can be suppressed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the control signal φO
Although the element to which the UT is supplied is the CMOS transfer gate, it may be another switch circuit capable of setting the potential at the connection point Y to about the intermediate value level of the output signal level.

In the above description, the invention mainly made by the present inventor is described as an output buffer circuit of a memory chip which is a field of application which is the background of the invention, but is not particularly limited and is applied to various other semiconductor integrated circuits. It is possible. INDUSTRIAL APPLICABILITY The present invention can be applied as an output buffer circuit at least in an output section where an output signal is fully swung.

[0021]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the voltage dividing circuit is turned on by the second control signal for a predetermined period immediately before the output operation of the output circuit is permitted by the first control signal, and is connected to the output terminal of the output circuit. The potential at the voltage dividing point can be set to a predetermined potential. The potential of the voltage dividing point obtained here is a desired potential between the power supply terminals in which the voltage dividing circuit is formed, and is preferably an intermediate value potential between the power supply terminals. The output operation of the output circuit is permitted, and the output signal output from the output terminal transits based on the potential at the voltage dividing point. Therefore, the output signal can be a signal in which the transition of the potential which is not fully swung is small. This makes it possible to form an output signal with less noise, and also contributes to shortening the logical value determination time at the destination.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an example of an output buffer circuit of the present invention.

FIG. 2 is a time chart showing an output transition of an output signal.

FIG. 3 is a circuit diagram showing an example of another buffer circuit of the present invention.

[Explanation of symbols]

 100 output buffer circuit 110 output circuit 120 voltage dividing circuit 101, 102 MOSFET

Claims (3)

[Claims] 1. An output buffer circuit connected to an external terminal of a semiconductor integrated circuit, the output circuit being allowed to perform an output operation by setting a first control signal to an activation level, and the output circuit of the output circuit. A voltage dividing circuit arranged between the output terminal and the external terminal, wherein the voltage dividing circuit has a first switch and a second switch arranged in series between a pair of power supply terminals, The connection point of the first switch and the second switch is connected to the output terminal of the output circuit and the external terminal as a voltage dividing point, and the first switch and the second switch output the first control signal. An output buffer circuit characterized in that both are turned on by a second control signal for a predetermined period immediately before the output operation of the circuit is permitted. 2. The output buffer circuit according to claim 1, further comprising a resistance element between the voltage dividing point and the pair of power supply terminals. 3. The output buffer circuit according to claim 1, further comprising diode-connected pass transistors between the voltage dividing point and the pair of power supply terminals.