JPH08293821A - Non-contact communication system and data carrier - Google Patents

Abstract

PURPOSE: To extract a continuous clock from a carrier transmitted from a read/write head. CONSTITUTION: A reception part 51 and a waveform shaping circuit 52 shaping received output are provided for the data carrier. A clock lack detection part 54 detects the lack of the clock shaped by the waveform shaping circuit 52. A frequency-dividing circuit 53 frequency-divides the output of the waveform shaping circuit 52. When a clock lacking state is detected, the frequency-dividing circuit is alternately set and reset from H-time and L-time and the output is continued so as to output the continuous clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distribution system for managing tools and products, an identification system used for identifying a person at an entrance / exit gate, and a data carrier.

[0002]

2. Description of the Related Art Conventionally, a system for identifying and managing various articles such as tools, parts and products in order to mechanize the management of tools of machine tools and the identification of parts and products in an assembly and conveyance line in a factory. Is required. Therefore, JP-A-1-151831
As shown in the item No., a memory unit (data carrier) having a memory is provided in the identification object, and necessary information is written in such a memory by data transmission from the outside, and the information is stored as necessary. There has been proposed a non-contact communication device adapted to read out.

Such a conventional non-contact communication device is shown in FIG.
As shown in FIG. 3, it is composed of a write / read control unit including an ID controller 1 and a read / write head 2 and a data carrier 3. Then, the read / write head 2 intermittently oscillates at a constant frequency to change the duty ratio and transmits a signal to the data carrier 3 side. When data is received, a signal having a constant duty ratio is sent to the resonance circuit in the data carrier. Control the reverberation by. In the read / write head 2, the signal is received by determining the presence or absence of this reverberation by the resonance circuit.

In FIG. 8, the write / read control unit is I
It has a D controller 1 and a read / write head 2. The ID controller 1 has a transmission control circuit 11, a reference clock generation circuit 12, and a reception control circuit 13. The transmission control circuit 11 has first and second duty ratios corresponding to the transmission data signal when transmitting data from the read / write head 2 side to the data carrier 3, and a constant third duty ratio when receiving data, For example, it generates a transmission signal of a constant frequency which is intermittent with a duty ratio of 50%. The read / write head 2 is provided with an oscillation circuit 15 and a transmission coil L1 connected to the oscillation circuit 15 as shown in the figure. Coil L1 is data carrier 3
Is provided on the surface facing to. The oscillator circuit 15 is an oscillator circuit that oscillates at a constant frequency under the control of the transmission control circuit 11. Also, the receiving circuit has a coil L2 and a capacitor C1.
Is provided. This resonance circuit 16
The output of is demodulated by the demodulation circuit 17 and given to the reception control circuit 13. Also, the receiving coil L2 is also the coil L1.
Is provided on the surface facing the data carrier.

FIG. 9 is a block diagram showing the structure of a conventional data carrier 3. In the figure, the data carrier 3 has a resonance circuit 31. The resonance circuit 31 is the coil L3.
And a capacitor C2 connected in parallel with the coil L3. At both ends of the resonance circuit 31, a full-wave rectification circuit 32 for rectifying the alternating current excited at the output end, a voltage limiting circuit 33 for limiting the voltage, and a smoothing circuit 34 are connected. The voltage limiting circuit 33 limits the voltage level at both ends to a predetermined value or less, and for example, a Zener diode is used. The smoothing circuit 34 smoothes the rectified and voltage-limited voltage Vcc and supplies it to each part of the data carrier.

A DEM extraction circuit 35 is connected to one end of the resonance circuit 31. The DEM extraction circuit 35 converts the carrier of the transmission signal into a square wave by half-wave rectifying and shaping the carrier of the transmission signal with the frequency of the carrier as the passing frequency, and the output thereof is given to the demodulation circuit 36. Further, the integration comparator circuit 37 is connected to the resonance circuit 31 as described later. The integration comparator circuit 37 is the resonance circuit 31.
The envelope signal of the obtained signal is detected, the power source is discriminated by the divided threshold value, the clock signal CKA is extracted, and the output thereof is output to the demodulation circuit 36. When the data carrier receives a signal, the demodulation circuit 36 counts the number of carrier pulses extracted by the DEM extraction circuit 35 based on the clock signal CKA, and either the H level or the L level is selected depending on the duty ratio of intermittent transmission. Is to determine. The signal thus demodulated is separated into a command and data by the memory control unit 38,
Necessary data is written in 9 and data is read from the memory 39. The output of the integration comparator circuit 37 is also given to the falling pulse generation circuit 40. The falling pulse generation circuit 40 outputs the output CKA of the integration comparator circuit 37.
The short pulse is generated at each trailing edge of the pulse, and its output is given to the shunt pulse generation circuit 41. The NRZ signal read from the memory control unit 38 is converted into, for example, a serial bi-phase code by the conversion circuit 42 and input to the shunt pulse generation circuit 41. The shunt pulse generation circuit 41 generates a shunt pulse by the logical product of these, and is input to the shunt circuit 43. The shunt circuit 43 has a pair of switching elements that ground both ends of the resonance circuit 31 based on a shunt pulse, and grounds both ends of the resonance circuit at the same time to stop reverberation in a short time. Here, the blocks from the falling pulse generation circuit 40 to the shunt circuit 43 constitute reverberation control means for controlling reverberation.

The integrating comparator circuit 37 has diodes D1 and D2 whose anode ends are connected to both ends of the resonance circuit 31 and whose cathode ends are commonly connected, a capacitor C3 for smoothing its output, and a load resistor R1. And its voltage output is applied to one end of the comparator 44. The other end of the comparator 44 is connected to the power supply voltage Vcc with resistors R2 and R2.
The reference voltage divided by 3 is given. The comparator 44 shapes the waveform rectified based on this reference voltage and extracts the clock signal CKA.

Next, the waveform of each part of the read / write head and the data carrier will be described. FIG. 10 (a)-
(D) shows the waveform of each part of FIGS. 8 and 9 a to d. FIG. 10A is a switch signal of the read / write head 2, and FIG. 10B is a transmission waveform transmitted from the transmission unit, and a waveform having a duty ratio of 50% is output when data is received. When this signal is received by the data carrier 3, a resonant waveform with reverberation is obtained in its resonant circuit 31. This signal is integrated by the integrating circuit of the integrating comparator circuit 37. The comparator 44 discriminates this signal with a predetermined threshold value to convert it into a square wave as shown in FIG. Therefore, the pulse signal of the DEM extraction circuit 35 is identified by this signal.

[0009]

However, in the conventional data carrier, the carrier is not transmitted to the data carrier side due to the fall of the switch signal of the read / write head 2 as shown in FIGS. 10 (a) and 10 (b). For,
This carrier could not be shaped as it is to generate a clock signal. Further, when PSK modulation is used when data is transmitted from the read / write head to the data carrier side, even if the carrier is shaped and extracted as the clock of the data carrier, FIG.
Since the phase of the carrier changes and the clock is interrupted as shown in (4), there is a drawback that this cannot be used as it is as the clock of the data carrier.

In order to reproduce the same clock as the carrier signal, an oscillator is provided in the data carrier or P
It is conceivable to use the LL circuit. However, such a method increases the power consumption in the data carrier, so that it is necessary to attach a battery to the data carrier. Further, when the electric power obtained from the read / write head is rectified and used as a power source for the data carrier, there is a drawback that the communication distance is limited to a short distance due to an increase in power consumption. Then, when the low-speed clock CKA based on the envelope is extracted as shown in FIG. 10D based on the signal received by the data carrier, it is difficult to operate the microcomputer that requires the high-speed clock.
Further, there is a drawback that a stable clock cannot be obtained due to demodulation.

The present invention has been made in view of the above conventional problems, and it is a technical object of the present invention to make it possible to extract a continuous clock from a carrier transmitted from a read / write head.

[0012]

The invention of claim 1 of the present application is a contactless communication comprising a data carrier and a write / read control unit for transmitting data to the data carrier and receiving the transmitted data. In the system, the data carrier includes a receiving unit including a coil, a waveform shaping circuit that shapes the output of the receiving unit, a clock loss detection unit that detects a loss of a clock obtained from the waveform shaping circuit, and a waveform shaping circuit. In addition to outputting the waveform-shaped clock signal, the H level time and the L level time of the clock signal are respectively detected at the time of detecting the clock loss by the clock loss detection unit, and the clock output is inverted every time the detection is performed to continue. A clock recovery unit that outputs a clock signal, and recovers data based on the clock and modulated carrier signal obtained from the clock recovery unit. A data demodulation circuit for a memory and, is characterized in that it comprises a memory control unit for controlling the memory, the based on the signal obtained from the data demodulation circuit.

The invention of claim 2 of the present application is a non-contact communication system comprising a data carrier and a write / read control unit for transmitting data to the data carrier and receiving the transmitted data. The carrier includes a receiving unit including a coil, a waveform shaping circuit that shapes the output of the receiving unit, an edge detection unit that detects an edge of a clock obtained by the waveform shaping circuit, and an arbitrary clock cycle obtained by the waveform shaping circuit. Is obtained by the clock regeneration unit, which has a time constant of 1 for even number of times, inverts the output at the timing of the time constant, and corrects the clock output based on the detection signal obtained by the edge detection unit. A data demodulation circuit that demodulates data based on a clock and a modulated carrier signal, a memory, and a signal obtained from the data demodulation circuit It is characterized in that it comprises a memory controller for controlling the memory based.

The invention of claim 3 of the present application is a data carrier for receiving a carrier signal modulated by a transmission signal, the receiving section including a coil, a waveform shaping circuit for shaping the output of the receiving section, and a waveform shaping. A clock dropout detection unit for detecting a clock dropout obtained from the circuit and a clock signal whose waveform is shaped by a waveform shaping circuit are output, and when the clock dropout detection unit detects the clock dropout, the time of the H level of the clock signal and L A clock recovery unit that detects each level time and outputs a continuous clock signal by inverting the clock output at each detection, and demodulates data based on the clock and the modulated carrier signal obtained from the clock recovery unit. A data demodulation circuit, a memory, and a memory control unit that controls the memory based on a signal obtained from the data demodulation circuit, It is characterized in that it comprises.

The invention of claim 4 of the present application is a data carrier for receiving a carrier signal modulated by a transmission signal, the receiving section including a coil, a waveform shaping circuit for shaping the output of the receiving section, and a waveform shaping. An edge detection unit for detecting the edge of the clock obtained from the circuit, and a time constant of 1 for any even number of the cycle of the clock obtained from the waveform shaping circuit,
A clock recovery unit that inverts the output at the timing of the time constant and corrects the clock output based on the detection signal obtained from the edge detection unit, and data based on the clock and the modulated carrier signal obtained from the clock reproduction unit. A data demodulation circuit that demodulates the memory, a memory, and a memory control unit that controls the memory based on a signal obtained from the data demodulation circuit.

[0016]

The functions of claims 1 and 3 of the present application having such characteristics
According to the invention, the data carrier shapes the carrier signal received by the receiving unit, and the missing clock is detected by the missing clock detecting unit. The waveform shaping circuit outputs the clock signal whose waveform has been shaped, detects the time of the H level and the L level of the clock signal at the time of detection of the loss by the loss detection unit, and inverts the clock at each detection to eliminate the clock loss. The continuous clock signal can be reproduced even at certain times. Further, according to the inventions of claims 2 and 4 of the present application, there is provided a clock generation section for reversing the clock at a timing of an even fraction of the period of the carrier signal obtained from the write / read control unit to reproduce a continuous clock. ing. An edge is detected from the signal shaped by the waveform shaping circuit for the clock by the clock regenerator, and the timing is corrected to extract the clock signal having a substantially constant cycle without a long time shift.

[0017]

1 is a block diagram showing the configuration of a clock extraction unit of a data carrier according to an embodiment of the present invention. In this figure, the same parts as those in the conventional example described above are designated by the same reference numerals. In the present embodiment, the coil L3 and the receiving section 50 including a resonance circuit are provided, and the receiving section 50 includes a multiplication circuit 51.
Is connected. The multiplication circuit 51 is composed of, for example, a full-wave rectification circuit, which doubles the carrier frequency f (Hz), and its output is input to the waveform shaping circuit 52. The waveform shaping circuit 52 discriminates and shapes the multiplied output by a predetermined threshold value, and the output is given to the frequency dividing circuit 53 and the clock dropout detection unit 54. The clock dropout detection unit 54 detects a 2fHz clock dropout, and the detection signals are L time detection unit 55 and H time detection unit 56.
Given to. L time detection unit 55 and H time detection unit 56
Respectively monitors the L time and the H time based on the output of the frequency dividing circuit 53, and outputs a set or reset signal to the frequency dividing circuit 53 if a predetermined time is exceeded. The frequency divider circuit 53 divides an input signal and operates by a set or reset input to extract a continuous clock signal having the same frequency f as the carrier frequency, and its output is input to the data demodulation circuit 57. It The configuration after the data demodulation circuit 57 is similar to that of the conventional data carrier described above, and thus detailed description thereof is omitted.

FIG. 2 is a circuit diagram showing the configuration of the main part of this embodiment. In the figure, the output of the waveform shaping circuit 52 is input to the clock loss detection unit 54 and the frequency dividing circuit 53 including a D-type flip-flop. The clock loss detection unit 54 is 2
If the same signal is continuously output for a period corresponding to a half of the f frequency, it is determined that the clock is missing, and as shown in the figure, the integrating circuit 54a made of CR and the cascade for shaping the output thereof are used. Connected inverters 54b, 54
It is configured to include c and 54d. Also, L time detection unit 5
Reference numeral 5 has a CR integrating circuit 55a connected to the Q-bar output terminal of the D-type flip-flop, and inverters 55b and 55c for shaping the output thereof, the output of which is input to the NAND circuit 55d. The NAND circuit 55d outputs a set signal to the D-type flip-flop by performing a logical product with the output of the clock dropout detection unit 54. Further, the H time detection unit 56 has a CR type integration circuit 56a connected to the Q output terminal of the D type flip-flop, and inverters 56b and 56c for shaping the output thereof, the output of which is input to the NAND circuit 56d. To be done. The NAND circuit 56d outputs a reset signal to the D-type flip-flop 53 by performing a logical product with the output of the clock dropout detection unit 54.

Next, the operation of this embodiment will be described with reference to a time chart. FIG. 3A shows an intermittent carrier signal transmitted from the read / write head, and this signal is received by the receiving unit 50 including the resonance circuit of the data carrier. Then, the multiplier circuit 51 performs full-wave rectification as shown in FIG. 3B, and waveform shaping is performed with a predetermined threshold value to obtain the clock input shown in FIG. 3C. This clock input changes the frequency of the received signal to f
Then, the frequency becomes twice the frequency 2f. Since this signal is input to the frequency dividing circuit 53 and the clock loss detection unit 54, the integration circuit 54a of the clock loss detection unit 54
When the time Td is exceeded, the output is inverted, and the output shown in FIG. 3D is obtained by the clock loss detector 54, that is, the H level output is obtained in the state where the clock loss is detected. This signal is applied to the L time detection unit 55 and the H time detection unit 56, and these circuits operate. Now, when the Q bar output exceeds the time Ts and the H state continues, the L time detection unit 55 outputs the H level output because the output of the integrating circuit 55a reaches the threshold value, and the H level output is obtained. Circuit 55d. Therefore, from the NAND circuit, FIG.
The output shown in FIG. 3 is added, and the frequency dividing circuit 53 composed of a D-type flip-flop is inverted as shown in FIGS. Then, from this time, the integration circuit 5 of the H time detection unit 56
6a starts operating. When the predetermined time Tr is exceeded, the inverters 56b and 56c are inverted and the NAND circuit 5
The output shown in FIG. 3 (f) is applied to the reset terminal via 6d. Therefore, the flip-flop of the frequency dividing circuit 53 is shown in FIG.
Invert as shown in (g) and (h). Even when the clock is missing in this way, the clock is continuously output as it is and added to the data demodulation circuit 57. Here, the time constant Td of the integration circuit of the dropout detection unit 54 is set to be slightly longer than 1 / 4f when the frequency of the signal applied from the read / write head is f. Also, the time constants Ts and Tr of the integrating circuits 55a and 56a are substantially equal to 1 / 2f of the carrier frequency, and are set to a time slightly longer than this. In this way, a continuous clock can be obtained. In this embodiment, the frequency dividing circuit 5
3, the L time detection unit 55, and the H time detection unit 56 output the waveform-shaped clock signal, and detect the L level and H level times of the clock signal when the clock loss detection unit detects the clock loss. A clock recovery unit that inverts the clock signal for each detection and outputs a continuous clock signal is configured.

FIG. 4 is a block diagram showing the structure of a clock extraction unit of a data carrier according to the second embodiment of the present invention. In this embodiment, a clock nfHz higher than the input fHz carrier signal is output. In the present embodiment, as shown in the figure, the frequency input circuit 6 on the output side of the waveform shaping circuit 52 and the edge input detection unit 6 for detecting the rising edge.
2 is provided. An L time detecting section 63 and an H time detecting section 64 are provided on the output side of the frequency dividing circuit 61 as in the first embodiment. Frequency divider circuit 61, L time detection unit 63, H time detection unit 6
Reference numeral 4 has a time constant of an arbitrary even number of the cycle of the clock obtained from the waveform shaping circuit, inverts the output at the timing of the time constant, and outputs based on the detection signal obtained from the H detection unit 64. It constitutes a clock reproducing unit for correcting the clock.

FIG. 5 is a circuit diagram showing a concrete circuit example of the edge input detector 62 to the H time detector. In the figure, the input clock is input to the clock input terminal of the D-type flip-flop that constitutes the frequency dividing circuit 61, and is further connected to the inverter 62 a of the edge input detection unit 62. The output side of the inverter 62a is connected to an integrating circuit 62b having a time constant sufficiently longer than the time constant of the input clock and an inverter 62c for shaping the output, and the outputs thereof are the L time detecting unit 63 and the H time detecting unit 64. Connected to the NAND circuit. The L time detection unit 63 has an integration circuit 63a and an inverter 63b which receive the Q-bar output of the D-type flip-flop, and the output thereof is input to the NAND circuit 63c. The H time detection unit 64 also has an integration circuit 64a to which the Q output is input, an inverter 64b, and a NAND circuit 64c. The output of the edge input detection unit 62 is input to the other inputs of these NAND circuits 63c and 64c. Given. The outputs of the NAND circuits 63c and 64c are connected to the set and reset terminals of the D-type flip-flop 61, respectively.

Next, the operation of this embodiment will be described. FIG. 6 is a time chart showing the operation of this embodiment.
(A)-(h) has shown the waveform of ah of FIG. 4, FIG. FIG. 6A shows the received signal received by the data carrier, and the waveform shown in FIG. 6B is obtained by shaping the waveform of the received signal by the waveform shaping circuit 52. By inputting this signal to the inverter 62a of the edge input detection unit 62, the output shown in FIG. 6 (c) is obtained. By integrating this and shaping the waveform with a predetermined threshold value, the edge input detection unit 62 displays The output shown in 6 (e) is obtained. The integrating circuits 63a and 64a of the L time detecting unit 63 and the H time detecting unit 64 of the present embodiment are assumed to have a time constant of an arbitrary even fraction of the input carrier period, for example, a quarter period. To do. Then, if the Q-bar output exceeds this time, D is output via the inverter 63b and the NAND circuit 63c.
Type flip-flop is set and its output is inverted. When a predetermined time has elapsed after the output is inverted, the Q output causes the inverter 64b of the H time detecting section to operate, and the output is added to the reset terminal to reset the flip-flop. Therefore, continuous clock signals are output as shown in FIG. And FIG. 6 (e)
As shown in, the gate circuit is prohibited at the falling edge of the input clock, and the set and reset inputs are prohibited. If the input clock is inverted at this time, the input of the D-type flip-flop is also inverted, and the shift is corrected in synchronization with the input clock. By using the input clock for correcting the continuous clock in this way, a clock having a frequency higher than the frequency f of the input clock signal can be obtained in the data carrier.

FIG. 7 is a circuit diagram showing a clock extraction unit of the data carrier according to the third embodiment. As shown in the figure, the output of the waveform shaping circuit 52 is input to the edge input detection unit 71. The edge input detection unit 71 generates an edge of an input signal and resets the entire circuit. In this embodiment, an RS flip-flop is provided as the frequency dividing circuit 72, and the output of the edge input detecting unit 71 is the L time detecting unit 73,
It is input to the H time detection unit 74. These detectors are CR
Type integrating circuit and an inverter, the outputs of which are applied to the set and reset input terminals, respectively. The edge input detection unit 71 resets the entire circuit by short-circuiting these capacitors via an analog switch. The time constants of the integrating circuits of the L time detecting unit 73 and the H time detecting unit 74 are set to an arbitrary even number 1 of the cycle corresponding to the frequency of the carrier signal input as in the second embodiment. This makes it possible to output a continuous clock of a higher frequency, as in the second embodiment.

Although the above-described first to third embodiments describe the data carrier for receiving the ASK-modulated signal in which the carrier is interrupted at a predetermined timing, the present invention describes PSK for changing the phase of the carrier. The present invention can also be applied to the FSK modulation method that modulates or changes its frequency. In the case of the FSK modulation method, the carrier frequency changes, but if the resonant circuit is made to resonate at one of the frequencies, the output obtained from the resonant circuit will be almost the same as ASK. It becomes possible to detect similarly in the embodiment.

[0025]

As described in detail above, according to the present invention, it is possible to reproduce the same clock signal as the carrier signal input from the write / read control unit in the data carrier of the non-contact communication device. Further, claims 2 and 4 of the present application
According to the invention, the clock signal having a frequency higher than that of the carrier signal can be reproduced, and a microcomputer or the like can be used in the data carrier.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a data carrier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a data demodulation unit of this embodiment.

FIG. 3 is a time chart showing the operation of this embodiment.

FIG. 4 is a block diagram showing a main part of a data carrier according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a data demodulation unit and its peripheral circuits according to a second embodiment.

FIG. 6 is a time chart showing the operation of this embodiment.

FIG. 7 is a circuit diagram showing a data demodulation unit and its peripheral circuits according to a third embodiment.

FIG. 8 is a block diagram showing an overall configuration of a conventional non-contact communication device.

FIG. 9 is a block diagram showing an example of a conventional data carrier.

FIG. 10 is a waveform diagram showing a waveform of each part of a conventional non-contact communication device.

[Explanation of symbols]

 1 ID Controller 2 Read / Write Head 3, 30 Data Carrier 11 Transmission Control Circuit 31 Resonance Circuit 36, 53, 55 Demodulation Circuit 37 Integral Comparator Circuit 38 Memory Control Section 39 Memory 41 Shunt Pulse Generation Circuit 42 Conversion Circuit 43 Shunt Circuit 44 Comparator 50 receiver 51 multiplier circuit 52 waveform shaping circuit 53, 61 frequency divider circuit 54 clock loss detector 55, 63, 73 L time detector 56, 64, 74 H time detector 57 data demodulator 62, 71 edge input detector 72 RSFF

Claims (4)

[Claims] 1. A contactless communication system comprising: a data carrier; and a write / read control unit for transmitting data to the data carrier and receiving the transmitted data, wherein the data carrier comprises a coil. A receiving unit including the waveform shaping circuit that shapes the output of the receiving unit; a clock loss detection unit that detects a loss of a clock obtained from the waveform shaping circuit; and a clock signal that is waveform shaped by the waveform shaping circuit. At the same time, when the clock dropout detection unit detects the clock dropout, the time of the H level of the clock signal and L
A clock regenerator that detects each level time and inverts the clock output at each detection to output a continuous clock signal, and demodulates data based on the clock and the modulated carrier signal obtained from the clock regenerator. A non-contact communication system, comprising: a data demodulation circuit for controlling the memory; a memory; and a memory control unit that controls the memory based on a signal obtained from the data demodulation circuit. 2. A non-contact communication system comprising a data carrier and a write / read control unit for transmitting data to the data carrier and receiving the transmitted data, wherein the data carrier comprises a coil. A receiving unit including; a waveform shaping circuit that shapes the output of the receiving unit; an edge detection unit that detects an edge of a clock obtained by the waveform shaping circuit; and an even number of clock cycles obtained by the waveform shaping circuit. A clock recovery unit that has a time constant of 1 minute, inverts the output at the timing of the time constant, and corrects the clock output based on the detection signal obtained from the edge detection unit; A data demodulation circuit for demodulating data based on a clock and a modulated carrier signal; a memory; and the data demodulation circuit Non-contact communication system, characterized in that on the basis of the obtained signal includes a memory controller for controlling the memory. 3. A data carrier for receiving a carrier signal modulated by a transmission signal, the receiving unit including a coil, a waveform shaping circuit for shaping the output of the receiving unit, and a clock obtained from the waveform shaping circuit. A clock loss detection unit for detecting a clock loss, a clock signal whose waveform has been shaped by the waveform shaping circuit, and an H level time and L of the clock signal when the clock loss detection unit detects a clock loss.
A clock regenerator that detects each level time and inverts the clock output at each detection to output a continuous clock signal, and demodulates data based on the clock and the modulated carrier signal obtained from the clock regenerator. A data carrier, comprising: a data demodulating circuit for controlling the memory; and a memory, and a memory control unit that controls the memory based on a signal obtained from the data demodulating circuit. 4. A data carrier for receiving a carrier signal modulated by a transmission signal, the receiving unit including a coil, a waveform shaping circuit for shaping the output of the receiving unit, and a clock obtained from the waveform shaping circuit. An edge detection unit that detects an edge of the waveform shaping circuit, and a time constant that is an even number 1 of the period of the clock obtained from the waveform shaping circuit. The output is inverted at the timing of the time constant and the edge detection unit obtains the time constant. A clock recovery unit that corrects a clock output based on the detected signal, a data demodulation circuit that demodulates data based on the clock and the modulated carrier signal obtained from the clock recovery unit, a memory, and the data demodulation circuit And a memory control unit that controls the memory based on a signal obtained from the data carrier. .