JPH08293737A - Signal output circuit - Google Patents

Abstract

PURPOSE: To reduce power source noises without increasing the components of the signal output circuit by impressing a control signal to gradually increase the voltage level to the gate of an insulated gate transistor. CONSTITUTION: The waveform of a control signal DIS for a discharge transistor is not a rectangular wave as a conventional one but is a saw-tooth-wave to gradually linearly increase its level. When the level of this control signal DIS exceeds the Vth of the discharge transistor, the discharge transistor is gradually discharged till the gate voltage of the discharge transistor finally becomes VDD and all the electric charges are discharged. Thus, the transistor for discharge is not rapidly changed from OFF to ON but gradually changes to the complete ON so that the discharge current can not be rapidly increased and the power source noises can be reduced. Besides, since the number of transistors for discharge to be simultaneously turned on is decreased, the power source noises can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal output circuit for outputting a drive signal to a capacitive load such as a liquid crystal element, and circuit means for supplying a voltage of a level according to an input signal to the capacitive load. The present invention relates to a signal output circuit having an insulated gate transistor for discharging the electric charge charged in the capacitive load.

[0002]

2. Description of the Related Art FIG. 2 shows the configuration of a conventional signal output circuit. This circuit outputs a voltage of a predetermined level according to the input signal VIN to the capacitive load LC.
Is output to Source follower transistor (P
A channel MOSFET) P1 and a bias transistor (N-channel MOSFET) N1 are connected in series to form an output buffer section. Source follower transistor P
The input signal VIN is applied to the gate of No. 1 and a predetermined bias voltage Vb is applied to the gate of the bias transistor N1. N2 is a discharge transistor (N-channel MOSFET), which is connected to the output terminal OT of the buffer. This transistor is for discharging the electric charge charged in the capacitive load LC, and the discharge pulse signal DIS is applied to its gate. The waveforms of the bias voltage Vb and the pulse signal DIS for discharging are shown in FIG.

Therefore, when the input signal VIN is applied to the gate of the source follower transistor P1 and a constant bias voltage Vb is applied to the gate of the bias transistor N1, an output voltage corresponding to the input signal VIN is applied to the load LC. Is output to. In addition, the discharge pulse signal DIS is set to VDD in response to the periodic change of the input signal.
When the discharge transistor N2 is set to the level and the discharge transistor N2 is turned on for a certain period of time, the charge charged in the capacitive load LC is discharged through the discharge transistor N2, and when the discharge of the charge in the capacitive load is completed,
The control signal DIS of the discharge transistor N2 is set to G
By setting the ND level, the transistor is turned off, and then the operation corresponding to the input signal is performed.

The signal output circuit is used, for example, as an output buffer circuit of a liquid crystal display driving device. A configuration diagram in that case is shown in FIG.

As shown in the figure, the liquid crystal display drive device includes a plurality of output circuits OC1 (not shown), ..., OCn, O.
C _{n + 1} , ... are arranged in parallel,
The signal output circuit OC is provided at the final stage of each output circuit. IL is an input line for an analog video signal. AS
1 and AS2 are analog switches, respectively.
Opening / closing is controlled by the control signals S1 and S2. That is, when the analog switch control signals S1 and S2 are at the H level, the corresponding analog switches AS1 and AS, respectively.
2 is turned on and the analog switch control signals S1 and S2 are L
At the time of level, the corresponding analog switch AS
1, AS2 are turned off. C1 and C2 are storage capacitors, which are connected to the outputs of the analog switches AS1 and AS2, respectively. N3 is a discharge transistor, which is turned on when the control signal DIS is H and discharges the electric charge of the capacitor C2. OP is an operational amplifier circuit, and BF is a buffer circuit.

The operation of the circuit of FIG. 4 will be described below with reference to the timing chart of FIG.

In FIG. 5, B is an input analog video signal. When the analog switch control signal S1 is H, the analog video signal is input to the storage capacitor C1 via the analog switch AS1. When the analog switch control signal S1 becomes L, the analog switch AS1 is turned off. The signal level DA1 immediately before the analog control signal S1 becomes L is stored in the storage capacitor C1. When the analog switch control signal S2 is H, the signal of DA1 accumulated in the capacitor C1 is guided to the operational amplifier circuit OP after passing through the analog switch AS2, passes through the buffer circuit BF, and passes through the signal output circuit O.
Input to C. When the analog switch control signal S2 becomes L, the analog switch AS2 turns off and the storage capacitor C
The signal stored in 2 is input to the operational amplifier circuit OP. Before the analog switch control signal S2 becomes H, D
The IS signal becomes H, and the charge in the storage capacitor C2 is discharged. That is, after discharging the capacitor C2 by the DIS signal,
The input signal level is stored in the capacitor C2 via the analog switch AS2.

The analog switches AS1 and A shown in FIG.
The configuration of S2 is shown in FIGS. FIG. 6 is a circuit configuration diagram,
FIG. 7 is a sectional structural view.

In the prior art shown in FIG. 4, DIS
When the signal changes from L to H, the charge stored in the capacitor C2 and the liquid crystal load is discharged, and the output is grounded to GND. The discharge current at this time is, for example,
The liquid crystal display device increases in size as the screen becomes larger, and abrupt discharge may occur, causing a large amount of noise on the power supply. The noise on the power supply may greatly exceed the signal level VS accumulated in the capacitor C1, for example. For example, in the case where the circuit shown in FIG. 4 is configured on the N ⁻ substrate, if the noise on the power supply exceeds the signal level VS of the capacitor C1 by a large amount, the parasitic of the N-channel MOSFET portion that configures the analog switch AS1 will occur. A forward bias voltage is applied to the diode portion (shown in FIG. 7), and a current flows into the capacitor C1. As a result, the signal level of the capacitor C1 floats, and the signal level input via the input line IL may not be correctly transmitted to the subsequent stage (see FIG. 8). As a solution to the above problem, Japanese Patent Laid-Open No. 6-1046
In 54, a configuration is proposed in which a parallel connection circuit of a resistor and a capacitor is inserted between the discharge transistor and GND. However, such a configuration has another problem that the number of circuit elements increases and the circuit area increases.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a structure for reducing power source noise without increasing the number of constituent elements of a signal output circuit.

[0011]

A signal output circuit according to the present invention is a signal output circuit for outputting a drive signal to a capacitive load, and a circuit for supplying a voltage of a level according to an input signal to the capacitive load. Means and an insulated gate type transistor for discharging the electric charge charged in the capacitive load, wherein the control signal whose voltage level is gradually increased is the insulated gate type transistor. It is characterized in that means for applying to the gate of is provided.

The control signal is a sawtooth wave control signal whose voltage level increases linearly.

Further, the control signal is characterized in that it is a step-like control signal whose voltage level increases stepwise.

The signal output circuit device of the present invention is a signal output circuit for outputting a drive signal to a capacitive load, and circuit means for supplying a voltage of a level according to an input signal to the capacitive load. In a signal output circuit device comprising a plurality of signal output circuits having an insulated gate type transistor for discharging the charges charged in the capacitive load, the plurality of signal output circuits are provided. It is characterized in that it is divided into a plurality of groups, and means for applying a control signal of a predetermined level to the gate of the insulated gate type transistor is provided at different timings for each group.

Further, the control signal is a control signal whose voltage level gradually increases.

[0016]

According to the present invention, the discharge transistor does not suddenly shift from the off state to the complete on state but gradually transitions to the complete on state. It is possible to reduce noise.

Further, according to the present invention, since the number of discharge transistors that are turned on at the same time is reduced, the power supply noise can be reduced without the discharge current rapidly increasing.

[0018]

EXAMPLES The present invention will be described in detail below based on examples.

FIG. 1 is a diagram showing a waveform of a control signal DIS applied to a discharge transistor and waveforms of a discharge current and a power supply noise in an embodiment of the present invention. The configuration of the signal output circuit is the same as the conventional one (FIG. 2).

That is, the signal output circuit of this embodiment outputs a voltage of a predetermined level to a capacitive load such as a liquid crystal display element according to the input signal VIN. A source follower transistor (P-channel MOSFET) P1 and a bias transistor (N-channel MOSFET) N1 are connected in series to form an output buffer section. The input signal VIN is applied to the gate of the source follower transistor P1, and the predetermined bias voltage Vb is applied to the gate of the bias transistor N1. Further, it has a discharge transistor N2 composed of an N-channel MOSFET, and one end of the transistor is connected to the output terminal OT of the buffer. This transistor is for discharging the electric charge charged in the capacitive load LC, and its gate has a pulse signal D for discharging.
IS is being applied. The waveform of the bias voltage Vb is the same as that in FIG.

When the input signal VIN is applied to the gate of the source follower transistor P1 and a constant bias voltage Vb is applied to the gate of the bias transistor N1, an output voltage corresponding to the input signal VIN is applied to the capacitive load LC.
Is output to Further, in response to the periodical change of the input signal, the discharge pulse signal DIS is applied to the gate of the discharge transistor N2 and the discharge transistor N2 is turned on, so that the charge charged in the capacitive load LC is discharged. When the discharge of the capacitive load LC is completed through the discharge of the transistor N2 and the discharge transistor N is discharged again.
By setting the control signal DIS of 2 to the GND level,
The transistor is turned off, and then the operation corresponding to the input signal is performed.

The feature of this embodiment lies in the waveform of the control signal DIS of the discharge transistor N2. That is, the waveform of the control signal DIS is not a rectangular wave as in the prior art, but a sawtooth waveform whose level gradually and linearly rises. As shown in FIG. 1, when the level of the DIS signal exceeds Vth of the discharge transistor, the discharge transistor gradually discharges, and finally the gate voltage of the discharge transistor becomes V _DD , and the entire charge is discharged. With such a configuration, the discharge current can be prevented from rapidly increasing, the level of power supply noise can be reduced, and the power supply noise can be made extremely small.

In the above embodiment, the sawtooth-shaped D
Although the configuration uses the IS signal, as another configuration,
The stepped signal whose level increases stepwise is DIS
The same effect can be obtained even when used as a signal.

FIG. 9 shows the waveform of the control signal DIS applied to the discharging transistor and the waveforms of the discharge current and the power supply noise in that case. The configuration of the signal output circuit is the same as the conventional one (FIG. 2).

By gradually increasing the gate voltage of the discharge transistor in a stepwise manner (VGS1, VGS2, ...), the charge charge of the load capacitance is gradually discharged, and finally the total charge as VDD is obtained. By discharging, the noise on the power supply is reduced. Such a step-like voltage generating circuit may be configured using, for example, an intermediate voltage (VGS1 or the like) generating circuit by resistance division or the like and a circuit that sequentially switches and outputs the intermediate voltage using a timer circuit or the like. it can.

Next, a third embodiment will be described.

In both of the above-mentioned two embodiments, the control signal of the discharge transistor is devised. However, the embodiments described below are related to a signal output circuit device having a plurality of signal output circuits. The signal output circuit is divided into a plurality of groups (blocks), and a control signal is applied at different timings for each group to reduce power supply noise.

For example, 120 output circuits OC1, ...
.. In the liquid crystal display driving device having OC120, a configuration diagram of an embodiment in which discharge transistor control signals DIS1 and DIS2 are divided into two groups of odd-numbered and even-numbered and different timings are illustrated. 10 shows a timing chart, and FIG. 11 shows a timing chart. FIG. 11 shows the waveforms of the DIS1 signal and the DIS2 signal, and the waveforms of the discharge current and the power supply noise. As shown in FIG. 10, DI is assigned to even-numbered blocks.
The S1 signal is applied and the DIS2 signal is applied to the odd-numbered blocks. Each output circuit OC1, ..., O
The circuit configuration of C120 is the same as that of FIG.

In this way, by driving to 1/2, the charge discharged from the load capacitance is dispersed to 1/2, and the value of each discharge current becomes small, so that the power supply noise can also be halved. Is possible.

FIG. 12 shows the first half blocks (OC1, ...
., OC60) and the second half block (OC61, ..., O)
It is a block diagram at the time of dividing into C120). The other configurations are the same as those in the above embodiment except for the way of division.

Although the above embodiment is divided into two, it is needless to say that it may be divided into three or more. Also, each DI
The S signal may partially overlap at its falling and rising portions. Further, if each DIS signal is a sawtooth wave signal or step signal as shown in FIG. 1 or FIG. 9, the power supply noise can be further reduced.

[0032]

As described above in detail, according to the present invention, it is possible to prevent the discharge current from rapidly increasing and to reduce the power supply noise. As a result, it is possible to prevent the malfunction of the circuit or the fluctuation of the signal level due to the power supply noise.

[Brief description of drawings]

FIG. 1 is a timing chart used for explaining a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a signal output circuit.

FIG. 3 is a timing chart used for explaining a conventional technique.

FIG. 4 is a configuration diagram of a liquid crystal display driving device.

5 is a timing chart provided for explaining the operation of the circuit of FIG.

FIG. 6 is a circuit configuration diagram of an analog switch.

FIG. 7 is a sectional structural view of the same.

FIG. 8 is a timing chart for explaining the problems of the conventional technique.

FIG. 9 is a timing chart provided for explaining a second embodiment of the present invention.

FIG. 10 is a configuration diagram of a third embodiment of the present invention.

FIG. 11 is a timing chart for explaining the embodiment.

FIG. 12 is a configuration diagram of a fourth embodiment of the present invention.

[Explanation of symbols] P1 source follower transistor N1 bias transistor N2 discharge transistor

Claims (5)

[Claims] 1. A signal output circuit for outputting a drive signal to a capacitive load, the circuit means supplying a voltage of a level according to an input signal to the capacitive load, and an electric charge charged in the capacitive load. And a means for applying a control signal whose voltage level gradually rises to the gate of the insulated gate transistor in a signal output circuit having an insulated gate transistor for discharging A signal output circuit characterized by the above. 2. The signal output circuit according to claim 1, wherein the control signal is a sawtooth wave control signal whose voltage level increases linearly. 3. The signal output circuit according to claim 1, wherein the control signal is a step-like control signal whose voltage level increases stepwise. 4. A signal output circuit for outputting a drive signal to a capacitive load, the circuit means supplying a voltage of a level according to an input signal to the capacitive load, and an electric charge charged in the capacitive load. In a signal output circuit device comprising a plurality of signal output circuits each having an insulated gate transistor for discharging a plurality of groups, the plurality of signal output circuits are divided into a plurality of groups, and each group is divided into a plurality of groups. A signal output circuit device comprising means for applying a control signal of a predetermined level to the gate of the insulated gate transistor at different timings. 5. The signal output circuit device according to claim 4, wherein the control signal is a control signal whose voltage level gradually increases.