JPH08292898A - Microcomputer and debugging device - Google Patents

Abstract

PURPOSE: To facilitate debugging at the actual site of a microcomputer after products is mounted by constituting a storage means which stores information on the address bus and data bus when a CPU operates and sends it out. CONSTITUTION: In a shift register 3, address information and data information on the address bus 4 and data bus 5 at the fall of a CPU clock where a CPU 1 writes information in a peripheral circuit 2 are written. When the CPU 1 reads or writes data at the rise of the CPU clock, the shift register 3 inputs the address information and data information at the rise of the CPU clock. Then a communication clock is supplied from outside a microcomputer 20 to a communication clock input terminal 10, and then the address information and data information which are inputted to the shift register 3 are sent out of the microcomputer 20 from a sent data terminal 9 by one bit at each time in synchronism with the communication clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer and a debugging device capable of easily debugging a microcomputer mounted on a product.

[0002]

2. Description of the Related Art In the field of application of microcomputers, it is very difficult to debug the microcomputer after it is mounted on a product. That is, when a trouble occurs, an ICE (In-Circuit Emulator) is used to cause the same phenomenon as the trouble to debug the microcomputer. However, the microcomputer chip and the ICE installed There are many cases where the above phenomenon is not reproduced due to the difference between the two, and debugging cannot be performed easily. Thus, debugging in the field of the microcomputer after mounting is emphasized. Particularly in the case of a one-chip microcomputer, since the CPU (Central Processing Unit) is built in the chip, it is not easy to monitor the operation of the CPU from outside the chip. As a debugging device for a microcomputer, for example, in Japanese Unexamined Patent Publication No. 2-287635, a circuit and a Re requesting an interrupt to a CPU as a debugging peripheral device and Re
It is disclosed that a control device for controlling the CPU with an ady signal is provided. As described above, conventionally, in order to debug the microcomputer, the microcomputer is provided with a complicated monitor function, and the microcomputer is externally controlled to enable debugging in the field. Therefore, the conventional debug device has problems that a ROM (read only memory) for a monitor program is required, the circuit becomes complicated, and the chip unit price increases. The present invention has been made to solve such a problem, and a microcomputer and a debug device which can easily perform on-site debugging of a microcomputer mounted on a product without requiring a complicated circuit and control. The purpose is to provide.

[0003]

The microcomputer of the present invention comprises a central processing unit driven by a CPU clock, peripheral circuits connected to the central processing unit, and the central processing unit. A microcomputer having an address bus and a data bus for connecting to the peripheral circuit on a single semiconductor substrate, the microcomputer being connected to the address bus and the data bus on the semiconductor substrate, and having the CPU clock. Information of the address bus and the data bus is stored at the timing of being supplied and read or written by the central processing unit, and a communication clock generated outside the microcomputer is supplied and stored by the supply of the communication clock. The storage means for transmitting the information of the address bus and the data bus, And it said that there were pictures.

The above-mentioned central processing unit is supplied with CP
Information is read from or written to the peripheral circuits at the rising or falling of the U clock. In addition, C is also stored in the storage means.
The PU clock is supplied, and the storage means stores the information of the address bus and the data bus at the timing when the central processing unit performs the read or write. On the other hand, when the communication clock generated outside the microcomputer is supplied to the storage means,
The storage means sends the information of the address bus and the data bus stored by the above operation to the outside. As described above, since the storage means included in the microcomputer stores and sends out the information of the address bus and the data bus when the central processing unit operates by the CPU clock and the communication clock, the microcomputer is complicated. It works so that it can be observed from the outside how the central processing unit operates inside the microcomputer without requiring any circuits and controls. Therefore, the microcomputer operates so that the microcomputer mounted on the product can be easily debugged in the field.

Further, the microcomputer of the present invention is
A reception data terminal connected to the storage means for supplying external address information and external data information supplied from the outside to the storage means, and a DMA signal provided on the semiconductor substrate and supplied from outside the microcomputer. Bus connection opening means for connecting or disconnecting an address bus and a data bus between the central processing unit and the peripheral circuit based on the above, and provided on the semiconductor substrate,
Further, the external address information and external data information stored in the storage means while the connection of the address bus and the data bus is cut off by the bus release means by the supply of the DMA signal, the storage means and the peripheral circuit. DMA processing means for performing a direct memory access operation between the central processing unit and the peripheral circuit when the central processing unit and the peripheral circuits are connected by the bus connection opening means. And storing the information of the data bus and transmitting the stored information to the outside, storing the external address information and the external data information supplied through the reception data terminal, and storing the external address information and the external data information by the bus connection opening means. When the arithmetic processing unit and the peripheral circuit are separated, the stored external address information and The Kigaibu data information may be sent to the DMA unit.

With this configuration, the storage means further performs the following operation in addition to the above-mentioned operation. That is, when an H (high) level DMA signal is supplied from the outside of the microcomputer, the bus connection opening means connects the address bus and the data bus between the central processing unit and the peripheral circuits. To do. Therefore, the storage means stores the information of the address bus and the data bus based on the CPU clock as described above, and the information of the address bus and the data bus stored by the supply of the communication clock to the outside. As well as sending
The external address information and the external data information supplied via the reception data terminal are stored. On the other hand, when an L (low) level DMA signal is supplied from the outside of the microcomputer, the bus connection opening means opens the address bus and the data bus between the central processing unit and the peripheral circuits. . Then, the storage means sends the external address information and the external data information stored by the above operation to the peripheral circuit based on the communication clock. Thus, the microcomputer according to claim 1 is provided with the reception data terminal, the bus connection opening means, and the DMA.
By including the processing means, the microcomputer acts so as to be able to read and write information from and to the peripheral circuits provided in the microcomputer, and can debug not only the program of the central processing unit but also the peripheral circuits. Act on. Therefore, the microcomputer operates so that the microcomputer mounted in the product can be easily debugged in the field.

Further, the microcomputer of the present invention is
Based on a data input terminal connected to the storage means for supplying external data information supplied from the outside to the storage means, and an external command enable signal provided on the semiconductor substrate and supplied from the outside, the central processing unit Data bus connection opening means for connecting and disconnecting the data bus between the device and the peripheral circuit; and the central processing unit and the peripheral circuit provided on the semiconductor substrate and by the data bus opening means. External command output means for sending the external data information stored in the storage means to the central processing unit on the basis of the external command enable signal while the connection of the data bus between them is cut off. The storage means is provided with the storage means when the central processing unit and the peripheral circuits are connected by the data bus connection opening means. The information on the bus and the data bus is stored, the stored information is sent to the outside, and the external data information supplied via the data input terminal is stored. When disconnected from the data bus, the stored external data information can be sent to the data bus and the central processing unit can read the external data based on the CPU clock.

With this structure, the storage means further performs the following operation. That is, when an H-level external command enable signal is supplied from the outside of the microcomputer, the data bus connection opening means connects the data bus between the central processing unit and the peripheral circuits. Therefore, the storage means stores the information of the address bus and the data bus based on the CPU clock as described above, and the information of the address bus and the data bus stored by the supply of the communication clock to the outside. The external data information which is sent out and supplied through the data input terminal is stored. On the other hand, when an L level external command enable signal is supplied from outside the microcomputer, the data bus connection opening means opens the data bus between the central processing unit and the peripheral circuits. Then, the storage means sends the external data information stored in the above-described operation to the data bus, and the central processing unit reads the external data information based on the CPU clock. The microcomputer is
It acts to take in external data information supplied from the outside to the central processing unit, and to facilitate on-site debugging of the microcomputer installed in the product without the need for complicated circuits and controls. .

Further, the microcomputer of the present invention is
The central processing unit is further provided with a SYNC signal output terminal for sending a SYNC signal indicating a cycle for reading an instruction to the outside, and the communication clock is sent to the microcomputer based on the SYNC signal sent from the SYNC signal output terminal. You can also

Since the SYNC signal output terminal sends out a SYNC signal indicating that the central processing unit reads the first byte of the instruction, it supplies the instruction information to the central processing unit outside the microcomputer. Act to be able to get the timing. Therefore, the microcomputer is the above-mentioned SYN.
Since the communication clock is supplied based on the C signal, the external data information acts so as to be taken into the central processing unit at the timing. Therefore, the microcomputer operates so that the microcomputer mounted in the product can be easily debugged in the field.

According to another aspect of the present invention, there is provided a debug device for use in a microcomputer according to any one of claims 1 to 4, wherein a system clock which is provided outside the microcomputer and which is a source of a CPU clock is generated. System clock control means for controlling the supply to the microcomputer, and the CPU for monitoring the CPU clock provided outside the microcomputer and sent by the central processing unit in the microcomputer, and the central processing unit reads. Communication clock control means for detecting the writing and sending the communication clock to the central processing unit.

With respect to the storage means provided in the microcomputer according to any one of claims 1 to 4, the system clock control means controls the supply of the system clock to the microcomputer, and the communication clock control means controls the communication clock. It is sent to the central processing unit provided in the microcomputer. By thus supplying the system clock and the communication clock to the microcomputer, the storage means sends out the information of the address bus and the data bus stored when the central processing unit operates as described above. Therefore, the debug device
With the configuration in which a simple circuit is added to the microcomputer, it works so that the microcomputer mounted on the product can be easily debugged in the field.

Further, the debug device of the present invention receives the information of the address bus and the data bus, which is provided outside the microcomputer and is sent from the microcomputer, in synchronization with the communication clock and receives the received address information and the received data. A reception / comparison means for comparing information with preset address information and preset data information,
The system clock control means may be configured to control the supply of the system clock to the microcomputer based on the comparison result of the reception comparison means.

With this configuration, the reception comparison means synchronizes the information of the address bus and the data bus sent from the microcomputer based on the communication clock sent by the communication clock control means with the communication clock. To receive. Further, the reception comparing means compares the received reception address information and the reception data information described above with the preset setting address information and the setting data information. For example, the reception address information and the reception data information are the setting address information and the setting data information. If it coincides with, the system clock control means is caused to stop sending the system clock. In this way, the reception comparison means acts to realize the break after executing the debug using the ICE,
This function facilitates on-site debugging of the microcomputer installed in the product.

According to another aspect of the present invention, there is provided a debug device for use in a microcomputer according to claim 2, wherein the system clock provided to the outside of the microcomputer is a system clock which is a source of generation of the CPU clock. And a system clock control means for controlling the supply of a clock signal to the microcomputer, which is provided outside the microcomputer to instruct the system clock control means to stop the sending of the system clock and to send a DMA signal to the microcomputer for DMA operation. After the transfer, the external address information and the external data information used for the DMA operation are sent to the reception data terminal provided in the microcomputer, and the processing control means for receiving the output information of the microcomputer by the DMA operation is provided. Was And wherein the door.

The storage means provided in the microcomputer stores the information of the address bus and the data bus as described above, and also sends this information to the outside. The processing control means sends out a DMA signal and further sends out external address information or external data information. The storage means further reads / writes information from / into the peripheral circuit without using the central processing unit as described above, and also stores the stored information to the outside by the DMA signal or the external address information or the external data information. Send to. In this way, the debug device
It not only monitors the operation of the central processing unit from the outside, but also works to read and write information directly to the above peripheral circuits, making it easy to debug the microcomputer installed in the product in the field. To do.

A debug device of the present invention is the debug device used in the microcomputer according to claim 3, wherein the debug device is provided outside the microcomputer.
System clock control means for controlling the supply of the system clock, which is the source of generation of the PU clock, to the microcomputer, and an instruction provided outside the microcomputer to instruct the system clock control means to stop the sending of the system clock. Thereafter, based on the CPU clock, the external command information is sent to the microcomputer, and an external command enable signal for sending the external data information to the central processing unit of the microcomputer is sent to the microcomputer. And processing control means.

The storage means provided in the microcomputer stores the information of the address bus and the data bus as described above, and also sends this information to the outside. The processing control means sends an external command permission signal and external data information. The storage means further sends the external data information to the central processing unit as described above in response to the external command permission signal and the external data information. In this way, the debug device acts not only to monitor the operation of the central processing unit from the outside, but also to give data information, such as instruction information, directly to the central processing unit from the outside. This function facilitates on-site debugging of the mounted microcomputer.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A microcomputer which is an embodiment of the present invention will be described below with reference to the drawings. still,
In this embodiment, a shift register is taken as an example of a component that performs the same function as the "storage means" has. FIG. 1 shows a microcomputer 20 having a basic configuration of a microcomputer according to an embodiment of the present invention. The microcomputer 20 formed of one semiconductor substrate includes a CPU (Central Processing Unit) 1 and a CP.
A peripheral circuit 2 that mutually accesses the U1, a shift register 3, an address bus 4 and a data bus 5 that mutually connect the CPU 1, the peripheral circuit 2 and the shift register 3, and a system clock from the outside of the microcomputer 20. And a system clock input terminal 6 for driving the CPU 1 to divide the system clock into C
A frequency dividing circuit 7 for generating a PU clock and sending the CPU clock to the CPU 1 and the shift register 3, and a frequency dividing circuit 7
A CPU clock output terminal 8 for sending the CPU clock sent from the CPU 1 to the outside of the microcomputer 20, a transmission data terminal 9 for sending the output information of the shift register 3 to the outside of the microcomputer 20, and a microcomputer. A communication clock input terminal 10 to which a communication clock is supplied from the outside of the computer 20 is provided. The system clock is supplied to the peripheral circuit 2 as well as the frequency dividing circuit 7 via the system clock input terminal 6. The shift register 3 stores the address information and the data information transmitted through the address bus 4 and the data bus 5 according to the CPU clock supplied from the frequency dividing circuit 7, while communicating from the outside through the communication clock input terminal 10. When the clock is supplied, the stored address information and data information are sent to the outside of the microcomputer 20 via the transmission data terminal 9 in synchronization with the communication clock.

The operation of the microcomputer 20 configured as above will be described below with reference to FIG. CPU1
Is the peripheral circuit 2 at the falling edge 11a of the CPU clock 11.
Read and write information to and. In addition, in the shift register 3, the CPU 1 for reading / writing information from / to the peripheral circuit 2 is used by the CPU 1.
Address bus 4 at falling edge 11a of U clock 11
And address information 12 and data information 1 of the data bus 5.
3 is written. Note that the CPU 1 uses the CPU clock 11
When reading and writing at the rising edge of, shift register 3
Takes in address information and data information at the rising edge of the CPU clock 11. Thereafter, the communication clock 14 is input from the outside of the microcomputer 20 to the communication clock input terminal 10.
Is supplied, the address information 12 and the data information 13 taken into the shift register 3 are sent as transmission data 15 from the transmission data terminal 9 bit by bit to the outside of the microcomputer 20 in synchronization with the communication clock 14. It

As described above, according to the microcomputer 20, the shift register 3 stores the information of the address bus 4 and the data bus 5 when the CPU 1 operates by the CPU clock 11 and sends out the information by the communication clock 14. Therefore, the microcomputer 20 does not require complicated circuits and controls, and the C
It is possible to observe from outside how the PU1 operates. Therefore, the microcomputer 20 is
Debugging of the microcomputer installed in the product in the field can be easily performed.

Next, another embodiment of a microcomputer 40 will be described below with reference to FIGS. 3 and 4. 3 and 4, the same components as those shown in FIGS. 1 and 2 are designated by the same reference numerals, and the description thereof will be omitted. In addition to the configuration of the microcomputer 20 described above, the microcomputer 40 further includes a bus connection opening means 25, a DMA processing means 26, a DMA permission terminal 27 to which a DMA signal is supplied from the outside of the microcomputer 40, and received data. And a terminal 28. The microcomputer 40 has a shift register 29 instead of the shift register 3. The bus connection opening means 25 is C
It is provided on the address bus 4 and the data bus 5 between the PU 1 and the peripheral circuit 2 and the shift register 29.
The CPU 1 and the address bus 4 and the data bus 5 are connected and disconnected according to the DMA signal supplied via the MA permission terminal 27. The shift register 29 stores, in addition to the address information 12 and the data information 13, bit data of an R / W signal indicating a read or write operation of information.
The DMA processing means 26 is connected to the output side of the shift register 29, and the output of the DMA processing means 26 is connected to the address bus 4 and the data bus 5, respectively.

These bus connection opening means 25, shift register 29 and DMA processing means 26 operate as follows. When the DMA signal supplied to the microcomputer 40 is at H level, for example, the bus connection opening means 25
Connects the CPU 1 to the peripheral circuit 2 and the shift register 29. Therefore, the shift register 29, like the operation of the shift register 3, has the falling edge 1 of the CPU clock 11.
1a stores the address information 12 of the address bus 4 and the data information 13 of the data bus 5, and the CPU 1
It also stores the R / W signal sent by. Further, the shift register 29 receives the communication clock 14 from the outside via the communication clock input terminal 10 when the DMA signal is at the H level, for example.
Is supplied, the stored address information 12 and the like is sent to the transmission data terminal 9 by one bit, and at the same time, external information supplied from the outside through the reception data terminal 28, that is, external address information and external data. Information and external R
Take in the / W signal. On the other hand, when the L level DMA signal is supplied, the bus connection opening means 25 disconnects the CPU 1, the address bus 4 and the data bus 5, and the DMA processing means 26 outputs the external address information stored in the shift register 29, the external The data information and the external R / W signal are read from and written to the peripheral circuit 2 via the address bus 4 and the data bus 5 based on the communication clock 14.

The operation of the microcomputer 40 thus constructed will be described. In the operation timing chart of the microcomputer 40 shown in FIG.
When the MA signal is supplied, the states of the address bus 4 and the data bus 5 at the falling edge 11a of the CPU clock 11 and the R / W signal are fetched into the shift register 29. When the communication clock 14 is supplied, the address bus information 12, the data bus information 13, and the R / W signal fetched in the shift register 29 are output from the microcomputer 40 as transmission data 15, and at the same time the reception data 30 is shifted. Take in.

Next, when the L level DMA signal is supplied through the DMA permission terminal 27, the bus connection opening means 25
Thus, the CPU 1 is disconnected from the address bus 4 and the data bus 5. When the bit data of the R / W signal is “1” in the received data 30 fetched from the outside into the shift register 29, the DMA processing means 26 uses the external address information stored in the shift register 29 as the communication clock 14
Is output to the address bus 4 at the first clock and the data information read from the peripheral circuit 2 by the external address information is fetched at the shift register 29 at the second clock. When the bit data of the R / W signal is "0", the DMA processing means 26 transfers the external address information and the external data information stored in the shift register 29 at the first clock of the communication clock 14 to the address bus 4, The data is output to the data bus 5, the R / W signal is set to the L level at the second clock, and the R / W signal is set to the H level at the third clock.
The data information supplied from the outside to the shift register 29 and stored therein is written to. Next, when the H-level DMA signal is supplied, the bus connection opening means 25
PU1 is connected to the peripheral circuit 2 again, and L level DMA
It returns to the state before the signal was supplied. When the communication clock 14 is supplied here, the DMA processing unit 26 causes the peripheral circuit 2 to operate.
Data stored in the shift register 29 and read out from the device is transmitted from the shift register 29 to the outside via the transmission data terminal 9.

As described above, according to the microcomputer 40, the peripheral circuit 2 provided in the microcomputer 40.
Information can be read from and written to the peripheral circuit 2 as well as the program of the CPU 1 can be debugged. Therefore, the microcomputer 40 can easily perform on-site debugging of the microcomputer mounted on the product.

A microcomputer 60 according to another embodiment will be described below with reference to FIGS. 5 and 6. 5 and 6, the same components as those shown in FIGS. 1 to 4 are designated by the same reference numerals, and the description thereof will be omitted. In addition to the configuration of the microcomputer 20 described above, the microcomputer 60 is further provided with a data bus connection opening unit 41, an external command output unit 43, and an external command permission signal 51 supplied from outside the microcomputer 60. An instruction permission terminal 44, a data input terminal 45 to which external data information is supplied from the outside, and SY indicating a cycle in which the CPU 1 reads an instruction.
SYNC output terminal 4 for sending NC signal 52 to the outside
6 and 6. Further, the microcomputer 60 includes a shift register 42 instead of the shift register 3.
The shift register 42 stores external data information supplied from the outside through the data input terminal 45, stores information of the address bus 4 and the data bus 5, and transmits the data terminal 9.
Stored information is sent to. Data bus connection opening means 4
1 is externally supplied with the external command enable signal 51 via the external command enable terminal 44, and the data bus connection opening means 41 is responsive to the external command enable signal 51 to connect the data bus 5 between the CPU 1 and the peripheral circuit 2. Connect and disconnect. The external command output means 43 is connected to the output side of the shift register 42 and sends the data information sent from the shift register 42 to the data bus 5 based on the external command enable signal 51.

The operation of the microcomputer 60 thus constructed will be described below. In this embodiment, command information supplied to the CPU 1 is taken as an example of the external data information. When the H-level external command enable signal 51 is supplied through the external command enable terminal 44, C
At the falling edge 11a of the PU clock 11, the shift register 4
2 stores the states of the address bus 4 and the data bus 5 and supplies the communication clock 14 to the microcomputer 60, so that the information stored in the shift register 42 is transmitted bit by bit to the outside via the transmission data terminal 9. Sent out. Further, at this time, in synchronization with the communication clock 14, the external data information 53 externally supplied via the data input terminal 45 is fetched into the shift register 42 bit by bit.

When the L level external command enable signal 51a is supplied, the peripheral circuit 2 is disconnected from the data bus 5,
The external command output means 43 sends the data sent from the shift register 42 to the data bus 5. In this state, the CPU
At the falling edge 11b of the clock 11, the CPU 1 reads the data sent from the external command output means 43 to the data bus 5, that is, the external data information supplied to the shift register 42 from the outside as a command. Further, a SYNC signal 52 indicating that the CPU 1 is a cycle for reading the first byte of an instruction is sent from the CPU 1 to the outside via the SYNC output terminal 46. By monitoring the SYNC signal 52 outside the microcomputer 60, the timing of giving the command information to the microcomputer 60 can be obtained.

Based on the above-mentioned operation, the operation of the microcomputer 60 will be described more specifically with reference to FIG. 6, taking as an example the case where an instruction to write the data of the shift register 42 to a certain address is executed. As described above, when the external data information is supplied as an instruction to the CPU 1 and the CPU 1 executes this instruction, the CPU 1
The instruction is read at the first clock of the CPU clock whose NC signal 52 is at the H level, the address is read at the second clock, and the data is written at the designated address at the third clock. In FIG. 6, only the time corresponding to one command is shown. Upon execution of the above instruction, the SYNC signal 52 goes high at the falling edge 11a of the CPU clock 11. Therefore, by externally monitoring the SYNC signal 52, it is possible to externally monitor that the CPU 1 is a cycle for reading the first byte of an instruction. At this time, if the communication clock 14 is supplied to the microcomputer 60, the CP
Information on the address bus and the data bus when the CPU reads / writes at the falling edge of the U clock 11 is sent to the outside from the transmission data terminal 9. Next, when the communication clock 14 is supplied, external data information is externally captured bit by bit into the shift register 42 via the data input terminal 45.

When the L level external command enable signal 51a is supplied, the external command output means 43 causes the shift register 42 to operate.
When the CPU clock 11 falls, the CPU 1 reads the stored data in the data bus 5 as an instruction when the CPU clock 11 falls. Similarly, the second byte instruction is sent to the CPU 1 at the next falling edge of the CPU clock 11.
To read. If the third clock is supplied as it is,
The CPU 1 executes the instruction read at the first clock and the second clock at the falling edge of the third clock. After that, when the communication clock 14 is supplied to the microcomputer 60, the result information, which is the result information executed by the CPU 1, is sent out from the transmission data terminal 9.

As described above, according to the microcomputer 60, external data information can be supplied from the outside as an instruction to the CPU 1, and further, the result information executed by the CPU 1 based on the supplied external data information is used as the shift register 42. Can be sent to the outside. Therefore, as compared with the microcomputer 40 described above, more advanced debugging can be performed with a simple structure and simple control.

Next, a debug device for debugging the above microcomputers will be described.
The microcomputer shown in FIG. 7 corresponds to the microcomputers 20, 40 and 60 described above. For the sake of explanation, the microcomputer 20 will be taken as an example of these microcomputers. The debugging device 80 of this embodiment includes a system clock control means 81 which is connected to the system clock input terminal 6 provided in the microcomputer 20 and controls the sending of the system clock in the microcomputer 20.
Connected to the CPU clock output terminal 8 and the communication clock input terminal 10 provided at 0, for example, the falling of the CPU clock sent from the CPU clock output terminal 8 is monitored to detect that the CPU 1 has read or written and the communication clock To the communication clock input terminal 10. The frequency of the system clock is set by the operator.

The operation of the debug device 80 configured as above will be described. CPU1 of the microcomputer 20
Is a CP obtained by dividing the system clock supplied from the system clock control means 81 by the frequency dividing circuit 7.
It operates on the U clock, and the CPU clock is supplied to the communication clock control means 82 via the CPU clock output terminal 8. The communication clock control means 82 detects the fall of the CPU clock, stores the data information of the address bus 4 and the data bus 5 in the shift register 3, and sends the stored data information to the outside from the shift register 3. A communication clock for sending is sent to the microcomputer 20. As described above, the debug device 80 can easily perform the debugging work in the field of the microcomputer mounted on the product only by adding a simple circuit to the microcomputer.

Further, as shown in FIG. 7, a debug device 87 can be configured by further adding a receiving means 83, an address bus, and a data bus monitoring means 84 to the above-described structure of the debug device 80. The receiving means 83 is connected to the communication clock control means 82 and the communication data terminal 9 provided in the microcomputer 20. The address bus / data bus monitoring means 84 is connected to the communication clock control means 82, the receiving means 83, and the system clock control means 81. The receiving means 83, the address bus, and the data bus monitoring means 84 are collectively referred to as reception comparing means.

The operation of the debug device 87 configured as above will be described. As described above, the communication clock control means 82 detects the fall of the CPU clock and sends the communication clock to the microcomputer 20. Receiving means 8
3 is a microcomputer 2 in synchronization with a communication clock
Information of the address bus 4 and the data bus 5 sent from the shift register 3 of 0 via the transmission data terminal 9 is received, and the received information is sent to the address bus and data bus monitoring means 84. On the other hand, the communication clock control means 82
When it judges that all data has been received by counting the number of communication clocks supplied to the microcomputer 20, it notifies the address bus / data bus monitoring means 84 of the end of communication data reception. The address bus / data bus monitoring means 84 is supplied with the communication data reception end, so that the information of the address bus 4 and the data bus 5 supplied from the receiving means 83 is changed by the operator to the address bus / data bus monitoring means 84. Check to see if the break condition matches the preset break condition. And if it matches the above break condition,
The address bus / data bus monitoring means 84 instructs the system clock control means 81 to stop the system clock.

As described above, the debug device 87 is, for example, I
The CE can be used to implement breaks after performing microcomputer debugging. Therefore, by using the debug device 87, debugging in the field of the microcomputer mounted on the product can be easily performed.

Furthermore, as shown in FIG. 8, for example, a semiconductor memory 91 as a storage means is connected to the communication clock control means 82 and the receiving means 83, and a display device 92 for visually displaying the contents of the memory 91 is provided as a memory. You may make it connect to 91. In FIG. 8, the same components as those shown in FIG. 7 are designated by the same reference numerals. With this configuration, the information stored in the shift register 3 sent from the microcomputer 20 can be stored in the memory 9
1 and the information stored in the memory 91 can be displayed on the display device 92.
It is possible to visually observe how the CPU 1 operates. Therefore, it is possible to easily debug the microcomputer mounted on the product in the field.

A debug device according to another embodiment will be described. FIG. 9 shows the microcomputer 40 described above.
The debug device 100 etc. which are used for FIG. In FIG. 9, the same components as those shown in FIGS. 7 and 8 are designated by the same reference numerals, and the description thereof will be omitted. Debug device 1
00 includes a system clock control unit 81, a communication clock second control unit 101, a processing unit 102, a transmission unit 103, and a reception unit 104. Incidentally, the communication clock second control means 101, the processing means 102, the transmission means 1
03 and the receiving means 104 constitute a processing control means. The processing means 102 includes a CPU clock output terminal 8 and a DMA permission terminal 2 provided in the microcomputer 40.
7 and the communication clock input terminal 10, and
It is also connected to the transmission means 103. The transmission means 103 is a reception data terminal 2 provided in the microcomputer 40.
8 is connected. The receiving means 104 is connected to the transmission data terminal 9 of the microcomputer 40. Further, the communication clock second control means 101 is connected to the communication clock input terminal 10, the transmission means 103, and the reception means 104 of the microcomputer 40. In addition, the debug device 1
00, the memory 91 connected to the receiving means 104,
The debug device 110 can also be configured by providing a display device 92 connected to the memory 91.

The debug device 10 configured as described above
The operation of 0 and 110 will be described below. In the case of normal debug operation in which the DMA operation is not performed on the microcomputer 40, the debug device 100 and the like operate as follows. That is, the CPU clock sent from the microcomputer 40 is supplied to the processing means 102, and when the processing means 102 detects the fall of the CPU clock, the processing means 102 instructs the communication clock second control means 101 to start reception, and the communication clock second The control means 101 sends a communication clock to the microcomputer 40, and the microcomputer 4
The information of the address bus 4 and the data bus 5 is sent from the shift register 29 provided in 0 to the receiving means 104 via the transmission data terminal 9. Communication clock second control means 101
Counts the number of clocks of the clock supplied to the communication clock input terminal 10, and stores the received data in the memory 91, which is a storage device, when it detects that all the data has been received. Further, by outputting the information stored in the memory 91 to an output device such as the display device 92, it is possible to observe how the CPU 1 of the microcomputer 40 operates.

When the microcomputer 40 is caused to perform the DMA operation and the data is directly read from the peripheral circuit 2 of the microcomputer 40, the processing means 102 causes the system clock control means 81 to stop the system clock and stop the CPU 1. , The read instruction and the external address information are sent to the sending means 103, and the communication clock second
It instructs the control means 101 to transmit the external data information.
The external address information and the external data information are supplied to the processing means 102 by the operator. After the transmission is completed, the processing means 102 sends the L-level DMA signal to the microcomputer 40 and sends the communication clock directly to the microcomputer 40 to cause the DMA processing means 26 of the microcomputer 40 to shift register 29.
The stored data of is read. Next, the processing means 10
2 is an H level DMA signal for the microcomputer 4
The communication clock second control means 101 is instructed to receive the read data information in order to send the data information read out from the shift register 29 to the outside of the microcomputer 40. Therefore, the receiving means 1
The data information read from the peripheral circuit 2 in the microcomputer 40 can be known from the data information received via 04, and debugging can be easily performed.

When the external data information is directly written to the peripheral circuit 2 of the microcomputer 40, the processing means 102 causes the system clock control means 81 to stop the sending of the system clock and the microcomputer 4
The operation of the CPU 1 of 0 is stopped, a writing instruction and external address information and external data information are sent to the transmission means 103, and the communication clock second control means 101 is instructed to send a communication clock for data transmission. After the transmission is completed, the processing means 102 sends out an L level DMA signal,
The DMA processing means 2 of the microcomputer 40 by directly sending the communication clock to the microcomputer 40.
6 to write external data information to the peripheral circuit 2. Next, the processing means 102 sends an H level DMA signal and ends the processing.

As described above, according to the debug device 100 and the like, the operation of the CPU can be monitored from the outside by sending the information stored in the shift register 29 to the outside of the microcomputer, and further the DMA operation is performed on the microcomputer. Therefore, it is possible to directly read / write information from / to the peripheral circuit 2 in the microcomputer from outside the microcomputer. Therefore, the debug device 100 and the like can more easily perform the debug operation in the field of the microcomputer mounted on the product, and can also debug the peripheral circuit.

A debug device according to another embodiment will be described. FIG. 10 shows the microcomputer 6 described above.
0 shows the debug device 120 used. In FIG. 10, the same components as those shown in FIG. 9 are designated by the same reference numerals and the description thereof will be omitted. The debug device 120 includes a processing unit 121 instead of the processing unit 102 described with reference to FIG. Other configurations are the same as those of the debug device 110 described above. As the processing control means, it is preferable that at least the communication clock second control means 101, the processing means 121, and the transmission means 103 are configured, and the reception means 104 is further added. Also, the processing means 1
21 is connected to an external command permission terminal 44, a SYNC output terminal 46 and a CPU clock output terminal 8 provided in the microcomputer 60.

The debug device 120 configured as described above
Will be described. In the case of a normal debug operation in which no instruction is externally supplied to the microcomputer 60, the debug device 120 uses the debug device 11 described above.
Similar to 0, it operates as follows. That is, the CPU clock sent from the microcomputer 60 is the processing means 1
02, the processing means 102, when detecting the fall of the CPU clock, instructs the communication clock second control means 101 to start reception, and the communication clock second control means 10
1 transmits a communication clock to the microcomputer 60, and causes the shift register 42 provided in the microcomputer 60 to transmit the information of the address bus 4 and the data bus 5 to the receiving means 104 via the transmission data terminal 9. The communication clock second control means 101 counts the number of clocks of the clock supplied to the communication clock input terminal 10, and when it detects that all the data has been received, stores the received data in the memory 91 which is a storage device. I do. Further, the information stored in the memory 91 is output to an output device such as the display device 92, whereby the microcomputer 40
It is possible to observe how the CPU 1 of 1. operated.

When causing the microcomputer 60 to execute an instruction from the outside, when the processing means 121 detects the rise of the CPU clock when the SYNC signal is at the H level, the processing means 121 causes the system clock control means 81 to operate.
Then, the sending of the system clock is stopped and the CPU 1 of the microcomputer 60 is stopped. Further processing means 12
1 sends an instruction code to the transmitting means 103, and causes the communication clock second control means 101 to send a communication clock to the microcomputer 60 to send the microcomputer 60.
The above instruction code is transmitted to.

After the transmission of the above instruction code is completed, the processing means 1
21 sends an L level external command enable signal to cause the system clock control means 81 to perform the operation until the fall of the CPU clock, and the CPU 1 of the microcomputer 60.
After reading the above instruction code, sends an external instruction permission signal of H level. When the instruction to be executed by the CPU 1 is composed of a plurality of bytes, the processing means 121
Causes the system clock control means 81 to operate the system clock until the next rise of the CPU clock, and sends the next second byte of the instruction code to the transmission means 103,
Similar to the first byte of the instruction code, a series of operations of transmission, transmission of an L level external instruction enable signal, supply of a system clock until the fall of the CPU clock, and transmission of an H level external instruction enable signal are performed. Let When the CPU 1 executes an instruction at the next CPU clock, the external instruction enable signal is kept at H level and the system clock is sent to the microcomputer 60 until the rising of the next CPU clock. If the instruction executed by the CPU 1 is read, the communication clock second control means 101 sends a communication clock to the microcomputer 60, and the receiving means 104 receives data from the microcomputer 60. Therefore, according to the external command supplied from the outside, CP
Result data, which is a result of the operation of U1, can be received.

As described above, according to the debug device 120,
The operation of the CPU of the microcomputer mounted on the product can be monitored from the outside, and by supplying an instruction to the CPU from the outside, it is possible to easily perform advanced debugging similar to ICE. It can be carried out.

The debug device 120 described above can also be configured as follows. Address bus 4 to the shift register 42 of the microcomputer 60,
Information is taken in the data bus 5 not only at the fall of the CPU clock but also at the rise and fall thereof. By doing this, when the CPU clock falls, CP
The result of reading and writing executed by U1 is fetched into the shift register 42, and at the rising edge of the CPU clock, the current CPU
The address output by 1 is taken into the shift register 42. Therefore, by reading the address of the shift register 42 after the rise of the CPU clock, when the read address matches the address at which the break occurs, the processing means 121 causes the system clock control means 81 to stop sending the system clock. be able to. Therefore, a break can be made before the CPU 1 executes at that address. Note that FIG. 11 shows the timing when the above-mentioned pre-execution break is performed.

Further, in the above-described debug device 120, as shown in FIG. 12, the second memory 130 for storing the instructions to be executed by the processing means 121 can be connected to the processing means 121. By adding the second memory 130 as described above, the second memory 130 can be provided while the program inside the microcomputer 60 is being executed.
It is also possible to execute the program stored in. Therefore, it is possible to easily modify and debug the program even in the microcomputer mounted on the product.

[0051]

As described above in detail, according to the microcomputer of the first aspect, the storage means stores the information of the address bus and the data bus when the CPU operates and sends it to the outside, which is complicated. It is possible to externally observe how the CPU operates inside the microcomputer without requiring any circuits and controls. Therefore, the microcomputer can easily debug the microcomputer mounted on the product in the field. Further, according to the microcomputer of the second aspect, since it is possible to perform the DMA operation, it is possible to read and write information from and to the peripheral circuit provided in the microcomputer, and not only the CPU in the microcomputer, It is also possible to debug the peripheral circuit. Therefore, the microcomputer can easily debug the microcomputer mounted on the product in the field. Further, according to the microcomputer of the third aspect, the external data information is stored in the storing means by using the external command enable signal and the external data information is sent to the CPU. Therefore, based on the external data information. The CPU can be operated. Therefore, the microcomputer can easily debug the microcomputer mounted on the product in the field. According to the microcomputer of claim 4, S
By transmitting the YNC signal, the C of the microcomputer can be sent from outside the microcomputer.
The timing of giving the instruction information to the PU can be obtained. Therefore, the microcomputer can easily debug the microcomputer mounted on the product in the field. According to the debug device of the fifth aspect, the storage means includes the system clock control means for controlling the supply of the system clock to the microcomputer and the communication clock control means for sending the communication clock to the microcomputer. Can store and send data. Therefore, the debugging device can easily perform on-site debugging of the microcomputer mounted on the product. According to the debug device of claim 8,
Since the processing control means for transmitting the DMA signal, the external address information and the external data information is provided, the storage means is C
Information can be read from and written to the peripheral circuits provided in the microcomputer without going through the PU. Therefore,
The debugging device makes it possible to easily debug the microcomputer installed in the product in the field. Further, according to the debug device of the tenth aspect, since the processing control means for transmitting the external command permission signal and the external data information is provided, the CPU provided in the microcomputer can be operated by the external data information. . Therefore, the debugging device can easily perform on-site debugging of the microcomputer mounted on the product.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a microcomputer that is an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the microcomputer shown in FIG.

FIG. 3 is a block diagram showing another configuration example of the microcomputer that is an embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the microcomputer shown in FIG.

FIG. 5 is a block diagram showing another configuration example of the microcomputer that is an embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the microcomputer shown in FIG.

FIG. 7 is a block diagram showing a configuration example of a debug device that is an embodiment of the present invention.

FIG. 8 is a block diagram illustrating another configuration example of the debug device that is an embodiment of the present invention.

FIG. 9 is a block diagram showing another configuration example of the debug device according to the embodiment of the present invention.

FIG. 10 is a block diagram showing still another configuration example of the debug device which is an embodiment of the present invention.

11 is a timing chart for explaining the operation of the debug device shown in FIG.

FIG. 12 is a block diagram showing still another configuration example of the debug device which is an embodiment of the present invention.

[Explanation of symbols]

1 ... CPU, 2 ... Peripheral circuit, 3 ... Shift register, 4 ...
Address bus, 5 ... Data bus, 6 ... System clock input terminal, 7 ... Divider circuit, 8 ... CPU clock output terminal, 9 ... Transmission data terminal, 10 ... Communication clock input terminal, 11 ... CPU clock, 14 ... Communication clock , 20
… Microcomputer, 25… Bus connection opening means, 2
6 ... DMA processing means, 27 ... DMA permission terminal, 28 ... Reception data terminal, 29 ... Shift register, 30 ... Reception data, 40 ... Microcomputer, 41 ... Data bus connection opening means, 42 ... Shift register, 43 ... External instruction Output means, 44 ... External command enable terminal, 45 ... Data input terminal, 46 ... SYNC output terminal, 51 ... External command enable signal, 52 ... SYNC signal, 53 ... External data information, 60
… Microcomputer, 80… Debugging device, 81…
System clock control means, 82 ... Communication clock control means, 83 ... Receiving means, 84 ... Address bus, data bus monitoring means, 87 ... Debugging device, 91 ... Memory, 92 ...
Display device, 100 ... Debug device, 101 ... Communication clock second control means, 102 ... Processing means, 103 ... Sending means, 104 ... Receiving means, 110 ... Debugging device, 120
... debug device, 121 ... processing means, 130 ... second memory.

Claims (13)

[Claims] 1. A central processing unit driven by a CPU clock, a peripheral circuit connected to the central processing unit, and an address bus and a data bus connecting the central processing unit and the peripheral circuit. A microcomputer having a single semiconductor substrate, which is connected to the address bus and the data bus on the semiconductor substrate and is supplied with the CPU clock at a timing for reading or writing by the central processing unit. Stores the information of the address bus and the data bus,
Further, the microcomputer is provided with a storage means for supplying information of the address bus and the data bus, which is supplied with a communication clock generated outside the microcomputer and is stored by the supply of the communication clock, to the outside. Computer. 2. A reception data terminal connected to the storage means for supplying external address information and external data information supplied from the outside to the storage means, and provided from the outside of the microcomputer on the semiconductor substrate. Bus connection opening means for connecting or disconnecting an address bus and a data bus between the central processing unit and the peripheral circuit based on the supplied DMA signal; and a bus connection opening means provided on the semiconductor substrate for storing the DMA signal. The external address information and the external data information stored in the storage means are directly connected between the storage means and the peripheral circuit while the connection of the address bus and the data bus is cut off by the bus opening means by the supply. DMA processing means for performing a memory access operation, wherein the storage means is the bus connection opening means. When the central processing unit and the peripheral circuits are connected to each other, the information of the address bus and the data bus is stored and the stored information is sent to the outside and is supplied via the reception data terminal. The external address information and the external data information that are stored are stored, and when the central processing unit and the peripheral circuit are separated by the bus connection opening means, the stored external address information and the external information. The microcomputer according to claim 1, which sends data information to said DMA means. 3. A data input terminal connected to the storage means for supplying external data information supplied from the outside to the storage means, and an external command enable signal provided on the semiconductor substrate and supplied from the outside. A data bus connection opening means for connecting and disconnecting the data bus between the central processing unit and the peripheral circuit based on the above, and the central processing unit provided on the semiconductor substrate and by the data bus opening means. An external command for sending the external data information stored in the storage means to the central processing unit based on the external command enable signal while the connection of the data bus between the peripheral circuit and the peripheral circuit is cut off. Output means, and the storage means connects the central processing unit and the peripheral circuit by the data bus connection opening means. In this case, the information of the address bus and the data bus is stored, the stored information is sent to the outside, and the external data information supplied via the data input terminal is stored, and the data bus connection opening means is provided. When the peripheral circuit is disconnected from the data bus according to, the stored external data information is sent to the data bus and the central processing unit reads the external data based on the CPU clock. 1. The microcomputer according to 1. 4. A SYNC signal which sends a SYNC signal indicating a cycle in which the central processing unit reads an instruction to the outside.
4. The microcomputer according to claim 3, further comprising a signal output terminal, wherein the communication clock is sent to the microcomputer based on a SYNC signal sent from the SYNC signal output terminal. 5. The debugging device used in the microcomputer according to claim 1, wherein a system clock provided outside the microcomputer and serving as a source of a CPU clock is supplied to the microcomputer. System clock control means for controlling supply, and the C provided outside the microcomputer and sent by a central processing unit in the microcomputer.
A debug device, comprising: a communication clock control means for monitoring the PU clock, detecting that the central processing unit has read or written, and sending the communication clock to the central processing unit. 6. A setting in which information of an address bus and a data bus provided outside the microcomputer and sent from the microcomputer is received in synchronization with the communication clock, and the received address information and the received data information are set in advance. 6. The reception / comparison means for comparing with the address information and the setting data information, wherein the system clock control means controls the supply of the system clock to the microcomputer based on the comparison result in the reception / comparison means. Debug device. 7. Storage means connected to the reception comparing means for storing the reception address information and the reception data information for each CPU clock, and the information provided outside the microcomputer and stored in the storage means are visible. The display device according to claim 6, further comprising: 8. The debugging device used in the microcomputer according to claim 2, wherein the CPU is provided outside the microcomputer.
System clock control means for controlling the supply of the system clock, which is the source of clock generation, to the microcomputer; and an instruction provided outside the microcomputer for instructing the system clock control means to stop the transmission of the system clock. A DMA signal is sent to the microcomputer, and after shifting to the DMA operation, the external address information and the external data information used for the DMA operation are sent to a reception data terminal provided in the microcomputer, and the microcomputer by the DMA operation is sent. A debug device, comprising: a process control unit that receives output information from a computer. 9. Storage means provided outside the microcomputer and connected to the processing control means to store the output information; and information stored outside the microcomputer and stored in the storage means visually. The display device for displaying, The debug device of Claim 8 provided. 10. The debug device used in the microcomputer according to claim 3, wherein a system clock provided outside the microcomputer for controlling supply of a system clock, which is a source of generation of a CPU clock, to the microcomputer. Control means and a microcomputer provided outside the microcomputer, which instructs the system clock control means to stop the sending of the system clock, and then sends external data information to the microcomputer based on the CPU clock, and the microcomputer. And a processing control means for sending an external command permission signal to the microcomputer for instructing the central processing unit provided therein to fetch the external data information. 11. The processing control means comprises a receiving means for receiving output information sent by the microcomputer after the central processing unit executes the external data information, and is connected to the receiving means. 11. The debugging device according to claim 10, further comprising: a storage unit that stores the information and a display device that is provided outside the microcomputer and that visually displays the information stored in the storage unit. 12. A second storage means connected to the processing control means for storing instruction information to be executed by the central processing unit as the external data information, wherein the external instruction permission signal is supplied from the processing control means. The debug device according to claim 10 or 11, wherein the central processing unit performs processing based on the command information supplied from the storage means. 13. The processing control means monitors the address information supplied from the microcomputer and stores the address information when the storage means included in the microcomputer stores information at the rising and falling edges of the CPU clock. 13. The debug device according to claim 11 or 12, which stops the transmission of the system clock when the specified address matches a specific address.