JP2945196B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (CP).
The present invention relates to a microcomputer having a built-in emulator interface circuit for externally monitoring the operation of U).

2. Description of the Related Art Recent microcomputers have a built-in emulator interface circuit, and an ICE (in-circuit
There is an apparatus in which the operation of the CPU is externally controlled and monitored (emulated) by an emulator. With the speeding-up of microcomputers, the emulating function of the ICE device has also been speeded up. However, when operating the CPU of the microcomputer using the data of the ICE apparatus, it is difficult to operate the emulator interface circuit at the same speed as the CPU because the data is a signal from outside the device. For this reason, there is a demand for a microcomputer that can speed up the emulation function.

[0003]

2. Description of the Related Art FIG. 4 schematically shows a conventional microcomputer 30. An emulator interface circuit 32 is connected to the CPU 31, and the CPU 31 and the emulator interface circuit 32 are supplied with a system clock signal SCLK0 having a period of 2t. The period 2t of the system clock signal SCLK0 was longer than the access time when accessing the memory on the external ICE device side.

When the break signal BRK is not input from an external ICE device (not shown), the CPU
Reference numeral 31 outputs an L-level mode transition signal MOD to the emulator interface circuit 32 to set the emulator interface circuit 32 to the execution history transmission mode. CPU
31 executes various digital signal processing according to a user program based on the system clock signal SCLK0,
Data signal DATA or status signal STA in real time
The execution history such as TUS is output to the emulator interface circuit 32. Emulator interface circuit 32
Is based on the system clock signal SCLK0,
1 is transmitted to the external ICE device.

When a break signal BRK is being input from an external ICE device (not shown), the CPU 31 outputs an H-level mode transition signal MOD to the emulator interface circuit 32 to connect the emulator interface circuit 32 to external data input. Emulation mode that can be used. With this operation, the emulator interface circuit 32 operates based on the system clock signal SCLK0.
A standby command WAIT or a monitor program from the external ICE device is input and output to the CPU 31 or the CPU 3
1 is transmitted to the external ICE device.

Therefore, the data signal IDATA between the emulator interface circuit 32 and the external ICE device is
Alternatively, as shown in FIG. 5, the status signal ISTATUS changes in the same cycle before and after the change in the mode transition signal MOD, that is, in a cycle 2t.

As described above, in the conventional microcomputer 30, the operation of the CPU 31 is executed based on the system clock signal SCLK0 having a low frequency of 2t, so that the emulator interface circuit 32 also operates based on the system clock signal SCLK0. A monitor program or the like can be input by accessing the memory on the device side.

[0008]

However, with the recent increase in the speed of the microcomputer 30, the frequency of the system clock signal has been increasing, and the emulator interface circuit 32 has stored the execution history of the CPU 31 in the external I / O.
If the signal is only sent to the CE device, the emulator interface circuit 32 can be operated based on the system clock signal having this high frequency.

However, when a monitor program for an external ICE device is input via the emulator interface circuit 32, the cycle of the system clock signal cannot be shorter than the access time. That is, when the operating speed of the microcomputer is increased, the operating speed of the emulator interface circuit is also increased, and there is a problem that the access time of the memory of the external ICE device cannot be secured.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has been made in consideration of the problems described above.
It is an object of the present invention to realize an emulator interface circuit that can transmit data to the E device at a high speed and can operate at a low speed when accessing the memory of the external ICE device.

[0011]

FIG. 1 is a diagram illustrating the principle of the present invention. The central processing unit 1 has a system clock signal SC.
Perform digital signal processing based on LK. Emulator clock generation circuit 3 and system clock signal SCL
When K is input and a mode transition signal MOD enabling external data input is input from the central processing unit 1, a clock signal lower in frequency than the system clock signal SCLK is set as the emulator clock signal ICLK, and the mode transition signal MOD is When not input, the system clock signal SCLK is supplied to the emulator clock signal I.
It is supplied to the emulator interface circuit 2 as CLK.

Then, the emulator interface circuit 2 monitors the operation of the central processing unit 1 based on the emulator clock signal ICLK.

[0013]

When the mode transition signal MOD is not input from the central processing unit 1, the system clock signal SCLK
Is supplied to the emulator interface circuit 2 as the emulator clock signal ICLK, the emulator interface circuit 2 operates at high speed, and the execution history of the central processing unit 1 is sent to the outside at high speed. Further, when the mode transition signal MOD enabling input of external data is input from the central processing unit 1, a clock signal lower in frequency than the system clock signal SCLK is supplied to the emulator interface circuit 2 as the emulator clock signal ICLK. The emulator interface circuit 2 operates at a low speed, and can access an external memory.

[0014]

FIG. 2 shows an embodiment of the present invention.
This will be described with reference to FIG. As shown in FIG. 2, an external ICE device 13 including an ICE body 11 and a terminal personal computer 12 can be connected to the microcomputer 10 via a buffer box (not shown).

The microcomputer 10 includes a CPU 15, a RAM 16, and an R, which are formed on one semiconductor chip 14.
It comprises an OM 17, a peripheral circuit 18 such as a timer and a serial interface, an emulator interface circuit 19, an emulator clock generation circuit 20, and the like. CPU 15, RAM 16, ROM 17, peripheral circuit 1
8 are connected to each other via a data bus 21.

A CPU 15 supplies a system clock signal S having a period t shown in FIG.
CLK and the external ICE device 13
Is supplied with a break signal BRK. The CPU 15 outputs an L-level mode transition signal MOD to the emulator interface circuit 19 and the emulator clock generation circuit 20 when the break signal BRK is not input, and outputs the L level mode transition signal MOD to the emulator interface circuit 19 and the emulator when the break signal BRK is input. An H level mode transition signal MOD is output to the clock generation circuit 20.

Then, the CPU 15 outputs the break signal BRK.
Is not input, the system clock signal S
Various digital signal processes are executed in accordance with the user program stored in the ROM 17 based on the clock signal CLK, and the data signal DATA or the status signal STATU is executed in real time.
Emulator interface circuit 19
Output to While the break signal BRK is being input, the CPU 15 executes digital signal processing according to the monitor program from the external ICE device 13 based on the system clock signal SCLK, and outputs the execution history to the emulator interface circuit 19.

The emulator clock generation circuit 20 has a data flip-flop (hereinafter, simply referred to as F
F) 22, multiplexer 23 and buffer 24
It is provided with. The data terminal D of the data FF 22 is connected to the inverted output terminal bar Q, and the clock terminal receives the system clock signal SCLK.
The data FF 22 is connected to the system clock signal S
CLK is divided by half, and a pulse signal having a period of 2t is output from the output terminal Q as shown in FIG. Note that data F
Period 2 of pulse signal output from output terminal Q of F22
t is equal to or longer than the access time when accessing the memory on the external ICE device 13 side.

The multiplexer 23 has the data FF2
2 and the system clock signal SCLK, and the mode transition signal MOD. The multiplexer 23 selects and outputs the system clock signal SCLK when the mode transition signal MOD is at the L level, and selects and outputs the output signal of the data FF 22 when the mode transition signal MOD is at the H level.

The buffer 24 supplies the output of the multiplexer 23 to the emulator interface circuit 19 as an emulator clock signal ICLK. The emulator interface circuit 19 outputs the mode transition signal M
When the OD is at the L level, only the execution history of the CPU 15 can be transmitted to the external ICE device 13 and the execution history transmission mode is set in which data cannot be input from the external ICE device 13. The emulator interface circuit 19 has a CPU
When the mode transition signal MOD of No. 15 is at the H level, an emulation mode in which a monitor program of the external ICE device 13 can be input is set. Then, the emulator interface circuit 19 performs the monitoring operation of the CPU 15 in each mode based on the emulator clock signal ICLK supplied from the emulator clock generation circuit 20.

That is, in the execution history sending mode in which the mode transition signal MOD is at the L level, the system clock S
CLK is supplied as the emulator clock signal ICLK, the emulator interface circuit 19
It operates at the same speed as PU15. Therefore, as shown in FIG.
The data signal IDATA or the status signal ISTATUS sent to the CE device 13 changes at a cycle t.

In the emulation mode in which the mode transition signal MOD is at the H level, data F having a cycle of 2t is used.
The pulse signal of F22 is the emulator clock signal ICL
Since it is supplied as K, the emulator interface circuit 19 operates at half the speed of the CPU 15. Therefore, as shown in FIG. 3, the data signal ID between the emulator interface circuit 19 and the external ICE device 13 is transmitted.
The ATA or status signal ISTATUS changes in a cycle 2t.

As described above, according to the microcomputer 10 of this embodiment, in the execution history sending mode, the emulator interface circuit 19 outputs the system clock signal SC.
Emulator clock signal ICLK having the same cycle t as LK
, The operation history of the CPU 15 can be sent out at high speed. In the emulation mode, the emulator interface circuit 19 sets the frequency of the system clock signal SCLK to one half, that is, twice the period of the system clock signal SCLK.
Since the operation is performed based on the t emulator clock signal ICLK, the memory of the external ICE device 13 can be accessed, and the CPU 15 can execute the monitor program of the external ICE device 13.

[0024]

As described in detail above, according to the present invention,
The execution history of the central processing unit can be sent to the external ICE device at high speed, and when accessing the memory of the external ICE device, there is an excellent effect that the operation can be performed at low speed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block circuit diagram showing an embodiment embodying the present invention.

FIG. 3 is a timing chart showing the operation of one embodiment.

FIG. 4 is a block circuit diagram showing a conventional example.

FIG. 5 is a timing chart showing the operation of the conventional example.

[Explanation of symbols]

 1 Central Processing Unit (CPU) 2 Emulator Interface Circuit 3 Emulator Clock Generation Circuit ICLK Emulator Clock Signal MOD Mode Transition Signal SCLK System Clock Signal

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 1/04-1/14

Claims (1)

(57) [Claims] 1. A system clock signal CPU Ru <br/> operates on the basis of, the central processing equipment based on the emulator clock signal
And emulator interface circuitry for monitoring the operation, the said emulator interface circuit emulator
Emulator clock generation time for supplying clock signal
A microcomputer and road, have been built, the emulator clock generator, Ri by said system clock signal when the mode transition signal which enables the central processing instrumentation placed et the external data input is input the emulator interface even if the frequency is low clock signal and the emulator clock signal
Is supplied to the circuit, supplied from said central processing unit to the emulator interface circuitry to the error <br/> emulator clock signal and the system clock signal when said mode transition signal is not <br/> input A microcomputer characterized in that: