JPH08292741A - Data transfer circuit and liquid crystal driving device using the circuit - Google Patents

Abstract

PURPOSE: To provide a data transfer circuit in which power consumption of a clock line, that transmits a clock, is reduced and a liquid crystal driving device employing the above circuit. CONSTITUTION: A data transfer circuit 31 generates an inverted clock signal and a clock signal from the clock signal inputted from a clock input terminal 32 by inverter circuits 34 and 36 and the signals are outputted to an inverted clock line 35 and a clock line 37. Plural flip-flop circuits 38, 39 and 40 are connected between the both clock lines in parallel and in a cascading manner. Thus, the data from the terminal 33 are successively transferred between each flip-flop circuit. Then, between the lines 35 and 37, a transfer gate 42 is provided to make the both lines shortcircuited/non-shortcircuited conditions. While the gate 42 is charged and discharged on the lines 37 and 35, both lines are shortcircuited and electric charges are moved from one line to the other so that the charges required for a charge-up can be made one half. Hence, the power consumption can be reduced to one half, too.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer circuit for sequentially transferring data to a plurality of data holding sections by using a clock and an inverted clock, and a liquid crystal drive device using the circuit.

[0002]

2. Description of the Related Art A conventional data transfer circuit is shown in FIG.
It is configured as shown in FIG. The data transfer circuit 1 of FIG. 13 has a clock input terminal 2 to which a clock signal having a constant frequency is input and a data input terminal 3.
The input clock signal is inverted by the inverter circuit 4 to generate an inverted clock signal and the inverted clock line 5
And outputs the inverted clock signal to the inverter circuit 6
The inverted clock signal is output to the clock line 7 again. A plurality of flip-flop (latch) circuits 8, 9, 10, ... For holding data are connected in parallel between the clock line 7 and the inverted clock line 5.

Further, the flip-flop circuits 8 and 9,
10, ... are connected in series so that the data signal input from the data input terminal 3 is input via the data input line 11 from the D input terminal of each flip-flop circuit and output from the Q output terminal. It is connected.

FIG. 14 is a timing chart showing the waveforms of the clock signal and the inverted clock signal supplied to the clock line 7 and the inverted clock line 5 of FIG. 13, and FIG. 15 shows the waveforms of φ1 and φ2 of FIG. It is a schematic diagram explaining the charging / discharging state of the clock line and the inversion clock line at a timing.

Therefore, in the operation of the data transfer circuit 1 of FIG. 13, the clock signal input from the clock input terminal 2 is supplied to the inverter circuit 4 and the inverter circuit 6 as shown in FIG.
Clock pulse waveform as shown in 4
And inverted clock line 5 are supplied.

For example, at the φ1 timing shown in FIG. 14, the clock signal (CLK) is at the ground level (GN).
D) Low to power supply voltage level (Vcc) High
And vice versa, the inverted clock signal (-CLK) changes from the power supply voltage level (Vcc) of High to the ground level (GND) of Low.

Therefore, at this time, the clock line 7 and the inverted clock line 5 are charged (clock line side) and discharged (inverted clock line side) as shown by φ 1 in FIG. That is, on the clock line side shown in FIG. 15, since SW1 is closed and SW2 is opened, the capacitor C1 is charged by the power supply voltage Vcc.

On the side of the inverted clock line, SW3
Opens and closes SW4, so that the electric charge accumulated in the capacitor C2 escapes to the ground side and becomes equipotential to the ground level (discharge).

Next, at the timing of φ 2 shown in FIG. 14, the clock signal (CLK) changes the power supply voltage level (Vc).
c) High to ground level (GND) Low
, And conversely, the inverted clock signal (_CLK) changes from the low level of the ground level (GND) to the power supply voltage level (V
cc) High.

Therefore, at this time, the clock line 7 and the inverted clock line 5 are discharged (clock line side) and charged (inverted clock line side) as shown by φ 2 in FIG. That is, on the clock line side shown in FIG. 15, since SW1 opens and SW2 closes, the charge accumulated in the capacitor C1 escapes to the ground side and becomes equipotential to the ground level (discharge). Further, on the inverted clock line side, SW3 is closed and SW4 is opened, so that the capacitor C2 is charged by the power supply voltage Vcc.

As described above, in the conventional data transfer circuit 1 shown in FIG. 13, charging / discharging is repeated on the clock line 7 and the inverted clock line 5, so that the data input terminal 3 in each of the flip-flop circuits 8, 9 and 10. Latch the data signal input from or output through,
While sequentially transferring data, each flip-flop circuit 8,
Output signals of O1, O2, and O3 are output from output terminals 9 and 10.

[0012]

However, in such a conventional data transfer circuit 1 as described above, the flip-flop circuits 8, 9, 10 ... Are arranged in parallel between the clock line 7 and the inverted clock line 5. It is connected. Therefore, the clock input terminal (CL
K) and the inverted clock input terminal are connected to the respective gate electrodes of the transfer gate, and serve as load capacitance.

Therefore, in the data transfer circuit, as the number of stages of the flip-flop circuit increases and the load capacity connected to the clock line increases, and when the load capacity connected to the clock line is the same, the frequency of the transfer clock is increased. There is a problem that the power consumption increases as the power consumption increases.

The reason is that when a clock pulse is passed through the clock line of the data transfer circuit, a high level voltage and a low level voltage are alternately applied to the load capacitance of the clock line. This corresponds to the repeated charging and discharging on each clock line. Therefore, an increase in the load capacity connected to the clock line leads to an increase in power consumption because the power required for charging increases and the power is consumed by discharging. Further, even if the load capacity connected to the clock line is the same, the power consumed by charging / discharging will increase in proportion to the frequency as the transfer clock frequency increases (if the frequency becomes n times, the power consumption will increase). Also n times).

Therefore, the present invention has been made in view of the above problems, and provides a data transfer circuit and a liquid crystal driving device using the circuit, which can reduce power consumption on a clock line for transmitting a clock. It is intended to be provided.

[0016]

A data transfer apparatus according to claim 1, further comprising: a transfer clock line for transferring a clock;
In a data transfer device in which a plurality of data holding units are cascaded in parallel with an inverted transfer clock line that transfers an inverted clock obtained by inverting the clock and sequentially transfers data to the data holding unit, Short-circuit / non-short-circuit switching means connected to the inverted transfer clock line and switching between short-circuiting and non-short-circuiting both clock lines; and switching control means for controlling switching timing of the short-circuit / non-short-circuiting switching means. It is characterized by having.

A data transfer device according to a second aspect of the present invention is
After the switching control means supplies the clock and the inverted clock to the data holding unit, switching is performed so that the transfer clock line and the inverted transfer clock line are short-circuited at a timing at which the clocks are inverted. After the electric charge is moved from one clock line to the other clock line, switching control is performed so that the clock lines are not short-circuited, and both clock lines are charged and discharged.

According to another aspect of the present invention, there is provided a liquid crystal drive device between a horizontal sync signal transfer line for transferring a horizontal sync signal and an inverted horizontal sync signal transfer line for transferring an inverted horizontal sync signal obtained by inverting the horizontal sync signal. In a liquid crystal drive device having a data line drive circuit that is connected in parallel in parallel and has a data holding unit that sequentially transfers data, the liquid crystal drive device is connected to the horizontal synchronization signal transfer line and the inverted horizontal synchronization signal transfer line, and both transfer lines are connected. Short-circuiting / non-short-circuiting switching means for switching between short-circuiting and non-short-circuiting, and supplying the horizontal synchronizing signal and the inverted horizontal synchronizing signal to the data holding unit, and then switching the short-circuiting / non-shorting switching means to both horizontal. The horizontal sync signal transfer line and the inverted horizontal sync signal transfer line are switched so as to be short-circuited in accordance with the inversion timing of the sync signal. After the charge to the other transmission line has moved, it switched so that the non-short-circuit, characterized by comprising a switch control means for controlling so as to perform charging and discharging of both the clock line.

According to a fourth aspect of the present invention, there is provided a liquid crystal driving device between a vertical sync signal transfer line for transferring a vertical sync signal and an inverted vertical sync signal transfer line for transferring an inverted vertical sync signal obtained by inverting the vertical sync signal. In a liquid crystal drive device having a scanning line drive circuit that is connected in parallel in parallel and has a data holding unit that sequentially transfers data, the transfer lines are connected to the vertical synchronization signal transfer line and the inverted vertical synchronization signal transfer line. Short-circuiting / non-short-circuiting switching means for switching between short-circuiting and non-short-circuiting, and after supplying the vertical synchronizing signal and the inverted vertical synchronizing signal to the data holding unit, the short-circuiting / non-short-circuiting switching means is set to both vertical Switching to short-circuit the vertical synchronization signal transfer line and the inverted vertical synchronization signal transfer line in accordance with the inversion timing of the synchronization signal,
After the electric charge is transferred from one transfer line to the other transfer line, it is switched so as not to be short-circuited, and switching control means for controlling to charge and discharge both clock lines is provided.

According to a fifth aspect of the present invention, there is provided a liquid crystal driving device, wherein a clock and a clock generating means for generating an inverted clock by inverting the clock, a transfer clock line for transferring the clock, and an inverted transfer clock for transferring the inverted clock. And a clock supply circuit for supplying a clock and an inversion clock specific to the data line drive circuit or the scanning line drive circuit of the liquid crystal display panel via the transfer clock line and the inverted transfer clock line. A short circuit / non-short circuit switching unit connected to the transfer clock line and the inverted transfer clock line, for switching between short-circuiting and non-short-circuiting of both clock lines, and the transfer clock line and the reverse transfer clock line. After supplying the clock and the inverted clock, the short circuit The non-short-circuit switching means is switched so as to short-circuit the transfer clock line and the inverted transfer clock line in accordance with the inversion timing of both clocks, and the electric charge is transferred from one clock line to the other clock line, and then the short-circuit is not short-circuited. Switching control means for controlling so as to charge and discharge both clock lines by switching so that
It is characterized by having.

[0021]

In the data transfer circuit according to the first and second aspects, the transfer clock line and the inverted transfer clock line in which a plurality of data holding units are cascaded in parallel are short-circuited /
The non-short circuit switching means switches between short circuit and non-short circuit, and the switching control means controls the switching timing. In particular, according to the present invention, after the switching control means supplies the clock and the inverted clock to the data holding unit, the transfer clock line and the inverted transfer clock line are short-circuited in accordance with the timing of inverting the both clocks, and Then, the electric charge is moved from one side to the other side, and then the non-short-circuited state is set to charge and discharge both clock lines.

Therefore, since there are two clock lines and the clock and the inverted clock are out of phase with each other by 180 degrees, when the two clocks are inverted, the transfer clock line and the inverted transfer clock line are short-circuited, By moving half of the charges charged in the load capacitance of one clock line to the load capacitance of the other clock line, the power consumption can be reduced by half.

In the liquid crystal driving device according to the third aspect, data for generating data for each drain line based on the horizontal synchronizing signal and the inverted horizontal synchronizing signal input to the data line driving circuit of the liquid crystal display device. A transfer circuit is configured, and short-circuit / non-short-circuit switching means is provided between the horizontal synchronizing signal transfer line and the inverted horizontal synchronizing signal transfer line of the data transfer circuit, and the transfer control means short-circuits or non-short-circuits both transfer lines. Control whether to switch. Therefore, the power consumed by the data transfer circuit of the data line driving circuit can be reduced by half.

According to another aspect of the present invention, there is provided a scanning line driving circuit for generating scanning data for each gate line based on the vertical synchronizing signal and the inverted vertical synchronizing signal of the liquid crystal display device. Short circuit between the vertical sync signal transfer line and the inverted vertical sync signal transfer line of the line drive circuit
Non-short-circuit switching means is provided, and switching control means controls switching between short-circuiting and non-short-circuiting of both transfer lines. Therefore, the power consumed by the scanning line driving circuit can be reduced by half.

According to another aspect of the liquid crystal drive device of the present invention, the transfer clock line for transferring the clock from the clock generating means and the inverted transfer clock line for transferring the inverted clock are supplied to the data line driving circuit or the scanning line driving circuit. In a clock supply circuit that supplies a clock, when switching between short-circuiting and non-short-circuiting the transfer clock line and the inverted transfer clock line by the short-circuit / non-short-circuit switching means, a clock is supplied to the transfer clock line and the inverted transfer clock line. After supplying the inversion clock, the transfer clock line and the inversion transfer clock line are short-circuited by the short-circuit / non-short-circuit switching means in accordance with the inversion timing of both clocks, and the charge is transferred from one clock line to the other clock line. After that, charge and discharge both clock lines as non-short circuit Controlled by the switching control means so.

Therefore, from the clock supply circuit, for example,
It is possible to halve the power consumed when supplying a clock to the scanning line driving circuit and the data line driving circuit.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a liquid crystal driving device using a data transfer circuit of the present invention will be described below with reference to the drawings. 1 to 12 are views for explaining a data transfer circuit of the present invention and a liquid crystal drive device using the same. Here, a drive circuit in which a drive circuit formed of a TFT is integrally formed on a glass substrate of a liquid crystal display panel. This is implemented as an integrated liquid crystal driving device.

(First Embodiment) First, the structure will be described. FIG. 1 shows a TFT-LCD 2 with an integrated drive circuit according to this embodiment.
It is a schematic block diagram of 1. This drive circuit integrated type TFT-L
The CD 21 forms a TFT (Thin Film Transistor) serving as a switching element for each pixel on a glass substrate in a display area of an LCD (Liquid Crystal Display), and also a drain driver (data line drive circuit) and a gate driver (scanning). A liquid crystal drive circuit including a line drive circuit) is integrally formed on the glass substrate.

As shown in FIG. 1, a TFT integrated with a drive circuit
-LCD 21 is a liquid crystal display panel (TFT-L) in which a TFT is formed for each pixel in a display area on a glass substrate 22.
CD) 23, a gate driver 24 that applies a scanning signal to the gate of each TFT of the liquid crystal display panel 23 to create a selected / non-selected state, and a display signal is applied to the TFT that is selected by the gate driver 24. A drain driver 25 for driving the liquid crystal for each pixel is provided, and a clock supply circuit 28 for supplying a horizontal synchronizing signal (XSCL) and a vertical synchronizing signal (YSCL) to the gate driver 24 and the drain driver 25. The drain driver 25 further includes a data transfer circuit 31,
It is composed of a latch circuit 26 and a driver circuit 27.

Data transfer circuit 31 in the first embodiment
Is also a part of the gate driver 24, and a plurality of flip-flop circuits for holding data are cascade-connected in parallel between the clock line and the inverted clock line. The input data is sequentially transferred to the next-stage flip-flop circuit by the clock and the inverted clock.

FIG. 2 is a diagram showing a configuration example of the data transfer circuit 31 according to the first embodiment. The data transfer circuit 31 of FIG. 2 has a clock input terminal 32 to which a clock signal having a constant frequency is input and a data input terminal 33. The input clock signal is inverted by the inverter circuit 34 to generate an inverted clock signal and output to the inverted clock line 35. Further, the inverted clock signal is inverted again by the inverter circuit 36, and the clock signal is returned to the clock line 37. Is output to. A plurality of flip-flop circuits 3 that hold data are provided between the clock line 37 and the inverted clock line 35 as in the conventional example.
.. are connected in parallel, and the data signal input from the data input terminal 33 is sequentially input from the D input terminal of the flip-flop circuit via the data input line 41 to output Q. They are connected in series so that they can be output from the terminals.

The characteristic configuration of the data transfer circuit of the present invention is, as shown in FIG. 2, a transfer which is connected to an inverted clock line 35 and a clock line 37 to bring both clock lines into a short-circuited state or a non-short-circuited state. Gate 4
2 is provided, and the transfer gate 42 is driven by a control clock (RC) and an inversion control clock (-RC). The data transfer circuit 31 of the first embodiment is further connected to the clock input terminal 32 and the clock line 37 when the transfer gate 42 is short-circuited.
The transfer gates 43 and 44 are provided to temporarily cut off the connection between the transfer clock 43 and the inversion clock line 35, and are driven by the control clock (RC) and the inversion control clock (-RC).

FIG. 3 shows the flip-flop circuit 38 of FIG.
It is a figure which shows the internal structural example of. As shown in FIG. 3, four transfer gates 51 to 54 are respectively connected in parallel to the inverted clock line 35 and the clock line 37 connected to the flip-flop circuit 38, and the flip-flop circuit is connected to the drain line. Since it is connected for a few minutes, it has a very large load capacity. Then, the transfer gates 51 and 54 are opened and closed at the same timing, and the transfer gates 52 and 53 are
The reverse opening / closing operation is performed at the same timing as the transfer gates 51 and 54. This transfer gate 5
By combining 1 to 54 and the inverter circuits 55 to 58, input data is latched by the clock signal and the inverted clock signal or is output through.

FIG. 4 is a block diagram of the transfer gate shown in FIGS. 2 and 3, and here it is composed of a CMOS type transfer gate in which a PMOS 61 and an NMOS 62 are combined. In the transfer gate 60 of FIG. 4, the gate of the PMOS 61 is Low,
When the gate of the NMOS 62 is High, the A and B terminals are in a conductive state, and conversely, the gate of the PMOS 61 is H.
When the gate of the NMOS 62 is Low at the time of high, it becomes non-conductive.

Next, the operation will be described. FIG. 5 shows a clock signal (CLK) supplied to the clock line 37 and the inverted clock line 35 of FIG.
K) and a control clock (RC) waveform for driving the transfer gates 42, 43 and 44. FIG. 6 is a clock line of the data transfer circuit 31 and an inversion at each timing of φ1 to φ4 of FIG. It is a schematic diagram explaining the charging / discharging state of a clock line.

Therefore, in the operation of the data transfer circuit 31 shown in FIG. 2, the clock signal input from the clock input terminal 32 is passed through the inverter circuits 34 and 36, so that the clock pulse waveform as shown in FIG. And the inverted clock line 35.

In the first embodiment, as shown in FIG. 2, the control clock (RC) and the inverted control clock (R
C) is applied to the gates of the transfer gates 42 to 44, respectively, so that the transfer gates 43 and 44 become non-conductive, the transfer gate 42 becomes conductive, and conversely, when the transfer gates 43 and 44 become conductive, The transfer gate 42 becomes non-conductive. This is because the clock line 37 and the inverted clock line 35 are made non-conducting with respect to the clock input terminal 32, and by short-circuiting the clock line 37 and the inverted clock line 35, half the electric charge is moved from one clock line to the other clock line. It is what makes me. Also,
When the clock line 37 and the inverted clock line 35 are brought into conduction with respect to the clock input terminal 32, the clock line 37 and the inverted clock line 35 are not short-circuited, and the normal charging / discharging operation is performed on both clock lines. .

The above operation will be described with reference to the timing charts of FIGS. 2 and 5 and the schematic diagram of FIG. First, at the timing of φ1, since the control clock (RC) is Low, the transfer gates 43 and 44 are in the conductive state, the transfer gate 42 is in the non-conductive state, the clock signal is at the potential of Vcc, and the inverted clock signal is at the GND. It is at the potential of.

Looking at this at φ 1 in FIG. 6, with the transfer gate 42 open, on the clock line 37 side, SW1 is closed and SW2 is open, so clock line 37 (corresponding to capacitor C1) Is being charged from the power supply voltage Vcc. On the side of the inversion clock line 35, SW3 is open and SW4 is closed, so that the electric charge accumulated in the inversion clock line 35 (corresponding to the capacitor C2) is discharged to the ground side and becomes the ground potential.

Next, the timing of φ2 is the timing at which the clock signal and the inverted clock signal are inverted. At this time, instead of discharging the electric charge accumulated in the clock line 37 as it is, by moving the electric charge by half to the inverted clock line 35 side, the electric charge required for charging the inverted clock line 35 side can be saved. Therefore, by changing the control clock (RC) from Low to High, the transfer gates 43, 4
4 is turned off, and the transfer gate 42 is turned on.

Looking at this at φ 2 in FIG. 6, since SW1 and SW2 on the clock line 37 side are open while the transfer gate 42 is closed, the clock line 37
The electric charge accumulated in (corresponding to the capacitor C1) flows only half through the transfer gate 42 toward the inverted clock line 35 (corresponding to the capacitor C2). Since SW3 and SW4 are open on the inverted clock line 35 side,
The inverted clock line 35 is charged about half by the electric charge flowing from the clock line 37.

Next, at the timing of φ3, since the control clock (RC) returns to Low, the transfer gates 43 and 44 are in the conductive state again, the transfer gate 42 is in the non-conductive state, and the clock signal is inverted. It becomes the GND potential, and the inverted clock signal becomes the potential of Vcc.

Looking at this at φ 3 in FIG. 6, with the transfer gate 42 open, on the clock line 37 side, SW1 is open and SW2 is closed, so the clock line 37 (corresponding to the capacitor C1). The remaining half of the electric charge stored in is discharged to the ground side and becomes the ground potential. Further, on the side of the inverted clock line 35, SW3 is closed and SW4 is opened, so that the charge is performed from the power supply voltage Vcc in addition to the electric charge that is already half accumulated in the inverted clock line 35 (corresponding to the capacitor C2). For this reason, the power required to charge the clock line 35 can be half that of the conventional one.

Next, the timing of φ4 is the timing at which the clock signal and the inverted clock signal are inverted again. At this time, instead of discharging the electric charge accumulated in the inverted clock line 35 as it is, the clock line 3
By moving the charges by half to the 7 side, the charges required for charging the clock line 37 side can be saved.
Therefore, the control clock (RC) is changed from Low to High.
To the transfer gate 43,
The transfer gate 42 is turned on while the switch 44 is turned off.

Looking at this at φ 4 in FIG. 6, since SW1 and SW2 on the clock line 37 side are open with the transfer gate 42 closed, the charge accumulated in the inverted clock line 35 (corresponding to the capacitor C2). Flows through the transfer gate 42 to the clock line 37 (corresponding to the capacitor C1) side by half. Since SW1 and SW2 are open on the clock line 37 side, the clock line 37 is charged to about half by the charge flowing from the inverted clock line 35.

As described above, the operations from φ1 to φ4 are performed in synchronization with the inversion timing of the clock signal and the inverted clock signal, and the clock line 37 and the inverted clock line 35 are changed from the charged state to the discharged state or the discharged state. When shifting from the charging state to the charging state, the clock line 37 and the inverted clock line 35 are connected to the transfer gate 42.
Short-circuiting to transfer half the charge from one to the other. For this reason, the power required to charge the clock line 37 or the inverted clock line 35 can be halved, and the power consumption can be halved.

FIG. 7 is a diagram showing signal waveforms at various parts of the data transfer circuit 31 shown in FIG. When the clock signal (CLK) and the control clock (RC) are shown in FIG.
When the data is input to the data transfer circuit 31, the waveform on the clock (CLK) line shown in FIG. 7 is obtained by the above-described operation. This waveform has L (Low) level and H (High)
h) level is not two levels, but M (Me
level). This is because the charge accumulated in the clock line or the inverted clock line is half of the charge moved to the other clock line due to the short circuit of the transfer gate 42, and the potential rises by half, and the remaining half rises in potential. Is due to charging from the power supply potential VCC. Thus, it can be seen that the power required for charging is half that of the conventional one.

Further, the clock (CLK) shown in FIG.
A flip-flop circuit 38 based on the waveform on the line,
39, 40, ... Are driven and input data D1,
The operation of latching D2 and D3 or outputting them through is sequentially repeated. As a result, the output signals O1, O2, O3, ... From the connecting portions of the adjacent flip-flop circuits 38, 39, 40 ,.
As indicated by 1 and O2, the input data is output with a sequential delay. This data transfer circuit 31 is similar to that of the first embodiment shown in FIG.
1 corresponds to the data transfer circuit 31 of the drain driver 25, and its output signal becomes a latch signal when the image data is latched by the latch circuit 26 at the next stage according to each drain line position.

In the first embodiment, the drain driver of the liquid crystal display device has been described as an example, but the gate driver 24 shown in FIG. 1 also has a data transfer circuit similar to that shown in FIG. A scan signal for sequentially selecting scan lines is generated. Therefore, the power consumption can be reduced to half for the same reason as the data transfer circuit 31 of the drain driver described above.

(Second Embodiment) Next, FIGS. 8 to 12 are diagrams showing a configuration example of the clock supply circuit 28 of FIG.
In each of the circuit diagrams of FIGS. 8 to 12, the terminal numbers indicated by are mutually connected to form one clock supply circuit 28.

In the second embodiment, even if the structure of the data transfer circuit of the drain driver and the gate driver of the liquid crystal driving device is the same as that of the conventional example, the same power consumption reduction effect as that of the first embodiment can be obtained. It is something to do. Specifically, a clock supply circuit 2 that supplies a horizontal synchronization signal (XSCL), a vertical synchronization signal (YSCL), and the like to a drain driver and a gate driver of a liquid crystal drive device including a data transfer circuit.
A circuit for short-circuiting the clock line and the inverted clock line in synchronization with the inversion timing of the clock signal to move half the electric charge from one side to the other side is provided on the 8 side.

The circuit shown in FIG. 8 is composed of a crystal oscillator 71, a load resistor 73, or a plurality of inverter circuits 73, 74 using CMOS or the like. The circuit of FIG. 8 has a load resistor 72 connected in parallel from a crystal oscillator 71.
A clock pulse of a predetermined frequency is output from the inverter circuit 73 via the, and the clock is inverted by the inverter circuit 74 and output to the terminal of.

The circuit shown in FIG. 9 includes an inverter circuit 81,
83, 84, 86, 88, a flip-flop circuit 82,
It is composed of 85, 87 and the like. The circuit of FIG. 9 corresponds to that of FIG.
The clock pulse output from the inverter circuit 74 is inverted by the inverter circuit 81 of FIG. 9, input to the inverted clock terminal (_CLK) of the flip-flop circuit 82, and output to the terminal. Further, the output clock of the inverter circuit 81 is inverted again by the inverter circuit 83 and input to the clock terminal (CLK) of the flip-flop circuit 82. The output signal output from the Q terminal of the flip-flop circuit 82 is inverted by the inverter circuit 84, input to the D terminal of the flip-flop circuit 82, and the inverted clock terminal of the next-stage flip-flop circuit 85. It is input to (_CLK).

The clock terminal (CLK) of the flip-flop circuit 85 has the flip-flop circuit 82.
The output signal from the Q terminal of is input. The output signal output from the Q terminal of the flip-flop circuit 85 is inverted by the inverter circuit 86, input to the D terminal of the flip-flop circuit 85, and the inverted clock terminal of the next-stage flip-flop circuit 87. (￣ CL
K).

Further, the flip-flop circuit 85 is connected to the clock terminal (CLK) of the flip-flop circuit 87.
The output signal from the Q terminal of is input. The output signal output from the Q terminal of the flip-flop circuit 87 is output to the terminal of and the inverter circuit 8
After being inverted at 8, it is input to the D terminal of the flip-flop circuit 85. In this way, the circuit of FIG. 9 constitutes a frequency dividing circuit for generating a clock having a cycle of an integral multiple based on the basic clock pulse generated by the circuit of FIG.

The circuit shown in FIG. 10 includes a flip-flop circuit 91 and an exclusive OR circuit (EX-OR) 9.
2, an inverter circuit 93 and the like. Figure 10
In the circuit of FIG. 8, the basic clock pulse of the output of the circuit of FIG. 8 is input to the clock terminal (CLK) of the flip-flop circuit 91, and the inverted basic clock pulse of the output of the circuit of FIG. 9 is the inverted clock terminal (-CLK). Entered in
The divided clock of the output of the circuit of FIG. 9 is input to the D terminal of the flip-flop circuit.

In the exclusive OR circuit 92, the signal output from the Q terminal of the flip-flop circuit 91 and the divided clock of the output of the circuit of FIG. 9 are input to the input side, and only one of them is input. "H (Hig
When "h)" is input, "H" is output. Further, the output of the exclusive OR circuit 92 is output to the same terminal as it is, and the output which is inverted via the inverter circuit 93 is output from the terminal of.

The circuit shown in FIG. 11 is composed of a flip-flop circuit 101. In the circuit of FIG. 11, the basic clock pulse output from the circuit of FIG. 8 is input to the inverted clock terminal (_CLK) of the flip-flop circuit 101,
The inverted basic clock pulse of the output of the circuit of FIG. 9 is input to the clock terminal (CLK), and the divided clock of the output of the circuit of FIG. 9 is input to the D terminal of the flip-flop circuit. The output signal output from the Q terminal of the flip-flop circuit 101 is output to the terminal.

The circuit shown in FIG. 12 is a characteristic component of the second embodiment, and includes inverter circuits 111 and 112.
The transfer gates 113, 114, 115 and the like are included. The circuit shown in FIG. 12 has clock line 1
1, a horizontal synchronizing signal (XSCL) is supplied to the data transfer circuit 31 of the drain driver 25 shown in FIG. 1 or a vertical synchronizing signal (YSCL) is supplied to the gate driver 24, and an inverted clock line 117 is used. Then, the inverted horizontal synchronizing signal (_XSCL) is supplied to the data transfer circuit 31 of the drain driver 25, or the inverted vertical synchronizing signal (_YSCL) is supplied to the gate driver 24.

In the circuit of FIG. 12, the output of the circuit of FIG. 11 is inverted by the inverter circuit 111 and output from the inverted clock line 117 to the inverted clock terminal 119. The output of the inverter circuit 111 is further inverted again by the inverter circuit 112 and output from the clock line 116 to the clock terminal 118.

A transfer gate 113 is provided on the clock line 116, a transfer gate 114 is provided on the inverted clock line 117, and a transfer gate is provided between the clock line 116 and the inverted clock line 117. 115 is provided.

These transfer gates 113, 1
14, 115 are driven simultaneously by the output of the circuit of FIG. 10 and its inverted output, and clock line 1
When 16 and the inverted clock line 117 are made non-conductive, both clock lines are short-circuited, and when the clock line 116 and the inverted clock line 117 are made conductive, both clock lines are non-short-circuited. With this configuration, as shown in FIG. 2 of the first embodiment, the clock line 37 and the inverted clock line 35 are made conductive / non-conductive in the data transfer circuit 31 of the drain driver, or both clocks are made conductive. It is not necessary to provide transfer gates 42, 43, 44, etc. for short-circuiting the lines. For example, even in the conventional data transfer circuit 1 shown in FIG. 13, the half effect of power consumption can be obtained as in the first embodiment. The advantage is that

Similarly, by adopting the circuits shown in FIGS. 8 to 12 on the clock supply circuit 28 side for supplying the clock to the gate driver, no change is made to the circuit on the gate driver side. However, there is an advantage that the power consumption can be reduced by half.

As described above, the liquid crystal driving device using the clock supply circuit 28 of the second embodiment can reduce the power consumption even if the existing drain driver or gate driver is used. The power consumption of the conventional liquid crystal display device can be saved. In particular, in the case of a liquid crystal drive device integrated with a drive circuit, since the liquid crystal display panel and the driver circuit are integrated, it is difficult to change the circuit configuration. Therefore, the configuration of the second embodiment is very effective. Is.

In this embodiment, the drive circuit integrated type liquid crystal drive device has been described as an example, but the present invention is not limited to this.
Further, the present invention is not limited to the TFT-LCD and can be applied to various liquid crystal display devices.

[0066]

According to the data transfer circuit of the first and second aspects, the transfer clock line and the inverted transfer clock line in which a plurality of data holding units are cascaded in parallel are short-circuited / non-short-circuited switching means. Switching between short-circuiting and non-short-circuiting, and the switching control means controls the switching timing. In particular, according to the present invention, after the switching control means supplies the clock and the inverted clock to the data holding unit, the transfer clock line and the inverted transfer clock line are short-circuited in accordance with the timing of inverting the both clocks, and Then, the electric charge is moved from one side to the other side, and then the non-short-circuited state is set to charge and discharge both clock lines.

Therefore, since there are two clock lines and the clock and the inverted clock are out of phase with each other by 180 degrees, the transfer clock line and the inverted transfer clock line are short-circuited when both clocks are inverted. By moving half of the charges charged in the load capacitance of one clock line to the load capacitance of the other clock line, the power consumption can be reduced by half.

According to the liquid crystal driving device of the third aspect, data for generating data for each drain line based on the horizontal synchronizing signal and the inverted horizontal synchronizing signal input to the drain driver of the liquid crystal display device. Configure the transfer circuit,
Short-circuit / non-short-circuit switching means is provided between the horizontal synchronizing signal transfer line and the inverted horizontal synchronizing signal transfer line of the data transfer circuit, and the switching control means controls switching between short-circuiting and non-short-circuiting of both transfer lines. . Therefore, the power consumed by the data transfer circuit of the drain driver can be halved.

According to the liquid crystal driving device of the fourth aspect, a gate driver for generating scan data for each gate line is constructed based on the vertical synchronizing signal and the inverted vertical synchronizing signal of the liquid crystal display device, and the gate driver is constructed. Short-circuit / non-short-circuit switching means is provided between the vertical synchronizing signal transfer line and the inverted vertical synchronizing signal transfer line of the driver, and switching control means controls switching between short-circuiting and non-short-circuiting. Therefore, the power consumed by the gate driver can be halved.

According to the liquid crystal drive device of the fifth aspect, the transfer clock line for transferring the clock from the clock generating means and the inverted transfer clock line for transferring the inverted clock supply the clock and the inverted clock to the drain driver or the gate driver. In the clock supply circuit for supplying, when switching between short-circuiting and non-short-circuiting the transfer clock line and the inverted transfer clock line by the short-circuit / non-short-circuit switching means, the clock and the inverted clock are set to the transfer clock line and the inverted transfer clock line. After the supply of and, the transfer clock line and the inverted transfer clock line are short-circuited by the short-circuit / non-short-circuit switching means in accordance with the inversion timing of both clocks, and the charge is transferred from one clock line to the other clock line, Charge both clock lines as non-short circuit Controlled by the switching control means so as to. Therefore, it is possible to halve the power consumed when the clock is supplied from the clock supply circuit to the gate driver and the drain driver, for example.

[Brief description of drawings]

FIG. 1 is a TFT-LCD integrated with a drive circuit according to this embodiment.
FIG.

FIG. 2 is a diagram showing a configuration example of a data transfer circuit according to the first embodiment.

FIG. 3 is a diagram showing an internal configuration example of a flip-flop circuit in FIG.

FIG. 4 is a configuration diagram of the transfer gate shown in FIGS. 2 and 3.

5 is a timing chart showing waveforms of a clock signal supplied to the clock line and the inverted clock line of FIG. 2, an inverted clock signal, and a control clock for driving the transfer gate.

6 is a schematic diagram for explaining charge / discharge states of a clock line and an inverted clock line of the data transfer circuit at each timing of φ1 to φ4 in FIG.

FIG. 7 is a diagram showing signal waveforms of respective parts of the data transfer circuit of FIG.

8 is a diagram showing a configuration example of the clock supply circuit of FIG.

9 is a diagram showing a configuration example of the clock supply circuit of FIG.

10 is a diagram showing a configuration example of the clock supply circuit of FIG.

11 is a diagram showing a configuration example of the clock supply circuit of FIG.

12 is a diagram showing a configuration example of the clock supply circuit of FIG.

FIG. 13 is a configuration diagram of a conventional data transfer circuit.

14 is a timing chart showing waveforms of a clock signal and an inverted clock signal supplied to the clock line and the inverted clock line of FIG.

15 is a schematic diagram for explaining charge / discharge states of the clock line and the inverted clock line at the timings of φ1 and φ2 in FIG.

[Explanation of symbols]

 21 integrated drive circuit TFT-LCD 22 glass substrate 23 liquid crystal display panel (TFT-LCD) 24 gate driver 25 drain driver 26 latch circuit 27 driver circuit 28 clock supply circuit 31 data transfer circuit 32 clock input terminal 33 data input terminal 34, 36 Inverter circuit 35 Clock line 37 Inverted clock line 38, 39, 40 Flip-flop circuit 42, 43, 44 Transfer gate

Claims (5)

[Claims] 1. A plurality of data holding units are cascaded in parallel between a transfer clock line for transferring a clock and an inverted transfer clock line for transferring an inverted clock obtained by inverting the clock, and data is stored in the data holding unit. In the data transfer circuit for sequentially transferring the data, the short circuit / non-short circuit switching unit that is connected to the transfer clock line and the inverted transfer clock line and switches between short-circuiting and non-short-circuiting both clock lines; A data transfer circuit comprising: a switching control unit that controls a switching timing of the short-circuit switching unit. 2. The switching control means supplies the clock and the inverted clock to the data holding unit, and then the transfer clock line and the inverted transfer clock line are synchronized with each other at a timing at which both clocks are inverted. 2. The charging / discharging of both clock lines is performed by switching so as to short-circuit, moving the charge from one side to the other between the clock lines, and then performing switching control so that the clock lines are not short-circuited. Data transfer circuit. 3. A horizontal synchronization signal transfer line for transferring a horizontal synchronization signal and an inverted horizontal synchronization signal transfer line for transferring an inverted horizontal synchronization signal, which is an inverted version of the horizontal synchronization signal, are cascade-connected in parallel to transfer data. A liquid crystal driving device having a data line driving circuit having a data holding unit for sequentially transferring, wherein the transfer lines are connected to the horizontal synchronizing signal transfer line and the inverted horizontal synchronizing signal transfer line, and both transfer lines are short-circuited or non-short-circuited. Short-circuit / non-short-circuit switching means, and after supplying the horizontal synchronizing signal and the inverted horizontal synchronizing signal to the data holding unit, the short-circuit / non-short-circuit switching means is adjusted to the inversion timing of both horizontal synchronizing signals. The horizontal sync signal transfer line and the inverted horizontal sync signal transfer line are switched so as to be short-circuited, and charges are transferred from one transfer line to the other transfer line. After, the liquid crystal driving apparatus having a data line driving circuit comprising: the switching control means for controlling both the clock line is switched to a non-short-circuit to charge and discharge, the. 4. A vertical synchronization signal transfer line for transferring a vertical synchronization signal and an inverted vertical synchronization signal transfer line for transferring an inverted vertical synchronization signal, which is an inverted version of the vertical synchronization signal, are cascade-connected in parallel to transfer data. A liquid crystal driving device having a scanning line driving circuit having a data holding section for sequentially transferring, wherein the vertical synchronizing signal transfer line and the inverted vertical synchronizing signal transfer line are connected, and both transfer lines are short-circuited or non-short-circuited. Short-circuiting / non-short-circuiting switching means, and after supplying the vertical synchronizing signal and the inverted vertical synchronizing signal to the data holding unit, the short-circuiting / non-shorting switching means is adjusted to the inversion timing of both vertical synchronizing signals. The vertical sync signal transfer line and the inverted vertical sync signal transfer line are switched so as to be short-circuited, and the charge is transferred from one transfer line to the other transfer line. After, the liquid crystal driving apparatus having a scanning line driving circuit comprising: the switching control means for controlling both the clock line is switched to a non-short-circuit to charge and discharge, the. 5. A clock generation means for generating a clock and an inverted clock obtained by inverting the clock, a transfer clock line for transferring the clock, and an inverted transfer clock line for transferring the inverted clock. In a liquid crystal drive device having a clock supply circuit for supplying a clock and an inversion clock specific to a data line drive circuit or a scanning line drive circuit of a liquid crystal display panel via a clock line and an inverted transfer clock line, the transfer clock line and the inverted clock Short-circuit / non-short-circuit switching means connected to the inverted transfer clock line and switching between short-circuiting and non-short-circuiting both clock lines; and the transfer clock line and the inverted transfer clock line with the clock and the inverted clock. After supplying, switch the short circuit / non-short circuit switching means to both The transfer clock line and the inverted transfer clock line are switched so as to be short-circuited in accordance with the inversion timing of the clock, and the charges are transferred from one clock line to the other clock line, and then switched so as not to be short-circuited. A liquid crystal drive device having a clock supply circuit, comprising: a switching control means for controlling charging and discharging of both clock lines.