JPH08288477A - Nonvolatile memory element and its preparation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the substrate damage in a peripheral circuit region and a boundary region and to improve the insulation characteristics between devices by forming a dummy conductive pattern on a field oxide film being formed between the peripheral circuit region and a cell array region. SOLUTION: A first field oxide film 24 for limiting a cell array region and a peripheral circuit region and a second field oxide film 25 for limiting the cell array region in each cell unit are formed on a semiconductor substrate 22. Especially, a dummy conductive pattern 34c is formed on the first field oxide film 24, and a groove A is formed on the first field oxide film 24 being lined up with one side surface of the dummy conductive pattern 34c. Also, a peripheral circuit device 34d and an etching prevention 36d are laminated in the peripheral circuit region, thus reducing the damage in the first field oxide film 24 and the substrate 22 of the peripheral circuit region and improving the insulation characteristics between devices.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having a dummy conductive pattern formed on a field oxide film between a cell array region and a peripheral circuit region and its manufacture. Regarding the method.

[0002]

2. Description of the Related Art A flash EEPROM has a floating gate for storing data and a control gate for controlling the floating gate so that a high voltage signal can be applied to the control gate or pocket wale to program or erase data. It has the characteristics that

A technique for such a flash EEPROM is disclosed in R. Shirota et al. Laid on page 103 to page 106 of IEDM in 1990, "2.3 μm2 memory cell structure for 16 megabit NAND EEPROM (A 2.
3μm 2 memory Cell Structure for 16Mb NAND EEPR
OMs) ". When manufacturing a flash EEPROM, a self-alignment process of simultaneously etching materials stacked in multiple layers to form a control gate and a floating gate is required.

1 to 3 are cross-sectional views illustrating a general manufacturing method for a non-volatile memory device, in particular, the self-alignment process. First, the field oxide film 4 is formed on the surface of the semiconductor substrate 2, the thin oxide film 6 is formed in the active region, and then the material 8 for forming the floating gate is formed.
And the insulating film 10 is laminated. Then, the floating gate forming material and the insulating film are etched using a mask pattern (not shown) for forming the floating gate, and then the control gate forming material 12 is deposited on the entire surface of the resultant substrate. Then, a first photoresist pattern 16 is formed to cover the gate electrode and the cell array region in the peripheral circuit region (FIG. 1).

An etching process using the first photoresist pattern 16 is performed to form a control gate pattern 12a in the cell array region and a gate electrode 12b in the peripheral circuit region. Next, a second region covering the peripheral circuit region and the region where the control gates are formed in the cell array region is formed.
A photosensitive film pattern 17 is formed (FIG. 2). Then, by using the second photoresist layer pattern 17 for forming the control gate as an etching mask, a stacking material and the like are simultaneously etched (self-alignment process) to form the floating gate 8a,
A cell including the insulating film 10 and the control gate 12c is formed in the cell array region (FIG. 3).

While the distance between cells is gradually narrowed due to an increase in the degree of integration of memory devices, the thickness of layers stacked on a semiconductor substrate (floating gate forming material, insulating film, control gate forming material, and (2) The thickness of the photoresist pattern does not change, so during the self-alignment process (process of FIGS. 2 and 3), the aspect ratio (Aspect Ratio:
As a result, the height / width is increased.

For example, although the distance between cells (member number A in FIG. 2) is reduced to about 0.5 μm due to the increase in the degree of integration, the height of the cell pattern is the floating gate, the control gate, and the second photosensitive layer. Since the total height of the film pattern is about 1.5 μm, the aspect ratio between the cells during the self-alignment process is about 3.0, which is considerably high. The thickness of the floating gate is usually 1000Å ~ 2000
It is about Å and the thickness of the control gate is 3000 Å
The thickness of the second photosensitive film pattern is 10,000Å
It's about.

If the aspect ratio between the patterns is large, the flow of the etching liquid flowing between the patterns becomes unstable and the shapes of the patterns become non-uniform. FIGS. 4 to 7 are cross-sectional views illustrating another general manufacturing method for a non-volatile memory device, which is proposed to solve the problems described above with reference to FIGS. It was done.

After applying the insulating material layer on the control gate forming material, the first photoresist pattern 16 as described with reference to FIG. 1 is formed. Then, an etching process using the first photoresist layer pattern 16 is performed to etch a material or the like stacked on the semiconductor substrate to form a gate electrode 12b in the peripheral circuit region and a control gate of the cell array region. A pattern 12a for forming is formed (FIG. 4). At this time, insulating material patterns 15a and 15b are respectively formed on the pattern 12a for forming the control gate and the gate electrode 12b.

Next, the second photoresist layer pattern 17 as described with reference to FIG. 2 is formed on the resultant substrate having the insulator layer patterns 15a and 15b, and the photoresist layer 17 is used as an etching mask. Pattern 15
A control gate pattern 15c is formed by performing an anisotropic etching process using a and 15b as an etching target (FIG. 5). Then, the second photoresist pattern 17 is removed (FIG. 6).

Anisotropic etching is performed using the control gate pattern 15c as an etching mask to perform floating etching on the cell region, the floating gate 8a, the insulating film 10 and the control gate 1.
A cell composed of 2c is formed (FIG. 7). According to the other general manufacturing method described above, the insulating material patterns 15a, 1
Since the self-alignment process is performed by using 5b as an etching mask, the height-to-width ratio of the second photoresist pattern 17 can be reduced. This has the effect of reducing the non-uniformity of the pattern generated by the non-uniform flow of the etching liquid between the patterns.

However, as shown in FIG. 7, since serious substrate damage D is induced in the peripheral circuit region and the boundary region, the reliability of the memory device is deteriorated.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-volatile memory device that minimizes substrate damage in the peripheral circuit region and the boundary region and improves the insulation characteristics between devices. Another object of the present invention is to provide a manufacturing method suitable for manufacturing the memory device.

[0014]

To achieve the above object, a non-volatile memory device according to the present invention is formed in a memory cell formed in a cell array region and in a peripheral circuit region located around the cell array region. A peripheral circuit element, a field oxide film formed between the cell array region and the peripheral circuit region, and on the field oxide film,
The present invention is characterized by including a dummy conductive pattern formed long according to the field oxide film.

In the nonvolatile memory device according to the present invention, it is preferable that a groove parallel to the dummy conductive pattern and aligned with one side surface of the dummy conductive pattern is further formed in the field oxide film. In the nonvolatile memory device according to the present invention, the dummy conductive pattern may be electrically connected to any one of a ground electrode and a power electrode.

In the non-volatile memory device according to the present invention, it is preferable that the dummy conductive pattern is made of the same material as that of the control gate of the memory cell. More preferably, the dummy pattern is made of any one of polycrystal silicon and polycide in which polycrystal silicon and silicide are laminated.

A method of manufacturing a non-volatile memory device according to another aspect of the present invention, which achieves the above-described other object, is characterized in that a first field oxide film that defines a cell array region and a peripheral circuit region and the cell array region is limited to a unit memory cell region. A second step of forming a second field oxide film on the semiconductor substrate, a second step of forming a first insulating film on the exposed semiconductor substrate between the first and second field oxide films, and A third step of sequentially forming a first conductive layer and a second insulating layer on the resultant substrate having one insulating layer, and a floating gate on the resulting substrate having the first conductive layer and the second insulating layer. A fourth step of forming a first photoresist layer pattern for forming a layer, a fifth step of etching a material stacked on the first insulating layer using the first photoresist layer pattern, and a fifth step of etching the material. 1 photosensitive film A sixth step of removing turns, a seventh step of sequentially forming a second conductive layer and an etching prevention layer on the resultant substrate, and a part of a first field oxide film on the etching prevention layer. And an eighth step of forming a second photoresist pattern covering the peripheral circuit region and a third photoresist pattern for forming a control gate, and using the second and third photoresist patterns to form the etching prevention layer. A ninth step of patterning, a tenth step of removing the second and third photoresist patterns, and an eleventh step of patterning a material stacked on the semiconductor substrate by using the patterned etching prevention layer. And a device forming a fourth photosensitive film pattern and a peripheral circuit region on the resultant product, the fourth photosensitive film pattern covering the cell array region and a part of the first field oxide film covered by the second photosensitive film pattern. of Fifth for adult
12 steps of forming a photoresist layer pattern, and patterning a material stacked on a semiconductor substrate using the fourth and fifth photoresist layer patterns, thereby forming a peripheral circuit device in the peripheral circuit region and a first field. A thirteenth step of forming a dummy conductive pattern on the oxide film is included.

In the nonvolatile memory device according to the present invention, the first insulating film is preferably formed by growing an oxide film with a thickness of about 100Å. In the non-volatile memory device according to the present invention, the first conductive layer is formed by depositing polycrystalline silicon to a thickness of about 1000Å to 2000Å, and the second conductive layer is formed of polycrystalline silicon and silicide on the polycrystalline silicon. It is preferable that any one of the laminated polycides is vapor-deposited to a thickness of about 2000Å to 3000Å.

The second insulating film is preferably formed by stacking an oxide film / nitride film / oxide film. In the method of manufacturing a non-volatile memory device according to the present invention, the etching prevention layer is formed of a material having a large etching selection ratio with respect to a material forming the first and second conductive layers with respect to a predetermined etching. Is desirable. More preferably, the etching prevention layer is formed of one of an oxide film and a nitride film, and is formed by a chemical vapor deposition method.

Therefore, according to the non-volatile memory device and the method of manufacturing the same according to the present invention, the insulation characteristic between the devices can be improved.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 8, member number 22 is a semiconductor substrate, 24 is a first field oxide film, 25 is a second field oxide film, 26 is a first insulating film, and 28a is a floating gate. , 30 is a second insulating film, and 34a
Is a control gate, 34c is a dummy conductive pattern, 34d is a peripheral circuit element, 36a is a first etching prevention layer pattern, 36c is a third etching prevention layer pattern, and 36c is a third etching prevention layer pattern.
d shows the 4th etching prevention layer pattern.

A first field oxide film 24 defining a cell array region and a peripheral circuit region and a second field oxide film 25 defining a cell array region for each cell unit are formed on the semiconductor substrate 22, and the field oxide film 2 is formed.
A first insulating film 26 is formed on the semiconductor substrate between 4 and 25. A first insulating film 26, a floating gate 28a, a second insulating film 30, and a control gate 34a are stacked in the cell array region to form each cell, and a first etching prevention layer pattern 36a is formed on the control gate 34a of each cell. Has been formed. First field oxide film 24
A dummy conductive pattern 34c is formed on the dummy conductive pattern 34c and is aligned with one side surface of the dummy conductive pattern 34c.
A groove A is formed in the field oxide film 24, and a third etching prevention layer pattern 36c is formed on the dummy conductive pattern 34c. In addition, in the peripheral circuit region, the peripheral circuit element 34d and the fourth etching prevention layer pattern 36d are formed.
Are stacked.

At this time, the dummy conductive pattern 34c is connected to a ground electrode or a power supply electrode (Vcc) (not shown). Referring to FIG. 4, a process of forming a first photoresist layer pattern 32 for forming a floating gate is shown, which is performed on the surface of the semiconductor substrate 22.
For example, a first field oxide film 24 that limits the cell array region and the peripheral circuit region and a second field oxide film 25 that limits the cell array region to each cell unit are formed using a normal LOCOS (Local Oxidation of Silicon) method. 1 step, the first and second field oxide films 24 and 25
In the second step, for example, growing an oxide film to form a first insulating film on the exposed semiconductor substrate 22 between, the entire surface of the resultant substrate having the first insulating film 26, such as polycrystalline silicon. The third step of forming a first conductive layer 28 by depositing a conductive material having a thickness of about 1000Å to 2000Å, for example, an oxide film / nitride film / oxide film laminated on the first conductive layer 28. A fourth step of forming the second insulating layer 30 is to form a first photoresist pattern 32 for forming a floating gate by applying a photosensitive material such as photoresist on the resultant substrate and then developing the photoresist. The process is performed in a fifth step and a sixth step of performing an anisotropic etching process using a material stacked on the semiconductor substrate 22 as an etching target using the first photoresist pattern 32 as an etching mask.

At this time, as another embodiment, the second insulating film 3
The fourth step of forming 0 may be performed after the sixth step of etching the material stacked on the semiconductor substrate 22. That is, the step of forming the second insulating film 30 can be performed by applying various other methods. FIG. 10 shows a step of forming a second conductive layer 34, an etching preventive layer 36, a second photosensitive film pattern 38 and a third photosensitive film pattern 39, wherein the first photosensitive film pattern (32 in FIG. 4) is formed. ) Is removed, a second step of stacking a second conductive layer 34 and an etching preventive layer 36 on the entire surface of the structure obtained from the removal of the first photoresist film pattern is performed. Second step of applying such a photosensitive material to a thickness of about 1.0 μm, and developing the photosensitive material to cover a part of the first field oxide film 24 and the peripheral circuit region and a second photosensitive film pattern 38 and a control gate. The third step of forming the third photosensitive film pattern 39 for forming the pattern is performed.

At this time, the second conductive layer 34 is, for example, 2
It is formed by depositing polycide having a thickness of about 000Å to 3000Å or polycide in which polycrystal silicon and silicide are laminated, and the etching prevention layer 36 is formed on the first and second conductive layers by a predetermined etching process. A material having a high etching selection ratio with respect to the material forming the element, for example, an oxide film or a nitride film is formed by a chemical vapor deposition method.

In FIG. 11, the second and third photoresist patterns 38 and 39 are used as an etching mask, and an anisotropic etching process is performed using the etching prevention layer (36 in FIG. 10) as an etching target. A first etching prevention layer pattern 36a and a second etching prevention layer pattern 36b are formed. In FIG. 12, the first and second etching prevention layer patterns 36a and 36b are used as an etching mask, and an anisotropic etching process is performed using a material stacked on a semiconductor substrate as an etching target. First insulating film 26, floating gate 28a, second
Each cell including the insulating film 30 and the control gate 34a is formed, and a conductive pattern 34 covering a part of the first field oxide film 24 and the peripheral circuit region is formed in the peripheral circuit region.
It proceeds in the step of forming b.

At this time, since the thickness of the material layer laminated in the cell array region and the thickness of the material layer laminated in the peripheral circuit region are different from each other, it is different from the second photosensitive film pattern (member number 38 in FIG. 11). A groove A is formed on the surface of the first field oxide film 24 between the third photoresist pattern (member number 39 in FIG. 11). Referring to FIG. 13, a photosensitive material, such as a photoresist, is applied to the entire surface of the resultant substrate on which the unit cells are formed, and then the photosensitive material is developed to partially remove the first field oxide film 24. And, a fourth photoresist pattern 40 covering the entire cell array region and a fifth photoresist pattern 41 for forming peripheral circuit elements are formed.

At this time, the fourth photosensitive film pattern 40 is
The area protected by the fourth photoresist pattern 40 should be formed so as to partially overlap the area protected by the second photoresist pattern 38. That is, the fourth photoresist pattern 40 is formed to protect a part of the second etching prevention layer pattern 36b. FIG. 14 shows a step of forming a dummy conductive pattern 34c and a peripheral circuit element 34d, which are stacked on a semiconductor substrate using the fourth and fifth photosensitive film patterns 40 and 41 as an etching mask. An anisotropic etching process using a material as an etching target is performed to form a peripheral circuit element 34 having the same shape as the dummy conductive pattern 34c and the fifth photosensitive film pattern (member number 41 in FIG. 13).
It progresses in the step of forming d.

[0029]

Therefore, according to the non-volatile memory device and the method of manufacturing the same of the present invention, the dummy conductive pattern is formed on the first field oxide film formed between the peripheral circuit region and the cell array region. In addition, the damage of the first field oxide film and the substrate in the peripheral circuit region can be reduced to improve the insulation characteristics between the devices.

The present invention is not limited to the above embodiments, and it is obvious that many modifications can be made by a person having ordinary skill in the art within the technical idea of the present invention.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a general manufacturing method for a nonvolatile memory device.

FIG. 2 is a cross-sectional view illustrating a general manufacturing method for a nonvolatile memory device.

FIG. 3 is a cross-sectional view illustrating a general manufacturing method for a nonvolatile memory device.

FIG. 4 is a cross-sectional view illustrating another general manufacturing method for a nonvolatile memory device.

FIG. 5 is a cross-sectional view illustrating another general manufacturing method for a nonvolatile memory device.

FIG. 6 is a cross-sectional view illustrating another general manufacturing method for a nonvolatile memory device.

FIG. 7 is a cross-sectional view illustrating another general manufacturing method for a nonvolatile memory device.

FIG. 8 is a cross-sectional view of a non-volatile memory device manufactured according to the present invention.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

FIG. 12 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

FIG. 13 is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory device according to the present invention.

FIG. 14 is a cross-sectional view illustrating the method of manufacturing the nonvolatile memory device according to the present invention.

[Description of Reference Signs] 22 semiconductor substrate 24 first field oxide film 25 second field oxide film 26 first insulating film 28a floating gate 30 second insulating film 34a control gate 34c dummy conductive pattern 34d peripheral circuit element 36a first etching prevention layer Pattern 36b second anti-etching layer pattern 36c third anti-etching layer pattern 36d fourth anti-etching layer pattern 32 first photosensitive film pattern 38 second photosensitive film pattern 39 third photosensitive film pattern 40 fourth photosensitive film pattern 41 fifth photosensitive Membrane pattern

Claims (12)

[Claims] 1. A memory cell formed in a cell array region, a peripheral circuit element formed in a peripheral circuit region located around the cell array region, and a field formed between the cell array region and the peripheral circuit region. A non-volatile memory device comprising: an oxide film; and a dummy conductive pattern formed on the field oxide film so as to extend along the field oxide film. 2. The parallel to the dummy conductive pattern,
The non-volatile memory device of claim 1, further comprising a groove formed in the field oxide layer, the groove being aligned with one side surface of the dummy conductive pattern. 3. The non-volatile memory device of claim 1, wherein the dummy conductive pattern is electrically connected to one of a ground electrode and a power electrode. 4. The non-volatile memory device of claim 1, wherein the dummy conductive pattern is made of the same material as a material forming a control gate of the memory cell. 5. The non-volatile memory device of claim 4, wherein the material is one of polycrystalline silicon and polycide in which polycrystalline silicon and silicide are stacked. 6. A first step of forming, on a semiconductor substrate, a first field oxide film that limits a semiconductor substrate to the cell array region and the peripheral circuit region and a second field oxide film that limits the cell array region to a unit memory cell region. A second step of forming a first insulating layer on the exposed semiconductor substrate between the first and second field oxide layers, a first conductive layer on the resultant substrate having the first insulating layer, and A third step of sequentially forming a second insulating layer, and a fourth step of forming a first photoresist pattern for forming a floating gate on a resultant substrate having the first conductive layer and the second insulating layer. A fifth step of etching a material stacked on the first insulating layer using the first photoresist layer pattern, and a sixth step of removing the first photoresist layer pattern; On the substrate of the thing A seventh step of sequentially forming a second conductive layer and an etching prevention layer, and forming a second photoresist pattern and a control gate on the etching prevention layer to cover a part of the first field oxide layer and a peripheral circuit region. Eighth Forming Third Photosensitive Film Pattern
A ninth step of patterning the etching prevention layer using the second and third photoresist patterns, a tenth step of removing the second and third photoresist patterns, and the patterned etch An eleventh step of patterning a material stacked on the semiconductor substrate using the blocking layer, and a second step of covering the cell array region on the resultant product.
12 steps of forming a fourth photoresist film pattern covering a part of the first field oxide film covered with the photoresist film pattern and a fifth photoresist film pattern for forming an element forming a peripheral circuit region; A peripheral circuit element is formed in the peripheral circuit region and a dummy conductive pattern is formed on the first field oxide film by patterning the material stacked on the semiconductor substrate using the fourth and fifth photoresist patterns. A method of manufacturing a non-volatile memory device, comprising the thirteenth step. 7. The first insulating film is formed by growing an oxide film with a thickness of about 100Å.
A method for manufacturing a non-volatile memory device according to item 1. 8. The first conductive layer is made of polycrystalline silicon.
The second conductive layer is formed by vapor deposition to a thickness of about 00Å to 2000Å, and the second conductive layer is made of polycrystalline silicon or polycide in which silicide is laminated on polycrystalline silicon.
The method of claim 6, wherein the non-volatile memory device is formed by vapor deposition to a thickness of 0Å to 3000Å. 9. The method of claim 6, wherein the second insulating film is formed by stacking an oxide film / a nitride film / an oxide film. 10. The etching preventing layer is formed by using a material having a large etching selection ratio with respect to a material forming the first and second conductive layers with respect to a predetermined etching. A method for manufacturing a non-volatile memory device according to item 1. 11. The method of claim 10, wherein the etch prevention layer is formed of one of an oxide film and a nitride film. 12. The method of claim 10, wherein the etch-prevention layer is formed by a chemical vapor deposition method.