JPH08288280A - Transistor structure - Google Patents

Abstract

PURPOSE: To decrease a p-n-junction leakage current without enlarging elastic and plastic strains caused by compressive stress at the end brim of a field oxide film, even if integration and packaging density are made higher for obtaining hyper fine structure such as VSLI, ULSI, etc., and along with it, in the case of DRAMs, to decrease a refreshing frequency and to make refresh time longer. CONSTITUTION: Concerning to the structure of a transistor formed into the shape of a quadrangle on the surface of a silicon substrate by surrounding an active region 18 all around with a field oxide film 17, an active region 18 in the shape of a quadrangle is formed arranging its end brim (LOCOS end) 18a along crystal orientation in the direction <100> by tilting it by 45 deg. from silicon crystal orientation in the direction <110> of the substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to selective oxidation element isolation (L
The present invention relates to a transistor structure in which an active region is surrounded by a field oxide film on all sides by a OCOS (LOCal Oxidation of Silicon) method and is formed in a rectangular pattern. More specifically, the present invention relates to a transistor structure suitable for a very large scale integrated circuit (VLSI) and a very large scale integrated circuit (ULSI).

[0002]

2. Description of the Related Art The LOCOS method is usually adopted for element isolation of bipolar ICs and MOS ICs because the active regions can be easily isolated to increase the density. Conventionally, as shown in FIGS. 2 and 4, an edge 18a of an active region 18 formed by a LOCOS method (hereinafter referred to as a LOCOS edge 18a) is one side of a rectangular pattern, and has a [110] silicon crystal. The direction is azimuth, and the sides of the quadrangle are aligned in the <110> direction.

On the other hand, in this LOCOS structure, as shown in FIG.
When the SiO ₂ film 11 shown in FIG. 5D becomes the thick field oxide film 17 shown in FIG. 5E, the edge of the field oxide film 17 goes under the edge of the nitride film 12 and expands in volume. It is known that stress is caused by this. Until now, the analysis of this stress has been performed using the Raman spectroscopy technique (for example, K. Kobayashi, et al. "Local
-Oxidation-Induced Stress Measured by Raman Microp
robe Spectroscopy "J. Electrochem. Soc., Vol.137, No.
6, pp. 1987-1989, June 1990). According to this report, as shown in FIG. 8, when the width W of the active region 18, which is also the distance between the LOCOS ends 18a, is 0.85 /
Raman shifts of 0.65 / cm when the width W is 2.2 μm and 0.30 / cm when the width W is 9.2 μm. This Raman shift represents a compressive stress when the shift amount is positive and a tensile stress when the shift amount is negative. Therefore, when the LOCOS having the same shape is formed, the width W of the active region becomes narrower, in other words, As the width of element isolation is narrowed to achieve higher integration and higher density, the compressive stress tends to increase as opposed to the tensile stress not changing so much. Due to this compressive stress, the crystal lattice of silicon immediately below the LOCOS edge elastically deforms, and when the stress exceeds the yield point, plastic deformation, that is, crystal defects occur. Further, if this crystal defect increases, it has been clarified that the pn junction leakage current flowing when a reverse bias voltage is applied increases in a pn junction transistor, though its theoretical elucidation has not yet been sufficiently clarified. .

Generally, this pn junction leakage current J is expressed by the following equation (1). J = J _L · L + J _A · A (1) where J _L is the peripheral component at the LOCOS edge and J _A is the LOCO
The area component of S (field oxide film), L is the peripheral length of the pattern (active region), and A is the area of the pattern (active region). It is not difficult to imagine that the pn junction leakage current caused by the crystal defects has a great influence on J _L (peripheral component at the LOCOS end) of the above formula (1).

[0005]

By the way, when an integrated circuit such as VLSI or ULSI is manufactured by a conventional transistor structure in which each side of a quadrangle active area is aligned in the <110> direction, these integrated circuits have the active area. Is much finer, the peripheral length becomes overwhelmingly larger than the area of the active region, and therefore the equation (1) is easily transformed into the following equation (2). _{J ≒ J L · L ...... (} 2) That is, if unable pn junction leakage current less inhibition of the LOCOS ends, resulting in the entire chip leakage current is disadvantageously increased. When a transistor such as a DRAM is manufactured under the condition that the leakage current at the LOCOS end is not suppressed to a low level, the transistor has a large amount of unexpected change in the electric charge stored as a memory, and the electric charge is periodically replenished. There is a drawback that the frequency of refresh operations is increased and the refresh time (interval between refresh operations) is shortened.

It is an object of the present invention to increase the elasticity and plastic strain at the LOCOS edge without increasing the elasticity and plastic strain even if the integration and the packaging density are increased in order to obtain a VLSI, ULSI or other ultrafine structure.
It is to provide a transistor structure capable of reducing an n-junction leak current. Another object of the present invention is to provide a transistor structure that can reduce refresh frequency and increase refresh time in the case of DRAM.

[0007]

As shown in FIGS. 1 and 3, the present invention is an improvement of a transistor structure in which an active region 18 is surrounded by a field oxide film 17 in a square shape on a surface of a silicon substrate 10. is there. Its characteristic configuration is
The quadrangular active area 18 has its edge (LOCOS edge).
18a is tilted by 45 degrees from the silicon crystal orientation of the <110> direction of the substrate 10 to be aligned with the crystal orientation of the <100> direction.

[0008]

In the silicon single crystal having the diamond structure, the {111} plane has the maximum atomic density and Young's modulus among the {100}, {110} and {111} plane orientations. Has less binding force than other surfaces. That is, in the silicon single crystal, the first cleavage plane is {11
1} plane, and the second cleavage plane is the {110} plane. It is known that cleavage usually does not occur except in these planes. As described above, in the conventional transistor structure, as shown in FIGS. 2 and 4, the rectangular active region 18 is formed.
, The LOCOS ends 18a are aligned in the <110> direction. As shown in FIG. 5E, the LOCOS end 18a
When a compressive stress is generated at, since the stress generating surface coincides with the {111} surface which is the first cleavage surface, the cleavage surface becomes a sliding surface, and when compressive stress is applied, <110
It is presumed that the crystal lattice is deformed in the> direction to elastically distort, and finally plastic deformation is introduced, resulting in a crystal defect causing a pn junction leakage current.

On the other hand, in the transistor structure of the present invention, as shown in FIGS. 1 and 3, the rectangular active region 18 is formed.
Since the respective sides, that is, the LOCOS ends 18a are aligned in the <100> direction, as shown in FIG.
When a compressive stress is generated at, the stress generating surface does not coincide with the {111} plane that is a sliding surface, the deformation amount of the crystal lattice is small even when the compressive stress is applied, and the crystal defects due to the plastic strain are Less likely to occur. As a result, VLSI, ULSI
Even if the integration and the packaging density are increased to obtain an ultra-fine structure such as the above, the pn junction leakage current when the reverse bias voltage is applied can be suppressed to be low.

[0010]

EXAMPLES Next, examples of the present invention will be described together with comparative examples. <Example> A p-type silicon wafer having a specific resistance of about 10 Ωcm in the (100) plane direction was prepared, and as shown in FIGS.
SiO ₂ film 1 with a thickness of about 30 nm
1 is formed, and a silicon nitride film (Si ₃ N ₄ ) 12 having a thickness of about 50 nm is formed on the upper surface of the SiO ₂ film 11 by the CVD method.
After forming, the photoresist 13 of photosensitive polymer was applied to the entire surface of the nitride film 12. As shown in the enlarged view of FIG. 3, each side of the square pattern has <1 of the silicon substrate 10.
The mask 14 facing the 00> direction was covered on the resist 13, and ultraviolet rays 16 were irradiated through the mask 14. Then, the photoresist 13 was exposed to light and developed to remove the unnecessary resist 13.

As shown in FIG. 5C, the remaining resist 13 is used as a protective film for etching to remove unnecessary portions of the nitride film 12.
After removing, all the resist was removed, and element isolation was performed by channel cut doping. That is, B was ion-implanted to increase the concentration of holes near the exposed surface of the silicon substrate 10. As shown in FIGS. 5D to 5F, heat treatment is performed at a temperature of 950 ° C. in a wet oxygen atmosphere to remove the remaining SiO ₂ film 11 not covered with the nitride film 12 by 5 times.
After the field oxide film 17 having a thickness of 00 nm is grown, the nitride film 12 and the SiO ₂ film 11 thereunder are removed, and the active region 18 is surrounded by the field oxide film 17 on all sides. A pattern as shown was obtained.

<Comparative Example> As shown in the enlarged view of FIG. 4, except that a mask in which each side of a quadrangular pattern faces the <110> direction of the silicon substrate is placed on the resist and ultraviolet rays are radiated through the mask. In the same manner as in the example, a pattern having an active region surrounded by field oxide films on all sides was obtained as shown in the enlarged view of FIG.

<Comparison Test and Evaluation> After ion-implanting As into the active region 18 on the silicon substrate 10 obtained in the examples and comparative examples to form an n-diffusion region, although not shown, electrodes made of polysilicon are used. Was formed. In both the pattern shown in the enlarged view of FIG. 3 and the pattern shown in the enlarged view of FIG. 4, the active region 18 has a width of 2 μm and a length of 2.2 mm, and the field oxide film 17 has a width of 1 μm and a length of 2.2 mm. Was the same. Further, the number of repetitions of the active region and the field oxide film was 1352, which were the same. LOC of these patterns
The total OS peripheral length and the area of the active region were the same in the examples and the comparative examples. In all the chips of each sample of the example and the comparative example, a reverse bias voltage of 0 to 10 V was applied between the polysilicon electrode and the measuring needle that was brought into contact with the back surface of the wafer, and changes in the pn junction leakage current were examined. Further, with the reverse bias voltage fixed at 5 V, the temperature of each wafer of the example and the comparative example was changed in the range of 30 to 125 ° C., and the change of the pn junction leakage current depending on the temperature was examined. The results are shown in FIGS. 6 and 7, respectively. As is clear from FIG. 6, as the reverse bias voltage becomes higher, p
Although the value J of the n-junction leak current was large, the value J of the pn-junction leak current at the time of application of the example was smaller than that of the comparative example regardless of the magnitude of the voltage. Further, as is clear from FIG. 7, the LOC of the pn junction leakage current in both the example and the comparative example.
The value J _L of the peripheral component at the OS edge becomes smaller as the temperature becomes lower, but the value J _L of the peripheral component at the LOCOS edge of the example is always lower than that of the comparative example, and the difference becomes particularly closer to room temperature. It was great.

[0014]

As described above, according to the present invention, by aligning the edge (LOCOS edge) of the square active region with the crystal orientation of the <100> direction of the silicon substrate, the field oxide film is formed. The elasticity and plastic strain of the silicon crystal lattice due to the stress generation can be suppressed. As a result, even if the integration and the packaging density are increased to form an ultrafine structure such as VLSI or ULSI, elasticity and plastic strain associated with the compressive stress at the edge of the field oxide film are not increased, and p
The n-junction leakage current can be reduced. In particular, when the transistor is a DRAM, the refresh frequency can be reduced and the refresh time can be increased.

[Brief description of drawings]

FIG. 1 is a perspective view showing a LOCOS structure of the present invention together with a crystal structure.

FIG. 2 is a perspective view showing a LOCOS structure of a conventional example together with a crystal structure.

FIG. 3 is a plan view of a chip-formed silicon wafer of the present invention.

FIG. 4 is a plan view of a conventional silicon wafer on which chips are formed.

FIG. 5 is a cross-sectional view of a silicon substrate in each element isolation process by the LOCOS method of the embodiment of the present invention.

FIG. 6 shows a pn when a reverse bias voltage is applied in the example and the comparative example.
The figure which shows the change of junction leak current.

FIG. 7 is a diagram showing changes in pn junction leakage current according to temperature in Examples and Comparative Examples.

FIG. 8 is a diagram showing a relationship between an active region width and a stress when an edge of a field oxide film dives under an edge of a nitride film.

[Explanation of symbols]

10 Silicon substrate 11 SiO ₂ film 12 Silicon nitride film 17 Field oxide film 18 Active region 18a Edge of active region (LOCOS edge)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisashi Furuya 1-297 Kitabukuro-cho, Omiya-shi, Saitama, Central Research Laboratory, Mitsubishi Materials Corporation (72) Inventor Masahide Inuishi 4-chome, Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. ULSI Development Laboratory

Claims (1)

[Claims] 1. A transistor structure in which an active region (18) is surrounded by a field oxide film (17) on all sides of a silicon substrate (10) and formed in a rectangular pattern, wherein the rectangular active region (18) is The edge (18a) is the substrate
A transistor structure characterized by being formed in alignment with the crystal orientation of the <100> direction by tilting 45 ° from the silicon crystal orientation of the <110> direction of (10).