JPH08287682A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To provide a semiconductor storage device which can accomplish reduction of current and power source noise at the time of outputting data. CONSTITUTION: The device is provided with a discharge line F1 common to each output signal and transistors, T1 to T4, which connect each output terminal, O1 to O4, with F1. Output control circuits, 11 to 14, are provided with comparison circuits which individually control transistors, T1 to T4, and compare each output terminal, O1 to O4, with the data of internal data, D1 to D4, to selectively connect the common discharge line F1 with the output terminals, O1 to O4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to an output buffer of a semiconductor memory device.

[0002]

2. Description of the Related Art As a conventional technique of this type, for example, in Japanese Patent Laid-Open No. 4-255990, there is no delay in access.
And for the purpose of reducing noise to the power supply line so as not to cause circuit malfunction, as shown in FIG. 7, a pair of output stage transistors 42-1 connected in series between the power supply and the ground at the output section, 43-1. These output stage transistors are turned on / off in reverse according to the outputs DT1 and DN1 of the data output buffer circuit 41-1 which receives the read data as input, and the power is supplied from the series connection point of these output stage transistors. Level or ground level read output (DOUT
1) and a potential generation circuit (VG1) 45-1 that generates a potential (intermediate potential) lower than the power supply voltage is provided.
A semiconductor memory device has been proposed in which the output terminal of (G1) is connected to the series connection point of the output stage transistors 42-1 and 43-1 by a transfer transistor 44-1 which is closed only during a period immediately before data output. . FIG. 4 shows an output circuit having an N-bit configuration.

FIG. 8 is a waveform diagram for explaining the operation of the circuit shown in FIG.

Referring to FIG. 8, first, a data output terminal DOU
When high level (high level) or low level (low level) data is output to T1 to N, the transistor
The clock G that supplies the gate voltage to 44-1 to 44-N is at the low level, and the potential generating circuits VG1 to N and the data output terminal D
The transfer gates 44-1 to 44-N between OUT1 to N are made non-conductive.

When the time to hold the next data is over, DT
All of 1 to DTN and DN1 to DNN are at low level, then the clock G is at high level and the output buffer circuit DO
UT1 to N are connected to potential generating circuits VG1 to VGN via transfer gates 44-1 to 44-N.

Here, the potentials of the data output terminals DOUT1 to NOUT become temporarily equal to the intermediate potential generated by the potential generating circuits VG1 to VGN.

When the next data is output, the clock G first goes to a low level, and then DT1 to DTN or DN1 to DN.
One of N becomes High level and data is output.

This is to reduce power supply noise at the time of output by starting the potential change at the time of outputting the data from the intermediate potential.

[0009]

Although there is a possibility that instantaneous power supply noise can be reduced in the above-mentioned conventional output circuit, there is a problem in that the current consumption increases because it is precharged to the intermediate potential before each output. It was

Therefore, an object of the present invention is to provide a semiconductor memory device which solves the above problems, reduces power supply noise at the time of data output, and achieves a significant reduction in current consumption.

[0011]

In order to achieve the above object, the present invention provides a common discharge line having one end connected to a capacitor, and a switch element for controlling a short circuit between the common discharge line and the output of an output circuit. Circuit means for generating a signal for controlling ON / OFF of the switch element, and a semiconductor memory device.

In the present invention, it is preferable that the common discharge line is in a floating state except when it is in operation.

Further, in the present invention, preferably, a transfer transistor is inserted as the switch element between the output of the output circuit and the common discharge line, and the rising or falling time of the output at which the logic level changes. The transfer transistor is turned on for a predetermined time immediately before, and the output is short-circuited to the common discharge line.

Further, in the present invention, preferably,
The above capacity is provided in the device.

According to the present invention, a common discharge line and a switch element for controlling a short circuit between the common discharge line and the output of the output circuit are provided.
Circuit means for generating a signal for controlling ON / OFF of the switch element, wherein one end of the common discharge line is connected to an external terminal, and the external terminal is connected to a capacitor provided outside the apparatus main body. A semiconductor memory device is provided.

Further, in the present invention, preferably, circuit means for generating a signal for controlling ON / OFF of the switch element includes a data signal input to the output circuit,
It is characterized in that a difference in logic level from a data output signal outputted from the output circuit to a corresponding external terminal is detected and a pulse signal having a predetermined time width is outputted.

In the present invention, preferably,
When the pulse signal is active, the output circuit is in a high impedance state.

Further, in the present invention, preferably,
The output circuit is connected in series between the power supply terminal and the ground,
One is rendered conductive according to the logical value of the data signal,
Circuit means comprising first and second output stage transistors for extracting a data output signal from a common connection point, and setting and controlling both the first and second output stage transistors to be in an off state when the pulse signal is in an active state Is inserted between the data signal and the control terminals of the first and second output stage transistors.

In the present invention, preferably, a selection signal for selectively setting the output of the output circuit to a high impedance state is provided.

According to the present invention, a common discharge line, one end of which is connected to a capacitor, a connection point between an output of an output stage transistor and an external output terminal, and a switch element inserted between the common discharge line, Circuit means for generating a signal for controlling on / off of the switch element, the switch element is turned on immediately before the rising or falling time of the output, and the output stage transistor is set to a high impedance state to output the output. There is provided an output circuit of a semiconductor device, which is short-circuited to the common discharge line.

[0021]

According to the present invention, the connection point between the high-potential-side terminal of the capacitor and the common discharge line is in a floating state. However, the average of the output data for a long period of time shows that the frequency of the high level and the low level is almost the same. Since the ratio is 1: 1, the capacitance is charged to the intermediate level. The present invention intends to reduce power consumption by using this capacity as a kind of power source.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

[0023]

[Embodiment 1] FIG. 1 shows the overall construction of an embodiment of the present invention. A 4-bit output circuit is shown in FIG. 1, D1 to D4 are data outputs (read data) from the internal circuit, T1 to T4 are N-channel transfer gates, O1 to O4 are external output terminals, and F1 is a discharge line (referred to as "common discharge line") commonly provided for each output, one end of which is connected to one terminal of the capacitor C1 and is in a floating state (floating state) except during operation. Transfer control signals E1 to E4 output from the output control circuits 11 to 14 for controlling conduction / non-conduction of the transfer gates are connected to gate terminals of the transfer gates T1 to T4.

FIG. 2 shows the output control circuits 11-14 of FIG.
An example of the circuit configuration of (DOUT1 to 4) is shown.

Referring to FIG. 2, the output control circuit receives N-channel type output stage transistors 22 and 23 connected in series between a power source and ground and a data output D from an internal circuit as a transfer control signal. E is the input of the control terminal,
The boot circuit 21 whose output is connected to the gate terminal of the transistor 22, the NOR circuit 24 whose data output D and the transfer control signal E are input and whose output is connected to the gate terminal of the transistor 23, the data output D and the output signal to the outside. And a comparison circuit 20 for comparing O.

The comparison circuit 20 has a negative exclusive OR circuit 25 (which outputs a high level when a match is detected) which receives the data signal D and the output signal O, and a delay which receives the output of the negative exclusive logic circuit 25. Circuit 26 and negative exclusive logic circuit 2
The output of 5 is used as one input (however, negative logic), and the delay circuit 26
Of the gate circuit 27 whose other input is the output of the delay circuit 26. The difference between the logic levels of the data signal D and the output signal O to the outside at the time when the data signal D changes is defined by the delay time DL1 of the delay circuit 26. A one-shot pulse having a pulse width of 10 μm is output as the transfer control signal E. The delay time DL1 is appropriately determined according to the characteristics required of the device.

The transfer control signal E output from the comparison circuit 20 is input to the gate terminal of the transfer gate (see T1 in FIG. 1) and also to the control terminal of the boot circuit 21 and is at the low level. Boot circuit 21
Is activated and when the data signal D is at high level,
The input data signal D is bootstrap-outputted, and a voltage equal to or higher than the power supply potential VDD is supplied as a gate voltage to the output stage transistor 22 on the power supply side to make the N-channel transistor 22 conductive. Then, a NOR circuit (NOR) circuit 2
Since the output of 4 (node F) is at the Low level, the N-channel transistor 23 is rendered non-conductive, and the output O is pulled up to the power supply potential.

When the data signal D is at low level, N
The output (node F) of the OR circuit 24 becomes High level, and N
The channel transistor 23 is rendered conductive, the N-channel transistor 22 is rendered non-conductive, and the output O is at ground potential. The boot circuit 21 is a circuit that creates a potential higher than the power supply voltage by a so-called bootstrap method using, for example, capacitive coupling, and raises the signal level to the power supply voltage VDD or higher (for example, VDD + VT or higher, where VT is an N-channel transistor). Of the N channel type output stage transistor 22).

When the transfer control signal E is at a high level (when a one-shot pulse is output), the NOR circuit 24
The node F, which is the output of, is set to the Low level, and the node C, which is the output of the boot circuit 21, is set to the Low level.
Both the transistors 22 and 23 are turned off, and the output O
Is disconnected from the power supply. The data output D1 in FIG.
To D4, outputs O1 to O4, transfer control signals E1 to
E4 corresponds to D, O, and E in FIG. 2, respectively.

There are the following four patterns of data change, and the operation for each of them will be described with reference to the waveform chart of FIG.

The first is the case where the output transits from the high level to the low level (shown as the output O1 in FIG. 3).

The output O1 initially outputs a high level, but when the data D1 changes from "H" to "L" (at the falling edge), the levels of the output O1 and the data D1 are different at a certain point. The output control circuit 11 outputs a one-shot pulse (having the pulse width of the delay time of the delay circuit 26 in FIG. 2) as the transfer control signal E1.

At this time, the transfer control signal E1 is High
During the level, the transfer gate T1 becomes conductive, and the output O1
Is disconnected from the power supply, connected to the node F1 via the transfer gate T1, and has an intermediate potential.

After that, the transfer control signal E1 becomes Low.
When the level becomes the level, the transfer gate T1 becomes non-conductive, the output O1 is separated from the node F1, and the output O1 is set to the Low level by the output control circuit 11.

The second is the case where the output transits from the low level to the high level (shown as the output O3 in FIG. 3). Referring to FIG. 3, in the case of the output O3, since it rises from the Low level to the High level, one-shot as the transfer control signal E3 is performed at the time when the logic levels of the data D3 and the output O3 are different, as in the case of the output O1 described above. A pulse is output and the output O3 is the transfer gate T3.
A connection is made to the node F1 via. When the transfer control signal E3 becomes low level, the transfer gate T
3 becomes non-conductive, the output O3 is separated from the node F1, and the output O3 becomes High level by the output control circuit 11.

The third and fourth patterns are the cases where the output is held at the high level or the low level (no change). Referring to FIG. 3, in the case of the outputs O2 and O4, the transfer control signals E2 and E4 do not change because the data does not change at High level and Low level (Lo
The transfer gates T2 and T4 are turned off.

An example of the operation and effect of this embodiment will be described below.

The current consumption of the output circuit depends on the pattern of the output data, but if all outputs alternately change by half as the most efficient pattern, the current consumption is reduced by about 50% in the present embodiment, and Even if all inefficient outputs operate simultaneously, if the capacity of the common node is half the total output load, it will be reduced by about 30%.

For example, for the sake of simplicity, the outputs are 2 of O1 and O2.
Regarding the two cases, the case where the High level and the Low level are alternately output will be described below. In the case of an output circuit that does not have the configuration of this embodiment (a configuration in which the output of the output stage transistor is connected to an external terminal), the capacitance of the output terminal (for example, C = 50 p
F) is driven between the power supply voltage VDD (for example, 5 V) and the ground level, so that the charge per cycle C × VDD = 50 pF ×
A current amount equivalent to 5V flows, so 1/2 x 50pF x 5V ²
(= 1/2 CVDD ² ) power is consumed.

On the other hand, in this embodiment, High
Level and low level output signals O1 and O2 are transferred to the transfer gate T by one-shot pulse signals E1 and E2.
1 and T2 are short-circuited to be approximately 1/2 VDD level. In this case, at the stage of becoming 1/2 VDD level, it is obtained by neutralizing with the voltage levels of the two outputs O1 and O2 and does not consume power source power (shorted output terminal and common connection line F1 are Has been separated).

Since the power is changed from 1/2 VDD (= 2.5 V) level to VDD or GND level, the power consumption is 1
It becomes (1/2) × 50 pF × 2.5 V ² per cycle, which is about 25% compared with the case where the configuration of this embodiment is not taken, and is actually 75%.
Also reduces power consumption (consumption current is 50%).

An example of the case where the efficiency is the worst will be described next. In FIG. 1, considering only the outputs O1 and O2, the capacitance value of the capacitance C1 is the capacitance value of all output loads (parallel combined capacitance value). In the case of half (for example, when the output load capacitance of O1 and O2 is 50 pF, the capacitance value of the capacitance C1 is 50 pF)
F) and outputs O1 and O2 are high level at the same time or low at the same time
In the case of changing to a level (referred to as "simultaneous operation"), when changing from "H" to "L" to "H", first, when changing from "H" to "L", the outputs O1 and O2 and the capacitance C1
The node F1 of the common discharge line, which is the high-potential side terminal of, is short-circuited, and the potential is (50pF × 5V × 2 + 50pF × 2.5) / 150pF
= 4.17V.

Then, the outputs O1 and O2 are simultaneously set to the low level, and the output O is output at the time before the output is changed to the high level.
1 and O2 are short-circuited to the 4.17V node F1 and the output potential is 0V to 50pF × 4.17 / 150pF = 1.39V. The amount of current required to raise this potential to the power supply potential VDD is 50pF × (5-1.39). ) × 2 = 361pF · V. On the other hand, in the case of the configuration not using this embodiment, 50 pF
× 5 × 2 = 500pF ・ V, which reduces the current consumption by about 30%.

[0044]

Second Embodiment FIG. 4 is a block diagram of the second embodiment of the present invention.

Referring to FIG. 4, the difference between this embodiment and the first embodiment is that the output can be brought into a high impedance state (“Hi-Z” state) by the device selection signal S.
And the node F1 is output as a terminal outside the device.

By outputting the node F1 as an external terminal to the outside, the capacitance required for the node F1 can be provided outside the device, and even if two or more memory devices are used on the system, only one capacitance is required.

FIG. 5 shows the output control circuit 7 in this embodiment.
It is a figure which shows the circuit structure of 1-74. In the circuit of FIG. 5, when the device selection signal S is the boot circuit 61, the NOR circuit 64,
NO of the output stage of the transfer control signal E of the comparison circuit 60
The point of being input to the R circuit 67 is different from the configuration of the first embodiment of FIG. When the device selection signal S is active (= High level), the circuit of FIG. 5 operates similarly to FIG. 2, but when the device selection signal S is inactive (= Low level), both the transistors 62 and 63 are off. The output O1 is in the high impedance state, and the signal E is always at the low level.

Further, in this embodiment, current reduction and noise reduction can be performed at the system level.

FIG. 6 is a diagram for explaining the configuration when two memory devices to which this embodiment is applied are used in the system. The system 83 selects one of the first and second devices M1 and M2 by the device selection signals S and S '.

The outputs O1 to O4 of the device not selected by the device selection signal S are in a high impedance state and the circuit does not operate, and the device selected by the device selection signal S is the same as in the first embodiment. Operate.

In the present embodiment, the case of the two-device configuration is shown, but the same applies to the case of using more devices, and the capacity C1 may be one.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments and includes various embodiments according to the principle of the present invention. For example, the present invention is preferably applied not only to a memory device but also to an output circuit of a semiconductor device which has a plurality of output terminals and outputs data output from an internal circuit to an external terminal. Further, the circuit configuration shown in FIG. 2 and the like is for the purpose of explanation only, and does not limit the present invention.

[0053]

As described above, according to the present invention,
By selectively connecting the output of the semiconductor memory device to the common node, current (current consumption) can be reduced and power supply noise can be reduced.

The amount of current depends on the pattern of the output data, but in the case where the total output alternately changes by half as the most efficient pattern, the current consumption is about 50 according to the present invention.
%, Even if the most inefficient all outputs operate at the same time, if the capacity of the common node is half of the total output load, the current consumption will decrease by about 30%.

Further, according to the present invention, the increase in the circuit scale due to the provision of the intermediate potential generation circuit for each output as in the conventional example is suppressed, and the power supply noise at the time of output change (switching) is suppressed by the simple circuit configuration. This has the advantage that the current consumption of the device is significantly reduced.

Further, according to the present invention, preferably, one end of the common discharge line is connected to the capacitor through the external terminal, so that one capacitor can be provided for a plurality of semiconductor memory devices. It has the advantage of being good.

Further, according to the present invention, since the external terminal for inputting the device selection signal is provided, the design of the memory system is facilitated and only the selected device is brought into the operating state, so that the power consumption at the system level is achieved. Has been achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of an output control circuit (DOUT) according to the first embodiment of the present invention.

FIG. 3 is a waveform diagram illustrating the operation of the first exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of an output control circuit (DOUT) according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an example of a system configuration using a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an output circuit of a conventional semiconductor device.

FIG. 8 is a waveform diagram illustrating the operation of the output circuit of the conventional semiconductor device.

[Explanation of symbols]

 11 to 14 output control circuit 20 comparison circuit 21 boot circuit 22, 23 output stage transistor 24 NOR circuit 25 negative exclusive OR circuit 26 delay circuit 27 NOR circuit with one negative logic input C1 capacitance D, D1 to D4 data Output E, E1 to E4 Transfer control signal F1 Common discharge line node O, O1 to O4 External output terminal S Device selection signal T1 to T4 Transfer transistor

Claims (11)

[Claims] 1. A common discharge line having one end connected to a capacitor, a switch element for controlling a short circuit between the common discharge line and an output of an output circuit, and a signal for controlling ON / OFF of the switch element. A semiconductor memory device comprising: circuit means. 2. The semiconductor memory device according to claim 1, wherein the common discharge line is in a floating state except during operation. 3. A transfer transistor is inserted as the switch element between the output of the output circuit and the common discharge line, and the transfer transistor is set to a predetermined level immediately before a rising or falling point of the output at which the logic level changes. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is turned on for a period of time to short-circuit the output to the common discharge line. 4. The semiconductor memory device according to claim 1, wherein the capacitor is provided in the device. 5. The semiconductor memory device according to claim 1, further comprising a plurality of the output circuits, wherein the switch element is provided between each output of the plurality of output circuits and the common discharge line. 6. A common discharge line, a switch element for controlling a short circuit between the common discharge line and an output of an output circuit, and a circuit means for generating a signal for controlling ON / OFF of the switch element, A semiconductor memory device, wherein one end of the common discharge line is connected to an external terminal, and a capacitance provided outside the device body is connected to the external terminal. 7. A circuit means for generating a signal for controlling ON / OFF of the switch element, a data signal input to the output circuit, and a data output signal output from the output circuit to a corresponding external terminal. 7. The semiconductor memory device according to claim 1, wherein the semiconductor memory device detects a difference in logic level between the two and outputs a pulse signal having a predetermined time width. 8. A semiconductor memory device according to claim 7, wherein said output circuit is in a high impedance state when said pulse signal is active. 9. The first and second output circuits, wherein the output circuit is connected in series between a power supply terminal and a ground, one of the output circuits is brought into a conductive state according to a logical value of the data signal, and a data output signal is taken out from a common connection point. The output stage transistor of, and when the pulse signal is in an active state, the first and second
8. The semiconductor memory according to claim 7, further comprising a circuit for setting both of the output stage transistors in the OFF state between the data signal and the control terminals of the first and second output stage transistors. apparatus. 10. The semiconductor memory device according to claim 1, further comprising a selection signal for selectively setting an output of the output circuit to a high impedance state. 11. A common discharge line, one end of which is connected to a capacitor, a connection point between an output of an output stage transistor and an external output terminal, and a switch element inserted between the common discharge line, and the switch element. Circuit means for generating a signal for controlling on / off of the output, the switch element is turned on immediately before the rising or falling time of the output, the output stage transistor is set to a high impedance state, and the output is shared. An output circuit of a semiconductor device, which is short-circuited to a discharge line.