JP2825069B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to an output buffer of a semiconductor memory device.

[0002]

2. Description of the Related Art As a prior art of this kind, for example, Japanese Patent Application Laid-Open No. Hei 4-255990 discloses that
For the purpose of reducing noise to the power supply line so as not to cause a circuit malfunction, as shown in FIG. 7, a power supply is connected to the output unit, a pair of output stage transistors 42-1 connected in series between the ground, 43-1. These output stage transistors are turned on and off in accordance with the outputs DT1 and DN1 of the data output buffer circuit 41-1 which receives read data as input. Readout (DOUT
1), and a potential generation circuit (VG1) 45-1 for generating a potential (intermediate potential) lower than the power supply voltage is provided.
A semiconductor memory device has been proposed in which the output terminal of G1) is connected to the series connection point of the output stage transistors 42-1 and 43-1 by the transfer transistor 44-1 which is closed only during a period immediately before data output. . FIG. 4 shows an output circuit having an N-bit configuration.

FIG. 8 is a waveform chart for explaining the operation of the circuit shown in FIG.

Referring to FIG. 8, first, a data output terminal DOU
When high level (high level) or low level (low level) data is output to T1 to N, the transistor
The clock G for supplying the gate voltage to 44-1 to 44-N is at the low level, and the potential generating circuits VG1 to VG and the data output terminal D
Transfer gates 44-1 to 44-N between OUT1 to OUTN are turned off.

Next, when the time to hold the data is over, DT
1 to DTN and DN1 to DNN all become Low level, and then the clock G becomes High level and the output buffer circuit DO
UT1 to UTN are connected to potential generation circuits VG1 to VGN via transfer gates 44-1 to 44-N.

Here, the potentials of the data output terminals DOUT1 to DOUTN are temporarily equal to the intermediate potentials generated by the potential generating circuits VG1 to VGN.

When the next data is output, first, the clock G goes low, and then DT1 to DTN or DN1 to DN
Any of N becomes High level, and data is output.

This is intended to reduce power supply noise at the time of output by starting the potential change at the time of data output from an intermediate potential.

[0009]

In the conventional output circuit, although there is a possibility that the instantaneous power supply noise can be reduced, there is a problem that current consumption increases because the power supply is precharged to an intermediate potential before each output. Was.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor memory device which solves the above-mentioned problems, reduces power supply noise at the time of data output, and achieves a significant reduction in current consumption.

[0011]

In order to achieve the above object, the present invention controls a common discharge line having one end connected to a capacitor, and controls a short circuit between the common discharge line and outputs of a plurality of output circuits.
A plurality of switching elements, and a circuit means for generating a signal for controlling each on / off of the plurality of switching elements, only including, output selection each of the plurality of output circuits
Alternatively, the capacitor is short-circuited to the common discharge line, and the capacity is high level.
It will be charged to a level almost between the low level and the low level
Thus, there is provided a semiconductor memory device characterized in that:

In the present invention, preferably, the common discharge line is in a floating state except during operation.

Further, in the present invention, preferably, a transfer transistor is inserted as the switch element between the output of the output circuit and the common discharge line, and a rising or falling point of the output at which a logical level changes is changed. Immediately before the transfer transistor is turned on for a predetermined time, and the output is short-circuited to the common discharge line.

Further, in the present invention, preferably,
The apparatus is characterized in that the capacity is provided in the device.

The present invention provides a common discharge line, a switch element for controlling a short circuit between the common discharge line and an output of an output circuit,
Circuit means for generating a signal for controlling ON / OFF of the switch element, wherein one end of the common discharge line is connected to an external terminal, and a capacitor provided outside the apparatus body is connected to the external terminal. And a semiconductor memory device characterized in that:

In the present invention, preferably, the circuit means for generating a signal for controlling on / off of the switch element comprises: a data signal input to the output circuit;
A pulse signal having a predetermined time width is output by detecting a difference in logic level from a data output signal output from the output circuit to a corresponding external terminal.

In the present invention, preferably,
When the pulse signal is active, the output circuit is configured to be in a high impedance state.

Further, in the present invention, preferably,
The output circuit is connected in series between a power supply terminal and ground,
One is made conductive according to the logical value of the data signal,
Circuit means for providing first and second output stage transistors from which a data output signal is extracted from a common connection point, and for setting and controlling both the first and second output stage transistors to an off state when the pulse signal is in an active state Is inserted between the data signal and control terminals of the first and second output stage transistors.

In the present invention, preferably, a selection signal for selectively setting the output of the output circuit to a high impedance state is provided.

According to the present invention, a common discharge line having one end connected to a capacitor, a connection point between an output of an output stage transistor and an external output terminal, a switch element inserted between the common discharge line, Circuit means for generating a signal for controlling the on / off of the switch element, wherein the switch element is turned on immediately before the rise or fall of the output, setting the output stage transistor to a high impedance state and turning the output on. An output circuit of a semiconductor device, wherein the output circuit is short-circuited to the common discharge line.

[0021]

According to the present invention, the connection point between the high-potential side terminal of the capacitor and the common discharge line is in a floating state. Because of the one-to-one ratio, the capacitance is charged to an intermediate level. The present invention aims to reduce power consumption by using this capacity as a kind of power supply.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

[0023]

[Embodiment 1] FIG. 1 shows the configuration of an entire embodiment of the present invention. FIG. 1 shows a 4-bit output circuit, D1 to D4 are data outputs (read data) from internal circuits, T1 to T4 are N-channel transfer gates, O1 to O4 are external output terminals, F1 is a discharge line provided in common for each output (referred to as "common discharge line"), one end of which is connected to one terminal of the capacitor C1 and is in a floating state (floating state) except during operation. The gate terminals of the transfer gates T1 to T4 are connected to transfer control signals E1 to E4 output from the output control circuits 11 to 14 and controlling conduction / non-conduction of the transfer gates.

FIG. 2 shows output control circuits 11 to 14 of FIG.
An example of the circuit configuration of (DOUT1 to 4) is shown.

Referring to FIG. 2, an output control circuit receives N-channel output stage transistors 22 and 23 connected in series between a power supply and a ground, and data output D from an internal circuit as input, and a transfer control signal. E is the input of the control terminal,
A boot circuit 21 having an output connected to the gate terminal of the transistor 22, a NOR circuit 24 having a data output D and a transfer control signal E as inputs and an output connected to the gate terminal of the transistor 23, a data output D and an external output signal And a comparison circuit 20 for comparing O with O.

The comparison circuit 20 has a negative exclusive OR circuit 25 (inputting a high level when a match is detected) to which the data signal D and the output signal O are input, and a delay input having the output of the negative exclusive logic circuit 25 as an input. Circuit 26 and the negated exclusive logic circuit 2
5 as one input (however, negative logic), and the delay circuit 26
And a gate circuit 27 having the other input as the other input. When there is a difference between the logic levels of the data signal D and the output signal O to the outside when the data signal D changes, the delay time DL1 of the delay circuit 26 defines the difference. A one-shot pulse having a predetermined pulse width is output as the transfer control signal E. The delay time DL1 is appropriately determined according to the characteristics required for the device.

The transfer control signal E output from the comparison circuit 20 is input to the control terminal of the boot circuit 21 in addition to the gate terminal of the transfer gate (see T1 in FIG. 1). Boot circuit 21
Is active, and when the data signal D is at the high level,
The input data signal D is bootstrap output, and a voltage higher than the power supply potential VDD is supplied as a gate voltage to the output-side transistor 22 on the power supply side to make the N-channel transistor 22 conductive. And a NOR (NOR) circuit 2
Since the output of No. 4 (node F) is at the Low level, the N-channel transistor 23 is turned off, and the output O is pulled up to the power supply potential.

When the data signal D is at the low level, N
The output (node F) of the OR circuit 24 becomes High level and N
Channel transistor 23 is turned on, N-channel transistor 22 is turned off, and output O is at the ground potential. The boot circuit 21 is a circuit for generating a potential equal to or higher than the power supply voltage by a so-called bootstrap method using, for example, capacitive coupling. , The gate threshold voltage of the N-channel type output stage transistor 22.

When the transfer control signal E is at the high level (one-shot pulse output), the NOR circuit 24
Is low, and the node C, which is the output of the boot circuit 21, is low.
Transistors 22 and 23 are both turned off, and output O
Is disconnected from the power supply. Note that the data output D1 in FIG.
D4, outputs O1 to O4, transfer control signals E1 to
E4 corresponds to D, O, and E in FIG. 2, respectively.

There are the following four patterns of data change, and the operation of each of them will be described with reference to the waveform diagram of FIG.

The first case is when the output transitions from the high level to the low level (in FIG. 3, it is shown as output O1).

Although the output O1 initially outputs a high level, when the data D1 changes from "H" to "L" (falling), the level of the output O1 differs from that of the data D1 at a certain point in time. The output control circuit 11 outputs a one-shot pulse (having the pulse width of the delay time of the delay circuit 26 in FIG. 2) as the transfer control signal E1.

At this time, the transfer control signal E1 becomes High.
The transfer gate T1 conducts during the level, and the output O1
Is disconnected from the power supply, is connected to the node F1 via the transfer gate T1, and has an intermediate potential.

After that, the transfer control signal E1 becomes low.
When the level becomes the level, the transfer gate T1 becomes non-conductive, the output O1 is disconnected from the node F1, and the output O1 is set to the low level by the output control circuit 11.

The second case is when the output transitions from the low level to the high level (in FIG. 3, it is indicated as output O3). Referring to FIG. 3, in the case of the output O3, since it rises from the Low level to the High level, as in the case of the output O1, the one-shot transfer control signal E3 is obtained when the logic levels of the data D3 and the output O3 differ. A pulse is output, and the output O3 is connected to the transfer gate T3.
Is connected to the node F1. When the transfer control signal E3 goes low, the transfer gate T
3 is turned off, the output O3 is disconnected from the node F1, and the output O3 is set to the high level by the output control circuit 11.

The third and fourth patterns are cases where the output is held at the high level or the low level (no change). Referring to FIG. 3, in the case of the outputs O2 and O4, the transfer control signals E2 and E4 do not change (Lo
, the transfer gates T2 and T4 are turned off.

An example of the operation and effect of this embodiment will be described below.

The current consumption of the output circuit depends on the pattern of the output data, but when the total output alternates by half as the most efficient pattern, the current consumption is reduced by about 50% in this embodiment. Even if inefficient all outputs operate at the same time, reducing the common node capacity by half of the total output load will reduce about 30%.

For example, for simplicity, the output is O1 and O2.
The case where the High level and the Low level are alternately output will be described below. In the case of an output circuit that does not take the configuration of the present embodiment (a configuration in which the output of the output stage transistor is connected to an external terminal), the capacitance of the output terminal (for example, C = 50p)
F) between the power supply voltage VDD (for example, 5 V) and the ground level, the charge per cycle C × VDD = 50 pF ×
A current amount corresponding to 5 V flows, and therefore 1/2 × 50 pF × 5 V ²
(= 1/2 CVDD ² ) of power is consumed.

On the other hand, in the present embodiment,
The output signals O1 and O2 of the low level and the low level are transferred to the transfer gate T by one-shot pulse signals E1 and E2.
1, short-circuited through T2, and set to approximately 1/2 VDD level. In this case, at the stage where the voltage becomes 1/2 VDD level, the power is not consumed because the power is obtained by neutralizing with the voltage levels of the two outputs O1 and O2 (the shorted output terminal and the common connection line F1 are Disconnected).

Since the power supply makes a transition from the 1/2 VDD (= 2.5 V) level to the VDD or GND level by the power supply, the power consumption is 1
(1/2) × 50 pF × 2.5 V ² per cycle, which is about 25% as compared with the case where the configuration of the present embodiment is not taken, and is actually 75%
Also reduce power consumption (current consumption by 50%).

Next, an example of the case of the lowest efficiency will be described. In FIG. 1, considering only the outputs O1 and O2, the capacitance value of the capacitor C1 is equal to the capacitance value (parallel combined capacitance value) of all output loads. In the case of half (for example, when the output load capacity of O1 and O2 is 50 pF, the capacity value of the capacity C1 is set to 50 pF.
F), Outputs O1 and O2 are High level at the same time or Low at the same time
In the case of an operation that changes to a level (referred to as “simultaneous operation”), when the state changes from “H” to “L” to “H”, first, when the state changes from “H” to “L”, the outputs O 1 and O 2 C1
The node F1 of the common discharge line, which is the high-potential side terminal, is short-circuited, and the potential is (50pF × 5V × 2 + 50pF × 2.5) / 150pF
= 4.17V.

Then, the outputs O1 and O2 go low at the same time, and the output O
1, O2 is short-circuited to the node F1 of 4.17 V, the output potential is changed from 0 V to 50 pF × 4.17 / 150 pF = 1.39 V, and the amount of current required to increase from this potential to the power supply potential VDD is 50 pF × (5-1.39 ) × 2 = 361 pF · V. On the other hand, in the case of a configuration not using this embodiment, 50 pF
× 5 × 2 = 500 pF · V, reducing the current consumption by about 30%.

[0044]

Embodiment 2 FIG. 4 is a block diagram of a second embodiment of the present invention.

Referring to FIG. 4, the difference between this embodiment and the first embodiment is that the output can be set to a high impedance state ("Hi-Z" state) by device selection signal S.
And the node F1 is output as a terminal outside the device.

By providing the node F1 as an external terminal to the outside, the capacity required for the node F1 can be provided outside the device. Even when two or more memory devices are used in the system, only one capacity is required.

FIG. 5 shows the output control circuit 7 in this embodiment.
FIG. 1 is a diagram illustrating circuit configurations 1 to 74. In the circuit of FIG. 5, the device selection signal S is supplied to the boot circuit 61, the NOR circuit 64,
NO at output stage of transfer control signal E of comparison circuit 60
The difference from the configuration of the first embodiment shown in FIG. When the device selection signal S is active (= High level), the circuit of FIG. 5 operates similarly to FIG. 2, but when the device selection signal S is inactive (= Low level), both the transistors 62 and 63 are off. State, the output O1 is in the high impedance state, and the signal E is always at the low level.

In this embodiment, current reduction and noise reduction can be performed at the system level.

FIG. 6 is a diagram for explaining the configuration when two memory devices to which the present embodiment is applied are used in a system. The system 83 selects one of the first and second devices M1 and M2 according to the device selection signals S and S '.

The outputs O1 to O4 of the devices not selected by the device selection signal S are in a high impedance state and the circuit does not operate, and the device selected by the device selection signal S is the same as in the first embodiment. Operate.

In this embodiment, the case of two device configurations is shown. However, the same applies to the case where more devices are used, and only one capacitor C1 is required.

Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment but includes various embodiments according to the principle of the present invention. For example, the present invention is suitably applied to an output circuit of a semiconductor device having a plurality of output terminals and outputting data output from an internal circuit to an external terminal, in addition to the storage device. Further, the circuit configurations shown in FIG. 2 and the like are merely for explanation, and do not limit the present invention.

[0053]

As described above, according to the present invention,
By selectively connecting the output of the semiconductor memory device to the common node, the current (current consumption) can be reduced and the power supply noise can be reduced.

The amount of current depends on the pattern of the output data, but when the total output alternates by half as the most efficient pattern, according to the present invention, the current consumption is about 50%.
Even if all outputs, which are the least efficient, operate at the same time, the current consumption is reduced by about 30% if the capacity of the common node is half of the total output load.

Further, according to the present invention, the increase in the circuit scale due to the provision of the intermediate potential generating circuit for each output as in the above-mentioned conventional example is suppressed, and the power supply noise at the time of output change (switching) is reduced by a simple circuit configuration. This has the advantage that the power consumption of the device is greatly reduced.

According to the present invention, preferably, one end of the common discharge line is connected to a capacitor via an external terminal, so that a plurality of semiconductor memory devices have one capacitor. It has the advantage of being good.

Further, according to the present invention, the provision of the external terminal for inputting the device selection signal simplifies the design of the memory system and activates only the selected device, so that power consumption at the system level is achieved. Reduction has been achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a circuit configuration of an output control circuit (DOUT) according to the first embodiment of the present invention.

FIG. 3 is a waveform chart for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating a circuit configuration of an output control circuit (DOUT) according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of a system configuration using a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of an output circuit of a conventional semiconductor device.

FIG. 8 is a waveform diagram illustrating an operation of an output circuit of a conventional semiconductor device.

[Explanation of symbols]

 11 to 14 Output control circuit 20 Comparison circuit 21 Boot circuit 22, 23 Output stage transistor 24 NOR circuit 25 Negative exclusive OR circuit 26 Delay circuit 27 NOR circuit with one negative logic input C1 Capacitance D, D1 to D4 Data Output E, E1 to E4 Transfer control signal F1 Node of common discharge line O, O1 to O4 External output terminal S Device selection signal T1 to T4 Transfer transistor

Claims (10)

(57) [Claims] 1. A common discharge line having one end connected to a capacitor, a plurality of switch elements for controlling a short circuit between the common discharge line and outputs of a plurality of output circuits, and turning on / off of the plurality of switch elements. viewing including circuit means for generating signals for controlling each of the selection outputs of the plurality of output circuits each to the common
Short-circuited to the discharge line, the capacitance is high level and low level
Wherein the semiconductor memory device is charged to a substantially intermediate level . 2. The semiconductor memory device according to claim 1, wherein said common discharge line is in a floating state except during operation. 3. A transfer transistor is inserted as the switch element between the output of the output circuit and the common discharge line, and the transfer transistor is set at a predetermined time immediately before the rise or fall of the output at which the logic level changes. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is turned on for a time, and the output is short-circuited to the common discharge line. 4. The semiconductor memory device according to claim 1, wherein said capacitor is provided in the device. 5. A common discharge line, the control circuit between the output of the common discharge line and a plurality of output circuits
A plurality of switch elements to be turned on and off and on / off of the plurality of switch elements, respectively.
Circuit means for generating an external signal; connecting one end of the common discharge line to an external terminal;
A capacitor provided outside the apparatus main body is connected to the output terminal, and the outputs of the plurality of output circuits are selectively connected to the common terminal.
Short-circuited to the discharge line, the capacitance is high level and low level
To be charged to almost the middle level of
A semiconductor memory device characterized by the above-mentioned. 6. An on / off control of the switch element.
Circuit means for generating a signal is input to said output circuit.
Data signal to be output and a corresponding external terminal from the output circuit.
The difference in logic level from the data output signal output to the
It detects and outputs a pulse signal of a predetermined time width
The semiconductor device according to claim 1, wherein
Storage device. 7. When the pulse signal is active, the output is
The power circuit is configured to be in a high impedance state.
7. The semiconductor memory device according to claim 6, wherein: 8. An output circuit according to claim 1, wherein said output circuit is connected in series between a power supply terminal and ground.
Connected according to the logic value of the data signal.
State and the data output signal is extracted from the common connection point.
First and second output stage transistors, and the first and second output stage transistors are provided when the pulse signal is in an active state.
To set both output stage transistors to off state
A circuit is connected to the data signal and the first and second output stage transformers.
A contractor characterized by being inserted between the
The semiconductor storage device according to claim 6. 9. The output of the output circuit is selectively high impedance.
It has a selection signal for setting the dance state.
The semiconductor according to any one of claims 1, 2, and 5, wherein
Storage device. 10. A common discharge line, one end of which is connected to a capacitor, each output of a plurality of output stage transistors and a corresponding output.
Between the connection point with each external output terminal and the common discharge line
A plurality of switch elements respectively inserted, and on / off control of the plurality of switch elements, respectively.
Circuit means for generating a signal to generate the output signal immediately before the rise or fall of the output.
The switch element is turned on, and the output stage transistor is set to a high
The output is shorted to the common discharge line as an impedance state.
And the capacitance is approximately halfway between the high level and the low level.
Characterized to be charged to the level
Output circuit of a semiconductor device.