JPH08286981A - Error correcting code generator for burst transfer memory - Google Patents

Abstract

PURPOSE: To simultaneously generate error correcting codes by an extended Hamming code for transferred data to the number of the signal lines of a data bus by fetching the data successively from each signal line of the data bus at the time of burst-transferring the data of continuous addresses. CONSTITUTION: While the effective data is transmitted on the data bus 1, a first circuit 5 makes an enable signal 7 outputted from a memory controller 10 an input signal, and outputs the strobe signals 8 of a prescribed number to instruct a second circuit 6 to fetch the data from the data bus 1 and use it for the calculation of the error correcting code and an initilaize signal 9 to set an initial state at the time of starting the calculation of the error correcting code. The strobe signal 8 is outputted so that the second circuit 6 generates the error correcting code by the extended Hamming code. The second circuit 6 receives the strobe signal 8 and the initialize signal 9, and fetches a prescribed data signal from the data bus 1, and calculates and outputs the error correcting code for every signal line of the data bus 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus using a semiconductor memory accessed by burst transfer, and more particularly to a circuit for detecting and correcting a bit error occurring in the semiconductor memory.

[0002]

2. Description of the Related Art Conventionally, the mainstream access method for semiconductor memories is to transfer only one data corresponding to an address each time it is designated. In this method, in order to transfer data at high speed, the width of the data bus is expanded and the number of bytes that can be transferred in one access is increased. As an example of generation of an error correction code for this conventional method, in a 32-bit width data bus, an error correction code by a 7-bit extended Hamming code is generated for each 32-bit data transferred in one access. There is a method to do. The data that appears in the 0th bit to the 31st bit is
The error correction code by the extended Hamming code is calculated and output by taking in the seven parity generation circuits.

In this method, an error correction code is generated by a combinational logic circuit. Therefore, as the speed of the microprocessor and the access speed of the memory improve, the problem that the error detection speed cannot follow can occur.

[0004]

In order to follow the increase in the speed of microprocessors, a method using burst transfer as in a synchronous DRAM or a Rambus channel is becoming popular as a means for faster memory access. It is possible to do it. However, there is a problem that it is difficult to support burst transfer with the conventional error correction code generation method.

Therefore, in order to solve this problem, an object of the present invention is to transfer the data of consecutive addresses by burst-transferring the data from each signal line of the data bus. An object of the present invention is to realize a device that simultaneously generates the error correction code by the extended Hamming code for the number of signal lines of the data bus. The burst transfer means a transfer mode in which the data bus is dedicated until the transfer of a predetermined amount of data is completed.

[0006]

According to the present invention, a predetermined number of parity check circuits are connected in parallel for each signal line of a data bus that transfers data between a memory device and a memory control device. When the burst transfer of a predetermined amount of data is completed for each data line, the calculation of the error correction code by the extended Hamming code is completed and output.

When a valid signal is sent to the data bus, an enable signal output from the memory controller is used as an input signal to fetch the data from the data bus and use the timing for calculating the error correction code according to a predetermined algorithm. A first circuit that outputs a predetermined number of strobe signals that are instructed based on the above, and an initialization signal that sets an initial state at the start of error code calculation; and a strobe signal and an initialization signal that are input signals from the data bus. It is characterized by comprising a second circuit for sequentially fetching data and calculating and outputting an error correction code for each signal line of the data bus.

[0008]

The first circuit uses the enable signal output from the memory control device as an input signal while valid data is being sent to the data bus, and the second circuit takes in the data from the data bus and calculates the error correction code. A predetermined number of strobe signals instructing the use thereof and an initialization signal for setting an initial state at the time of starting the calculation of the error correction code are output.

The strobe signal is output so that the second circuit generates an error correction code by the extended Hamming code.
The second circuit receives the strobe signal and the initialization signal, takes in a predetermined data signal from the data bus, calculates an error correction code for each signal line of the data bus, and outputs the error correction code.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. As an example, data transfer performed between the synchronous DRAM 11 and the memory control device 10 that controls the access will be described.

Reference numeral 1 is a data bus connecting the memory control device 10 and the synchronous DRAM 11 and simultaneously transfers n-bit data by n signal lines. In the following description, n-bit data that is transferred at the same time will be called a word. Reference numeral 2 is an address bus, which is composed of m signal lines and has m bits, but the address designating method is determined by the specifications of the synchronous DRAM 11 to be used.

Reference numeral 3 is a clock signal or a signal line. Since the synchronous DRAM 11 transfers data in synchronization with the clock signal, each of the circuit blocks 5, 6, 10 and 11 receives the clock signal. Reference numeral 4 denotes a synchronous DRAM control signal, which is the synchronous DRAM 11
It depends on the specifications of.

Reference numeral 5 denotes a first circuit, which is the memory control device 1
The enable signal 7 output from 0 is used as an input signal,
A strobe signal 8 instructing that the data is taken in from the data bus and used for calculating the error correction code is output. The strobe signal 8 is given a code of 0 to s-1 to indicate the distinction of the signal lines. The number s of strobe signals is equal to the number of bits of each error correction code generated by the second circuit. The timing at which the strobe signal 8 is output is determined so that the second circuit generates the error correction code by the extended Hamming code. The first circuit also outputs an initialization signal 9 that sets an initial state at the start of error correction code calculation.

Reference numeral 6 denotes a second circuit, which sequentially receives data from each signal line of the data bus 1 with a control signal composed of a plurality of strobe signals 8 and an initialization signal 9 indicating the timing at which the data should be taken in as an input signal. Then, an error correction code based on the extended Hamming code is calculated and output for each signal line. Reference numeral 10 is a memory control circuit that controls reading and writing of data sent and received on the data bus to and from the synchronous DRAM 11.

The memory control circuit 10 also outputs an enable signal 7 which indicates that valid data is being sent to the data bus. Next, a configuration example of the second circuit is shown.
As an example, a case will be described in which a 7-bit error correction code is generated from 32-bit data by an extended Hamming code (l = 7).

FIG. 2 shows the internal details of the second circuit 6. The terminal code indicated by the circuit block A in the figure is the same as the terminal code of all the other circuit blocks, and the operation of the circuit is also the same. In the circuit block A, I is an initialization signal 9, S is a strobe signal 8, D is a data bus 1, Q.
Is a terminal code for exchanging the output signal of the error correction code.

Regarding the block numbers assigned to the respective circuit blocks, (0,0) to (0,6) represent the seven circuit blocks in the 0th row to the 0th column to the 6th column. (N-1,
0) and (n-1, 6) represent the seven circuit blocks in the 0th column to the 6th column of the (n-1) th row.

0- (n- of the data bus which started the transfer
For each signal line of 1), the parity is generated by the seven circuit blocks in each row, and when the transfer of 32 words is completed, the signal lines of each data bus of 0 to (n-1) A 7-bit error correction code based on the extended Hamming code is calculated and output. By using a predetermined extended Hamming code (FIG. 4 described later), it is possible to specify the occurrence position of a 1-bit error in the 32-bit data transferred by each of the n signal lines of the data bus. , The error correction code output by the second circuit can be used. (This theory has already been announced) FIG. 3 shows an operation example in which the output makes a state transition with respect to an input signal to the circuit block A.

In the circuit block A, the strobe signal S is H.
The number of times that the data D at the (level) is H (level) is counted and a parity bit is generated. In the example of FIG. 3, odd parity is generated. Next, a method of deciding the strobe signal so that the output of the second circuit 6 becomes the error correction code by the n sets of extended Hamming codes after the data transfer of 32 words will be described.

FIG. 4 shows an example of an extended Hamming code generation algorithm. Bit 0 of the error correction code is obtained from the parity of the bit marked with X in the first row of FIG. 4 among the 32 bits of data. Similarly, bits 1 to 6 of the error correction code are also obtained by the parity of the bits of the data marked with X in the corresponding row.

FIG. 5 shows a time chart in the case where an error correction code is output each time 32 words of data are burst-transferred. Strobe signals 0 to 6 in FIG.
Respectively correspond to bits 0 to 6 of the error correction code. When the i-th word (i = 0 to 31) is transferred onto the data bus, each strobe signal is marked with an X mark in the column of the i-th bit of the data in the row of bits of the corresponding error correction code in FIG. If it is, H (level) is output, and if it is not, L (level) is output. When valid data is not transferred on the data bus, each strobe signal outputs the same level as when the 0th word is transferred. Next, the operation of generating the error correction code will be described with reference to the time chart of FIG.

A. The enable signal H (level) is output only while the memory controller 10 transfers valid data on the data bus. The first circuit 5 outputs L (level) as the initialization signal only for 31 clocks from the clock next to the clock that detects that the enable signal and the initialization signal are both H (level). The strobe signal is output as described above.

B. Since the initialization signal is H (level) when the 0th word appears on the data bus, 7
Bits 0 to 3 and 6 of each error correction code
Are initialized by the level of the signal line of the data bus corresponding to the 0th word. Bits 4 to 5 of the error correction code are initialized to L. C. While the 1st word to the 31st word appear on the data bus, each bit of the error correction code is inverted only when the strobe signal is H (level).

D. As described above, the error correction code is updated for each of the 1st to 31st words for each signal line of the data bus, and one cycle is started for one clock from the rising edge of the clock when the 31st word appears on the data bus. (32
During word transfer), an effective error correction code for the data transferred on each signal line of the data bus is output.

E. A broken line shows a signal change when the burst transfer is not completed and another 32 words are continuously transferred. The first circuit 5 outputs the initialization signal L for 31 clocks.
After setting to (level), the value is returned to H (level), but when it is detected that the enable signal 7 remains H (level), 1
After the clock, the initialization signal is set to L (level) and the generation of the next error correction code is immediately started.

[0026]

The present invention has the following effects. I. Since the parity generation circuit is realized by a set of small-scale synchronization circuits that sequentially take in data bit by bit, it is possible to meet the demand for high-speed data transfer. B. Even if the width of the data bus is small, the error correction code can be added efficiently, so that the unit of memory expansion can be reduced. (If the bus width is 8 bits, it will be 1/4 the extension unit of 32 bits.) C. Since the data transfer and the error correction code generation are executed in parallel, the high speed performance of the burst transfer is not impaired.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration of a second circuit.

3 is a diagram showing an example of state transition of a circuit block A. FIG.

FIG. 4 is a diagram showing an example of an extended Hamming code generation algorithm.

5 is a diagram showing a time chart when an error correction code is generated for each transfer of 32 words using the algorithm shown in FIG.

[Explanation of symbols]

 1 Data Bus 2 Address Bus 3 Clock Signal (Line) 4 Synchronous DRAM Control Signal (Line) 5 First Circuit 6 Second Circuit 7 Enable Signal 8 Strobe Signal 9 Initialization Signal 10 Memory Control Device 11 Synchronous DRAM

Claims (1)

[Claims] 1. A timing for fetching data from a data bus and using it for calculating an error correction code, using an enable signal output from a memory control device as an input signal while valid data is being sent on the data bus, A first circuit that outputs a predetermined number of strobe signals that are instructed based on a predetermined algorithm and an initialization signal that sets an initial state at the start of error code calculation; and the strobe signal and the initialization signal as input signals, An error correction code generation device for a burst transfer memory, comprising: a second circuit for sequentially fetching data from a data bus, calculating an error correction code for each signal line of the data bus, and outputting the error correction code.