JPH08279756A - Digital data processing circuit - Google Patents

Abstract

PURPOSE: To provide a digital data processing circuit of a simple configuration and less power consumption. CONSTITUTION: The data supplied to an input terminal 2 of a digital data processing circuit 11 of a C-MOS are supplied to a terminal (a) of a switch 12 and a terminal (b) of a switch 13. Foxed data, whose signal level is constant, are supplied to the terminal (b) of the switch 12 and the terminal (a) of the switch 13. When an 'encoder mode' is selected, based on a signal MS, the movable terminals of switches 5, 12 and 13 are turned to the (a) side. The supplied data are encoded by an encoder circuit 3, passed through the switch 5 and a common circuit 6 to be outputted from an output terminal 7. The fixed data are supplied through the switch 13 to a decoder part 4 and power consumption is reduced. At the time of 'decoder mode', the movable terminals of switches 5, 12 and 13 are turned to the (b) side. The data are decoded by the decoder circuit 4, passed through the switch 5 and the circuit 6 and outputted from the terminal 7. The fixed data are supplied though the switch 12 to the encoder part 3 and power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data processing circuit. Specifically, of the plurality of circuit blocks that process digital data, it is assumed that the digital data is input only to the used circuit blocks and the fixed data is input to the unused circuit blocks to reduce the power consumption of the unused circuit blocks. By reducing the power consumption, the power consumption of the digital data processing circuit is reduced.

[0002]

2. Description of the Related Art In a conventional digital data processing circuit,
2. Description of the Related Art There is known a circuit block for digital data processing, for example, one in which two circuit blocks, an encoder circuit for encoding digital data and a decoder circuit for decoding encoded digital data, are provided in one integrated circuit. There is.

FIG. 2 shows the configuration of a digital data processing circuit having two circuit blocks, an encoder circuit and a decoder circuit. This digital data processing circuit has two functions: an "encoder mode" in which input digital data is encoded and output by an encoder circuit, and a "decoder mode" in which input digital data is decoded and output by a decoder circuit. I have.

In FIG. 2, the digital data processing circuit 1 is composed of a complementary metal oxide semiconductor (C-MOS), and the data input terminal 2 of the digital data processing circuit 1 has digital data or encoded data. Digital data is supplied from an external device. The digital data supplied to the data input terminal 2 is the encoder circuit 3
Is supplied to the decoder circuit 4.

In the encoder circuit 3, the supplied digital data is encoded and the terminal a of the signal changeover switch 5 is encoded.
Is supplied to. In the decoder circuit 4, the supplied digital data is decoded and the terminal b of the signal changeover switch 5 is decoded.
Is supplied to. The movable terminal of the signal changeover switch 5 is connected to the common circuit 6, and the common circuit 6 controls the output timing of the digital data selected by the signal changeover switch 5, and the digital data is output from the data output terminal 7. Is output.

The changeover control of the signal changeover switch 5 is performed based on the mode changeover signal MS supplied to the mode changeover terminal 8 from the outside. For example, when the "encoder mode" is selected and the mode switching signal MS is set to the low level "L", the movable terminal of the signal switching switch 5 is set to the terminal a side. Therefore, the digital data encoded by the encoder circuit 3 is output from the data output terminal 7. Also, when the "decoder mode" is selected, the mode switching signal MS
Is set to the high level "H", the movable terminal of the signal changeover switch 5 is set to the terminal b side. Therefore, the digital data decoded by the decoder circuit 4 is output from the data output terminal 7.

The power supply of the digital data processing circuit 1 is supplied from the power supply terminal 9. Further, the digital data processing circuit 1 is grounded by the ground terminal 10.

[0008]

By the way, in the above-mentioned digital data processing circuit, the digital data is stored in the encoder circuit 3 and the decoder circuit 4 regardless of whether the "encoder mode" or the "decoder mode" is selected. Is supplied. Therefore, the encoder circuit 3
Since the digital data processing is performed by both the decoder circuit 4 and the decoder circuit 4, the digital data processing circuit 1
It was supposed to consume a lot of electricity.

Further, as shown in FIG. 3, the encoder circuit 3
Power is supplied to the decoder circuit 4 from the power supply terminal 9a.
The digital data processing circuit 1a is configured so that power is supplied from the power supply terminal 9a and a power supply terminal 9b of a different system, and when the "encoder mode" is selected, the power supply to the decoder circuit 4 which is not used is Stop the supply,
When the "decoder mode" is selected, the power supply to the unused encoder circuit 3 may be stopped to reduce the power consumption of the digital data processing circuit 1a. However, in this method, the power supply lines of the encoder circuit 3 and the decoder circuit 4 need to be separated from each other, and the structure becomes special and complicated, and the number of terminals increases, which causes a cost increase. .

Therefore, the present invention provides a digital data processing circuit which has a simple structure and consumes less power.

[0011]

A digital data processing circuit according to the present invention has a plurality of circuit blocks for processing digital data, and only the circuit blocks used among the plurality of circuit blocks are used. Digital data is input, and fixed data is input to unused circuit blocks.

[0012]

According to the present invention, the digital data is supplied only to the circuit blocks required for processing the digital data, and the signal level of the other circuit blocks is high level "H" or low level "L". Fixed data fixed to either one is supplied. For this reason,
It is possible to reduce the power consumption of the circuit block to which the fixed data is supplied.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of a digital data processing circuit according to the present invention will be described below with reference to FIG. Note that, in FIG. 1, portions corresponding to those in FIG. 2 are denoted by the same reference numerals.

In FIG. 1, the digital data supplied to the data input terminal 2 of the digital data processing circuit 11 composed of C-MOS is supplied to the terminal a of the signal changeover switch 12 and the terminal b of the signal changeover switch 13. It Further, the terminal b of the signal changeover switch 12 and the signal changeover switch 1
For example, the signal level at the terminal a of 3 is high level "H".
Alternatively, fixed data fixed to the low level “L” is supplied. The movable terminal of the signal changeover switch 12 is connected to the encoder circuit 3, and the movable terminal of the signal changeover switch 13 is connected to the decoder circuit 4.

In the encoder circuit 3, the supplied digital data is encoded and the terminal a of the signal changeover switch 5 is encoded.
Is supplied to. In the decoder circuit 4, the supplied digital data is decoded and the terminal b of the signal changeover switch 5 is decoded.
Is supplied to. The movable terminal of the signal changeover switch 5 is connected to the common circuit 6, and the output timing of the digital data selected by the signal changeover switch 5 is controlled by the common circuit 6 as described above, and the data output terminal 7 To output digital data.

The changeover control of the signal changeover switches 5, 12, 13 is performed based on the mode changeover signal MS supplied to the mode changeover terminal 8 from the external device. The power of the digital data processing circuit 11 is supplied from the power supply terminal 9. Further, the digital data processing circuit 11 is grounded by the ground terminal 10.

Next, the operation will be described. For example, when the "encoder mode" is selected and the mode changeover signal MS is set to the low level "L", the signal changeover switch 5,
The movable terminals 12 and 13 are on the terminal a side, respectively. Therefore, the digital data supplied to the data input terminal 2 is encoded by the encoder circuit 3 and output from the data output terminal 7 via the common circuit 6. Further, since the fixed data of the terminal a of the signal changeover switch 13 is supplied to the decoder unit 4, the switching operation in the decoder unit 4 is reduced and the power consumption is reduced.

When the "decoder mode" is selected and the mode changeover signal MS is set to the high level "H", the movable terminals of the signal changeover switches 5, 12 and 13 are set to the terminal b side. Therefore, the digital data supplied to the data input terminal 2 is decoded by the decoder circuit 4 and output from the data output terminal 7 via the common circuit 6. At this time, since fixed data having a constant signal level supplied to the terminal b of the signal changeover switch 12 is supplied to the encoder unit 3, the power consumed by the encoder unit 3 is reduced.

As described above, according to the above-described embodiment, the circuit block which is not used is supplied with fixed data whose signal level is the high level "H" or the low level "L", and this circuit block is supplied. Since the power consumed by the digital data processing circuit is reduced, the power consumption of the digital data processing circuit can be reduced. Particularly, when the processing speed of the encoder unit 3 and the decoder unit 4 is high, the power consumed for processing the digital data is large. Therefore, it is possible to further reduce the power consumption by supplying the fixed data. it can.

The circuit block of the digital data processing circuit is not limited to the encoder circuit and the decoder circuit shown in the embodiments, and other functions such as a data encoding / decoding circuit or an error detection / correction circuit are provided. It goes without saying that it may be a circuit block having

[0021]

According to the present invention, the digital data is input only to the circuit block used for processing the digital data, and the signal level is high level "H" or low level "L" in the circuit blocks not used. "
Fixed data is supplied to either one of
Power consumption of unused circuit blocks is reduced. Therefore, the number of terminals is not increased by making the structure of the digital data processing circuit special and complicated, and it is possible to easily provide the digital data processing circuit with low power consumption without increasing the cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a digital data processing circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a conventional digital data processing circuit.

FIG. 3 is a diagram showing a configuration of a conventional digital data processing circuit.

[Explanation of symbols]

 1, 1a, 11 Digital data processing circuit 2 Data input terminal 3 Encoder circuit 4 Decoder circuit 5, 12, 13 Signal changeover switch 6 Common circuit 7 Data output terminal 8 Mode changeover terminal

Claims (2)

[Claims] 1. A plurality of circuit blocks for processing digital data, wherein the digital data is input only to a circuit block that is used among the plurality of circuit blocks, and fixed data is input to a circuit block that is not used. A digital data processing circuit characterized by inputting. 2. The digital data processing circuit according to claim 1, wherein the plurality of circuit blocks are composed of complementary metal oxide film semiconductors.