JPH08274551A - Operational amplifier - Google Patents

Abstract

PURPOSE: To reduce the area occupied by a chip in the case of making an operational amplifier into an IC. CONSTITUTION: When a positive input voltage is impressed to a positive phase input terminal 11 in respect to a negative phase input terminal 12, a signal is amplified with the same phase as the input voltage by a differential amplifying step 10 and outputted to a node N1. The level of that signal is shifted forward just for the voltage change component of the node N1 by a first level shift step 20 and the signal is outputted to a node N2. The voltage change component of the node N2 is amplified with the reverse phase by a first amplifying step 30 and outputted to a node N3. The level of that signal is shifted backward just for the voltage change component of the node N3 by a second level shift step 40 and the signal is outputted to the gate of a PMOS 71 inside an output step 70. The voltage change component of the output side node N1 is amplified with the reverse phase (in the negative direction) by a second amplifying step 50 and outputted to a node N5. Even when the voltage of the node N5 is fluctuated almost to a negative power source, the voltage of a node N6 is not lowered rather than a threshold voltage by an NMOS 61 and an NMOS 72 is not turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier which is formed on an integrated circuit by CMOS and used for addition and subtraction of analog signals, and in particular, an operational amplifier which can output an output voltage close to a power supply voltage even for a low resistance load. It is about.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, some documents were described in the following documents. Reference: Japanese Patent Application Laid-Open No. 5-152870. In the above reference, an input signal is differentially amplified by a differential amplification stage, and an output of the differential amplification stage is level-shifted by a level shift stage. First load M composed of a diode
A first amplification stage having an OS amplifies the output of the level shift stage and gate-controls a P-channel MOS transistor (hereinafter referred to as PMOS) forming the output stage. An N-channel MOS transistor (hereinafter referred to as N-channel MOS transistor) (hereinafter referred to as N
(Referred to as MOS). The phase compensating means impedance-converts the respective outputs of the first and second amplification stages, and the capacitors feed back to the differential amplification stage.

[0003]

However, the conventional operational amplifier has the following problems. Since the load element of the first and second amplification stages is a MOS diode connection in which the gate and the source are connected, the equivalent resistance value is small, so the amplification degree of the first and second amplification stages becomes small, and the output stage In order to make a large current flow through, it was necessary to increase the ratio of the channel width (W) / channel length L of the transistor in the output stage in order to increase the channel conductance. Therefore, there is a problem that the element of the transistor in the output stage becomes large.

[0004]

In order to solve the above-mentioned problems, a first aspect of the present invention performs a complementary operation based on a differential amplification stage for differentially amplifying an input signal and an output of the differential amplification stage. In an operational amplifier including a P-channel transistor whose source is connected to the first power supply potential and an output stage having an N-channel transistor whose source is connected to the second power supply potential, the following means are provided. That is, the output of the differential amplification stage or a first amplification stage that amplifies the signal whose level is shifted in the direction of the second power supply potential in opposite phase, and the output of the differential amplification stage or the output A second amplification stage that amplifies a signal level-shifted in the direction of the first power supply potential in anti-phase, and an output of the first amplification stage is level-shifted in the direction of the first power supply potential and the P A first level shift stage for controlling the gate of the channel transistor, and a second level shift stage for controlling the gate of the N channel transistor by level shifting the output of the second amplifying stage in the direction of the first power supply potential. And are provided.

[0005]

According to the first aspect of the invention, since the operational amplifier is configured as described above, the differential amplifying stage differentially amplifies the input signal. The first and second amplification stages amplify the output of the differential amplification stage or the level-shifted signal of the output in anti-phase. If the amplification degree of the first and second amplification stages is large, the output may swing to near the first power supply potential and the second power supply potential. The first and second level shift stages level-shift the outputs of the first and second amplification stages to output PMOS and NMOS.
Is not in the off area. Therefore, the above problem can be solved.

[0006]

1 is a circuit diagram showing an operational amplifier according to an embodiment of the present invention. The operational amplifier of the present embodiment is different from the conventional operational amplifier in that first, the gate of the first amplifier stage 30 is biased to the bias voltage V _b2 and the source thereof is the positive power supply V ^{+ serving} as the first power supply potential. High resistance PMOS connected to
A high resistance NMOS 52 having a gate biased to the bias voltage V _b1 and a source connected to the negative power supply V ₋ as the second power supply potential is used in the second amplification stage 50. Is the higher. Second, by increasing the amplification degree, the voltage of the node N3 of the first amplification stage 30 and the voltage of the node N5 of the second amplification stage 50 are close to the positive power supply V ⁺ and the negative power supply V ⁻ , respectively. In order to prevent the PMOS 71 and the NMOS 72 of the output stage 70 from being in the off region, the levels thereof are respectively set to the negative power supply V
^- , That is, the second and third level shift stages 40 and 60 for level shifting in the direction of the positive power source V ⁺ are provided.

As shown in FIG. 1, the operational amplifier includes a differential amplifier 10, a first level shift stage 20, a first amplification stage 30, a second level shift stage 40, and a second amplification stage 5.
0, a third level shift stage 60, a first source follower stage 80, and a second source follower stage 90. The differential amplifier stage 10 performs differential amplification according to the input voltage difference between the positive-phase input terminal 11 and the negative-phase input terminal 12 and outputs it to the node N1.
4. NMOS 15 for constant current source and PMOS for load
It is composed of 16 and 17. The gates of the NMOSs 13 and 14 are connected to the positive phase input terminal 11 and the negative phase input terminal 12, respectively. The sources and substrates of the NMOSs 13 and 14 are commonly connected to the drain of the NMOS 15. The gate of the NMOS 15 is connected to the bias voltage V _b1, and the source of the NMOS 15 is connected to the negative power supply V ₋ . The gates of PMOS 16 and 17 are PMOS 16
And the drain of the NMOS 13. The drain of PMOS 17 is NM
It is connected to the drain of the OS 14 and also to the node N1. The first level shift stage 20 level-shifts the voltage on the node N1 in the negative power supply V ⁻ direction and outputs it to the node N2.
3. The drain of the NMOS 21 is connected to the positive power source V ⁺ , the gate is connected to the node N1, and the substrate and source are connected to the drain and gate of the NMOS 22. The source of the NMOS 22 is connected to the node N2 and the drain and gate of the NMOS 23. The source of the NMOS 23 is connected to the negative power supply V ⁻ .

The first amplifying stage 30 amplifies the voltage of the node N2 in reverse phase and outputs it to the node N3.
It is composed of an OS 31 and a PMOS 32. NMO
The gate of S31 is connected to the node N2, and the drain is P
It is connected to the drain of the MOS 32 and the node N3, and the source thereof is connected to the negative power supply V ⁻ . PMOS3
The gate of ₂ is connected to the bias voltage V _b2 , and the source thereof is connected to the positive power supply V ⁺ . The second level shift stage 40 level-shifts the voltage of the node N3 in the direction of the negative power supply V ⁻ and outputs it to the node N4.
PMOS 41 and NMOS 42 connected by S diode,
It is composed of a capacitor 43. The source of the PMOS 41 is connected to the node N3, the gate and drain of the PMOS 41 are connected to the node N4, and NM
Connected to the drain of OS42. The gate of the NMOS 42 is connected to the bias voltage V _b1 , and the source thereof is connected to the negative power source V ^−, which works as a constant current source. The capacitor 43 is
It is connected to the source and drain of the PMOS 41. The second amplification stage 50 amplifies the voltage of the node N1 in reverse phase and outputs it to the node N5.
It is composed of the OS 52. The gate of the PMOS 51 is connected to the node N1, and the drains thereof are the nodes N5 and N.
The drain and source of the MOS 52 are connected to the positive power source V ⁺ , respectively. The gate of the NMOS 52 is connected to the bias voltage V _b1 , and the source is connected to the negative power supply V ⁻ . The third level shift stage 60 level-shifts the voltage of the node N5 in the direction of the positive power supply V ⁺ and outputs it to the node N6.
It is composed of S61, PMOS 62, and capacitor 63. The source of the NMOS 61 is connected to the node N5, and the gate and drain thereof are connected to the node N6 and the drain of the PMOS 62. PMOS
The gate of 62 is a bias voltage V _b2 , and the source is a positive power supply V
Each is connected to ⁺ and acts as a constant current source. The capacitor is connected to the source and drain of the NMOS 61.

The output stage 70 outputs an output voltage driven by the voltages of the nodes N4 and N6 to the output terminal 73, and is composed of a PMOS 71 and an NMOS 72. The source of the PMOS 71 is the positive power supply V ⁺ ,
The gate is the node N4, and the drain is the output terminal 73 and N.
It is connected to the drain of the MOS 72. NMOS 72
Has its gate connected to the node N6 and its source connected to the negative power supply V ⁻ . The first source follower stage 80 is a phase compensation means for preventing oscillation, and includes an NMOS 81 and an NMOS.
82 and a capacitor 83. NMOS
The drain of 81 is the positive power supply V ⁺ , and the gate is the node N4.
And the source and substrate are the nodes N8 and NMO.
It is connected to the drain of S82. The NMOS 82 has a gate connected to the bias voltage V _b1 and a source connected to the negative power supply V ⁻ , and the capacitor 83 has a node N8 and a node N.
It is connected between 1. The second source follower stage 90 is a phase compensation means for preventing oscillation, and includes a PMOS 91 and a PMOS 91.
It is composed of a capacitor 92 and a capacitor 93. PMOS
The drain of 91 is a negative power supply V ⁻ , and the gate is a node N6.
, The sources are connected to the node N9, and the PMOS
The source of 92 is the positive power supply V ⁺ , and the gate is the bias voltage V
_{The b2} and drain are respectively connected to the node N9, and the capacitor 93 is connected between the node N9 and the node N1. FIG. 2 is a waveform diagram of FIG.
2 is a waveform diagram of the waveform of the node N1, the nodes N1 to N6, and the output terminal 73. The operation of FIG. 1 will be described below with reference to FIG.

(A) Current supply operation to output load When a positive input voltage is applied to the positive-phase input terminal 11 with respect to the negative-phase input terminal 12, the resistance of the NMOS 13 of the differential amplifier 10 becomes small and becomes constant. Since a constant current flows through the current source 15, a larger current flows through the NMOS 13 as compared with the PMOS 14. Therefore, the voltage drop of the PMOS17 becomes smaller, the input voltage is amplified by the input and common mode (forward), and is output to the node N1 (N1 in FIG. 2). The first level shift stage 20 is a source follower, and its voltage gain is about 1. NMOS21,
The diode-connected NMOSs 22 and 23 level shift the voltage of the node N1 in the direction of the negative power supply V ⁻ (first level shift in FIG. 2), and in-phase with the change of the node N1. 2 to N2 ). Here, the NMOS 22 causes a constant voltage drop,
It functions to prevent an excessive current from flowing when the positive power supply V ⁺ rises. In the first amplification stage 30, when the voltage of the node N2 increases, the voltage between the gate and the source of the NMOS 31 increases and the resistance value of the NMOS 31 decreases. Therefore, the voltage drop of the NMOS 31 becomes small and the PMO
The voltage between the source and drain of S32 increases. That is, in the first amplifier stage 30 amplifies the voltage change of the node N2 in opposite phase, and outputs to the node N3 (N3 in FIG. 2). Since the gate of the PMOS 32 is biased to the bias voltage V _b2 and its resistance value is large, the amplification degree of the first amplification stage 30 becomes large. Here, what the output of the first level shift stage 20 rather than the output of the differential amplifier stage 10 to the gate input of NMOS31 the negative power supply V to the output of the differential amplifier stage 10, as shown in Figure 2 ^- of This is because the source-gate voltage of the NMOS 31 is reduced by level shifting in the direction to reduce the steady current consumption of the first amplification stage 30.

The second level shift stage 40 has a voltage gain of approximately one. The voltage of the node N3 drops due to the diode-connected PMOS 41 and NMOS 42. NMOS
Since 42 is a constant current source, a constant current flows in the PMOS 41, so that the voltage drop (second level shift in FIG. 2) of the PMOS 41 is constant. Since the PMOS 41 is diode-connected, this voltage drop becomes larger than the threshold voltage of the PMOS 41 due to the characteristic peculiar to the transistor. That is, in the second level shift stage 40, the voltage of the node N3 is level-shifted in the direction of the negative power supply V ⁻ , and the voltage change of the node N3 is in-phase,
PM node N4 output stage 70 via the (N4 in Figure 2)
Output to the gate of OS71. The PMOS 41 has a load capacitance (source / gate capacitance, gate / drain capacitance, etc.) not shown, and the phase of the signal input to the gate is delayed by the load capacitance and the resistance of the PMOS 41. Since the capacitor 43 is provided between the input side and the output side of the PMOS 41, its delay becomes short and phase compensation is performed. The gate-source voltage of the PMOS 71 of the output stage 70 increases, and current is supplied to the output load connected to the output terminal 73. Moreover, due to the amplification by the first amplification stage 30 and the level shift toward the negative power supply V ⁻ by the second level shift stage 30, the gate of the PMOS 71 is
The source-to-source voltage becomes larger. Therefore, PMOS7
1 has a larger drain current and the load resistance connected to the output terminal 73 has a low resistance, the drain of the operating point of the PMOS 71 in the characteristic curve of the drain current and the drain voltage determined by the gate-source voltage at that time The voltage rises to near the positive power supply V ⁺ .

During the operation of the PMOS 71, the voltage of the output node N4 of the second level shift stage 40 is impedance-converted by the first source follower stage 80 having a voltage gain of about 1, and the differential voltage is generated by the first capacitor 83. Amplification stage 1
0 is fed back to the output side node N1. Since the change in the voltage of the node N4 fed back to the node N1 has a reverse phase with respect to the change in the voltage of the node N1, a high frequency component that oscillates is canceled and oscillation is prevented. On the other hand, the output stage 7
Explaining the NMOS 72 in 0, the second amplification stage 50 amplifies the voltage change amount of the output side node N1 of the differential amplification stage 10 in the negative phase (negative direction) and outputs it to the node N5.
The third level shift stage 60 has a voltage gain of about 1, level shifts the voltage of the node N5 toward the positive power supply V ⁺ , and outputs the voltage to the gate of the NMOS 72 via the node N6. As a result, the gate-source voltage of the NMOS 72 becomes smaller, and the drain current of the NMOS 72 becomes smaller. At this time, even if the voltage of the node N5 swings to substantially the negative power supply V ⁻ due to the amplification operation of the second amplification stage 50, the NMOS 6
Since 1 is a drain-gate connected MOS diode connection, the voltage between the node N5 and the node N6 (NMO
The source-gate voltage of S61) does not become lower than the threshold voltage peculiar to the transistor of the NMOS 61. Therefore, the NM having the same characteristics as the NMOS 61
Since the gate-source voltage of the OS 72 does not become lower than the threshold voltage, the NMOS 72 is never turned off. That is, in the NMOS 72, even when a positive input voltage is applied to the positive-phase input terminal 11 with respect to the negative-phase input terminal 12, a small amount of current flows through the NMOS 72.

(B) Current absorption operation from output load When a negative input voltage is applied to the positive phase input terminal 11 with respect to the negative phase input terminal 12, a large amount of current flows through the NMOS 14 due to the input voltage. , Amplified in phase (negative direction),
It is output from the node N1. In the second amplification stage 50, when the voltage of the node N1 decreases, the voltage between the gate and the source of the PMOS 51 increases, the resistance value of the PMOS 51 decreases, the voltage drop of the PMOS 51 decreases, and P
The drain voltage of the MOS 51 becomes high. Therefore, the voltage change of the node N1 is amplified with reverse phase (forward), and is output to the node N5 (N5 in FIG. 2). Since the gate of the NMOS 52 is biased to the bias voltage V _b1 and its resistance value is large, the amplification degree of the second amplification stage 50 becomes large. The third level shift stage 60 has a voltage gain of about 1. The voltage at node N5 is diode-connected NMO
It rises due to S61 and PMOS 62. PMOS 62
Is a constant current source, a constant current flows through the NMOS 61, so the voltage of the NMOS 61 (the third level shift in FIG. 2) is constant. This voltage is NMOS
Since 61 is diode-connected, the threshold voltage of the NMOS 61 becomes higher than that of the NMOS 61 due to the characteristic peculiar to the transistor. That is, the third level shift stage 60
In, level shift the voltage of the node N5 to the positive supply V ⁺ direction, the node N6 through (N6 in FIG. 2) output stage 7
Output to the gate of the NMOS 72 of 0. Capacitor 63
Is provided between the input side and the output side of the NMOS 61, the delay is shortened and the phase is compensated. As a result, the gate-source voltage of the NMOS 72 increases, and the current is drawn from the output load connected to the output terminal 73. Moreover, due to the amplification by the second amplification stage 50 and the level shift toward the positive power supply V ⁺ by the third level shift stage 60, the gate-source voltage of the NMOS 72 becomes larger. Therefore, the drain current of the NMOS 72 becomes larger, and even if the load resistance connected to the output terminal 73 has a low resistance, the operating point of the NMOS 72 in the characteristic curve of the drain current and the drain voltage determined by the gate-source voltage at that time. Drain voltage drops to near the negative power supply V ⁻ .

At this time, since the source-gate voltage of the PMOS 71 in the output stage 70 becomes small, the PMOS 71 becomes
Drain current becomes smaller. Here, since the second level shift stage 40 has the MOS diode of the PMOS 41, the voltage of the node N4 does not become lower than the threshold voltage peculiar to the transistor of the PMOS 41, and therefore the PMOS 71 having the same characteristic is set to the off region. Never. Further, when the NMOS 72 in the output stage 70 operates, the voltage of the output side node N6 of the third level shift stage 60 is impedance-converted by the second source follower stage 90, and the second capacitor 93 causes the differential amplification stage 10 to operate.
Is fed back to the output side node N1. Therefore, the oscillating operation of the operational amplifier can be properly prevented. As described above, since the PMOS 71 and the NMOS 72 in the output stage 70 each have a region that is not turned off, the output voltage of the output terminal 73 smoothly shifts from positive to negative and from negative to positive. The crossover distortion of is small.
As described above, this embodiment has the following advantages.

(A) The second level shift stage 4 is provided between the output stage 70 and the first amplification stage 30 and the second amplification stage 50 which drive the PMOS 71 and the NMOS 72 in the output stage 70.
Since the 0th and third level shift stages 60 are provided, crossover distortion is small, and an output voltage with a large amplitude can be supplied to a low resistance output load. (B) The second level shift stage 40 and the third level shift stage 60 are drain-gate connected MO biased by the constant current sources of the PMOS 41 and the NMOS 61.
Since it is configured by the S diode, the amplification degree of the first amplification stage 30 and the second amplification stage 50 which is the preceding stage can be made large, so that the ratio of the channel length and the channel width of each of the PMOS 71 and the NMOS 72 in the output stage 70 can be set. Even if it is not large, a large current can flow through the output terminal 73, so that an increase in the chip occupying area can be suppressed when integrated into an IC. (C) Since the third capacitor 43 and the fourth capacitor 63 are provided in the second level shift stage 40 and the third level shift stage 60 in order to compensate for the phase delay of the signal, the oscillation operation of the operational amplifier is prevented. It can be prevented.

The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) When the potential of the node N1 of the differential amplifier stage 10 is level-shifted to the potential of the negative power supply, the first level shift stage can be omitted. Instead, the second
A signal obtained by level-shifting the potential of the differential amplification stage 10 to the potential of the positive power supply may be input to the gate input of the PMOS 51 of the amplification stage 50 of FIG. (2) The first and second source follower stages 80, 90 are
A gain of 1 may be used. (3) The second and third level shift stages 40 and 60 are
Even if the potentials of the nodes N3 and N5 of the first and second amplification stages 30 and 50 swing to the positive potential V ⁺ and the negative potential V ⁻ , respectively, P
Other diodes may be used as long as the source-gate potential drops so as to be higher than the threshold voltage so that the MOS 71 and the NMOS 72 are not turned off. (4) The negative power supply V ⁻ may be ground potential. Further, even if the negative power supply V ⁻ and the positive power supply V ⁺ in FIG. 1 are replaced with each other, and the circuit configuration is changed such that the NMOS is replaced with the PMOS and the PMOS is replaced with the NMOS, the same advantages as those of the above-described embodiment can be obtained.

[0017]

As described in detail above, the first to sixth aspects
According to the invention, since the second and third level shift stages are provided between the first and second amplification stages and the output stage, crossover distortion is small and a large amplitude output voltage can be output. it can. Further, the first and second amplification stages having a large amplification degree can be used, and the chip area can be reduced when the operational amplifier is integrated into an IC.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an operational amplifier according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of FIG.

[Explanation of symbols]

 10 differential amplifier 20 first level shift stage 30 first amplification stage 40 second level shift stage 50 second amplification stage 60 third level shift stage 70 output stage 80 first source follower stage 90 second Source Follower Dan

Claims (6)

[Claims] 1. A differential amplifier stage for differentially amplifying an input signal,
An output stage having a P-channel transistor whose source is connected to a first power supply potential and an N-channel transistor whose source is connected to a second power supply potential, which perform complementary operations based on the output of the differential amplification stage; An operational amplifier comprising: a first amplification stage for amplifying an output of the differential amplification stage or a signal obtained by level-shifting the output in the direction of the second power supply potential in anti-phase; and an output of the differential amplification stage. Alternatively, a second amplification stage that amplifies a signal obtained by level-shifting the output in the direction of the first power supply potential in anti-phase, and a level shift of the output of the first amplification stage in the direction of the second power supply potential. A first level shift stage for controlling the gate of the P-channel transistor, and an output of the second amplifying stage for level-shifting in the direction of the first power supply potential to control the gate of the N-channel transistor. A second level shift stage according to the present invention. 2. A P-channel transistor having a source connected to the first power supply potential and a gate connected to a first bias potential, and a source connected to the second power supply potential in the first amplification stage. The gate of the differential amplifier is connected to the gate of the differential amplifier stage or the output of the differential amplifier stage is level-shifted in the direction of the second power supply potential.
The operational amplifier according to claim 1, further comprising an N-channel transistor connected to a drain of the channel transistor, wherein the drain of the P-channel transistor serves as an output terminal. 3. The N-channel transistor having a source connected to the second power supply potential and a gate connected to a second bias potential, and a source connected to the first power supply potential in the second amplification stage. The gate of the differential amplifier stage is connected to the output of the differential amplifier stage or a signal obtained by level-shifting the output of the differential amplifier stage in the direction of the first power supply potential.
The operational amplifier according to claim 1, further comprising a P-channel transistor connected to a drain of the channel transistor, wherein the drain of the N-channel transistor serves as an output terminal. 4. The first level shift stage, wherein the source of the PMOS transistor is an input terminal for inputting the output of the first amplification stage, a MOS diode in which the gate and drain of the PMOS transistor are commonly connected, A constant current source for drawing a common connection point of a gate and a drain to the second power supply potential side, the common connection point serving as an output terminal, the PMOS transistor of the output stage and the first level shift The operational amplifier according to claim 1, 2 or 3, wherein the characteristics of the PMOS transistors of the stages are the same. 5. The second level shift stage, wherein the source of the NMOS transistor is an input terminal for inputting the output of the second amplification stage, and a MOS diode in which the gate and drain of the NMOS transistor are commonly connected, A constant current source connected to a common connection point of a gate and a drain and supplying a current from the first power supply potential side, the common connection point serving as an output terminal, the NMOS transistor of the output stage and the second The operational amplifier according to claim 1, 2, or 3, wherein the NMOS transistors of the level shift stage have the same characteristics. 6. The operational amplifier according to claim 4, wherein the first or second level shift stage has a capacitor provided between an input terminal and an output terminal of the MOS diode.