JPH08274428A - Power control circuit - Google Patents

Abstract

PURPOSE: To cancel magnetic field each other by performing input signal line connection for an outward path of an input signal line to a conductive layer of a forward input side end part and for an inward path of an input signal line onto a common conductive layer and performing output signal line connection for an inward path of an output signal line to a conductive layer of a forward output side end part and for an inward path of an output signal line onto a common conductive layer. CONSTITUTION: Input signal lines 51, 53, 55 of an outward path are connected to a conductive layer 32 of a forward input side end part among a plurality of conductive layers on a first main surface 42. Input signal lines 52, 53, 56 of an inward path are connected to a position on a common conductive layer 38 opposite to the conductive layer 32 of an input side end part. An output signal line 57 of an outward path is connected to a conductive layer 36 of a forward output side end part among a plurality of conductive layers on a second main surface 42. An output signal line 58 of an inward path is connected to a position on a common conductive layer 38 opposite to the conductive layer 36 of an output side end part. Since the common conductive layer 38 exists in a region opposite to a second terminal of a device connecting conductive layers 32, 34, 36 and an adjacent conductive layer, outward and inward paths of a current are opposed with a board 30 between and can cancel a magnetic field.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power control circuit for switching a large amount of electric power, and more particularly to a power control circuit having reduced inductance in circuit wiring.

[0002]

2. Description of the Related Art In recent years, it has become possible to control a large amount of electric power, which is conventionally switched using a mechanical switch such as a relay, by using a semiconductor switch. A power MOS is used as a device forming a semiconductor switch.
FETs, IGBTs (insulated gate bipolar transistors), GTOs, thyristors and the like are known. One of the advantages of such a semiconductor switch is that it can be highly controlled by a microprocessor system.

FIG. 7 shows a usage example of a semiconductor switch, and is a simplified block diagram of a device characteristic measuring circuit using an IGBT as a device under test (DUT). Of course, the device under test may be another semiconductor device. In this example, the drive circuit 12 is an IGBT (device under test, DUT).
A drive voltage is supplied to the gate of the IGBT 10 through the gate resistance Rg, and the collector-emitter voltage Vce and the current Ice of the IGBT (DUT) 10 at this time are measured.
That is, the power supply voltage 14 supplies the voltage Vcc to the collector of the IGBT 10, and the current Ice in that state is measured by the ammeter Im.
At 16, the voltage Vce is measured by the voltmeter Vm18. The analog measurement values of the ammeter Im16 and the voltmeter Vm18 are analog-to-digital converted (not shown) and stored as digital data in a storage device in a known microprocessor system. The switch SW20 is a DU if necessary.
It is provided to cut off the voltage and current supplied to T10. For example, when the measured values of the ammeter Im16 and the voltmeter Vm18 exceed a predetermined value, the power is supplied to the DUT 10 in accordance with the control of the microprocessor system, which is used for power control.

FIG. 8 shows a semiconductor switch (power control circuit).
A basic circuit example in which 20 is configured by wiring a plurality of IGBTs in a matrix is shown. In FIG. 8, the IGBT is composed of two columns and only three rows are shown, but generally m rows and n
Each IGBT can be composed of columns (m and n are arbitrary natural numbers)
Will be referred to as Tmn. T1 which is the first row IGBT
1 and T12 are connected in series by connecting the emitter of T11 and the collector of T12. The same applies to the other rows. In this case, since the number of IGBTs is two, I
Compared to the case of one GBT, it can handle up to twice the voltage. Each row is connected in parallel, and if there are m rows, one IGBT
It can handle up to m times the current compared to the case of individual pieces.

Each column of the IGBT semiconductor switch 20 is used by being divided by the voltage dividing resistors R1 and R2, and accordingly, a voltage is applied to the gate of each column in the first and second gate drive circuits 22 and 24, respectively. Supplied and driven. The first and second gate drive circuits 22 and 24 are controlled by gate control signals from the microprocessor system (not shown) described above. As shown in FIG. 7, the input terminal 26 of the semiconductor switch 20 is connected to the power supply Vcc, and the output terminal 28 is connected to the load (DUT 10 in this example).

[0006]

[Problems to be Solved by the Invention]
A power control circuit based on matrix wiring of devices or a circuit similar to this is used for controlling a large amount of power. In this case, there is a stray inductance Ls in the wiring of the circuit on the substrate. With the stray inductance Ls, the surge voltage ΔVs is generated in the relationship of ΔVs = Ls × di / dt when the current change rate due to high-speed switching or the like is set to di / dt. This surge voltage ΔVs has a risk of destroying devices (elements) on the circuit. Moreover, in the measurement of the element characteristics as shown in FIG. 7, a measurement error is caused. Therefore, in a circuit using a power device, it is an important subject to reduce the stray inductance Ls existing in the wiring of the circuit. Furthermore, if the length of the wiring path between each element of the matrix wiring circuit and the power supply is different, there will be a difference in inductance, so a transient imbalance occurs in the current flowing through each element during switching, and the expected characteristics You may not get it.

Therefore, an object of the present invention is to provide a power control circuit with reduced inductance. Another object of the present invention is to provide a power control circuit with reduced inductance imbalance.

[0008]

The power control circuit of the present invention is provided on a substrate. The first and second main surfaces of the substrate facing each other are configured as follows. On the first main surface,
A plurality of conductive layers are provided in parallel. A plurality of power devices in which the respective first and second terminals are connected in the forward direction are provided between the adjacent conductive layers. A common conductive layer is on the second major surface. It is provided in the area on the second major surface corresponding to the terminals of the power device and the plurality of conductive layers that are present between the conductive layers for connecting the adjacent conductive layers. And
Connect the forward path of the input signal line to the conductive layer at the input side end in the forward direction, connect the return path of the input signal line to a position on the common conductive layer that faces the conductive layer at the input side end, and output in the forward direction. The forward path of the output signal line is connected to the conductive layer at the side end, and the return path of the output signal line is connected to a position on the common conductive layer facing the conductive layer at the output side end in the forward direction. Depending on this, the forward path and the return path of the signal flowing through the circuit face each other across the substrate, and the magnetic fields generated by each other cancel each other out, reducing the inductance.

Further, the plurality of conductive layers on the first main surface are formed in an arc shape, and the conductive layers at the forward end on the input side are connected to the conductive layers at the forward end on the output side via the plurality of power devices. You may reduce the difference of the length of each path to a layer. As a result, the imbalance between the inductances in each path through which the signal flows is reduced.

Further, the conductive layer may be brought into contact with a contact surface (generally used for heat dissipation) electrically connected to the first terminal provided on one main surface of the power device package. Good. According to this, the current does not flow through the elongated lead-out terminal extending from the package of the power device electrically connected to the first terminal (for example, the collector), and the current flows through the contact surface having a large area. The generation of inductance can be reduced.

[0011]

1 is a view of a substrate 30 on which a power control circuit of the present invention is mounted, as viewed from the first main surface 41 side. In FIG. 1, each lead terminal from the package of each IGBT has a gate (third terminal) at the left end, a collector (first terminal) at the center, and an emitter (second terminal) at the right end. However, since the lead-out terminal of the collector (first terminal) is cut off from the root, it is extremely short. Further, FIG. 2 is a diagram of the substrate 30 viewed from the second main surface 42 side. In Figure 2,
These are indicated by broken lines in order to show the correspondence of the arrangement of the plurality of power devices on the first main surface 41. In FIGS. 1 and 2, the region of the conductive layer is shown by hatching. FIG. 3 is a sectional view taken along the broken line 8 in FIGS. 1 and 2. In this embodiment, an example using an IGBT as a power device is shown. As the IGBT to be used, for example, PO3 type, TO
There are 220 types. Note that, in FIG. 3, for convenience of description, each is illustrated thicker than it actually is.

A conductive layer 3 is formed on the first main surface 41 of the substrate 30.
2, 34 and 36 are provided in parallel. A plurality of m IGBTs are arranged in each of the conductive layers 32 and 34, and a plurality of m IGBTs in each column are connected in parallel by connecting their collectors (first terminals). Here, an example is shown in which five IGBTs are connected in parallel in each of the conductive layers 32 and 34. That is, the collectors of T11 to T51 are connected in parallel in the conductive layer 32, and the collectors of T11 to T51 are connected in parallel in the conductive layer 34. However, the number of power devices in each column is not limited to 5, and may be any other natural number.

When connecting the conductive layer and the collector, the lead terminal of the collector extending from the package of the IGBT may be used, but in a three-terminal type power device, the collector is provided on one main surface of the package of the device. (First
Some terminals have a contact surface connected to them. Usually, this collector contact surface is mainly used for heat dissipation, but it is good to connect the conductive layer and the collector by bringing the collector contact surface into contact with the conductive layer. FIG.
Indicates that the collector contact surface S31 of T31 contacts the conductive layer 32, and the collector contact surface S32 of T32 contacts the conductive layer 34. According to this, the contact area is wide,
It is possible to reduce the influence of the inductance generated at the elongated lead-out terminal of the collector coming out of the package. The collector lead-out terminal should be cut off from the root and removed if not used.

Of the adjacent conductive layers 32 and 34, one conductive layer 32 is connected to the collectors of T11 to T51 as described above, while the other conductive layer 34 serves as an emitter (second terminal) of T11 to T51. Connected. For this connection, the lead-out terminal of the emitter coming out of the package is used. Similarly, of the adjacent conductive layers 34 and 36, one conductive layer 34 is connected to the collectors of T12 to T52, and the other conductive layer 36 is connected to the emitters of T11 to T51. In this way, each power device is connected in a fixed forward direction. Thereby, the plurality of IGBTs are connected in 5 rows and 2 columns. In the embodiment shown in FIG. 1 etc., there are only two IGBT columns, but in general, any number of n columns can be used.

In FIG. 1, the bent lead-out terminal extending from the IGBT package is a gate terminal. Although not shown, the columns of transistors T11 to T51 and T12 to
The gates of T52 are commonly connected to each other and connected to a gate drive circuit as shown in FIG. The substrate on which the gate drive circuit is mounted may be installed in the housing of the device so as to be superposed on the substrate 30 on which the power control circuit according to the present invention is mounted, for example, at regular intervals. This is because if the gate drive circuit is provided on the substrate 30, the symmetry of the wiring of the substrate 30 is broken, and the balance of the inductance on the wiring is broken.

As shown in FIG. 2, the second major surface 4 of the substrate 30 is
A common conductive layer 38 is provided on the surface 2. This common conductive layer 38 corresponds to the second terminal (here, the emitter) of the power device (IGBT) existing between the conductive layers for connecting the adjacent conductive layers and the second main layer corresponding to the conductive layers 32, 34 and 36. It is provided in the area on the surface. That is, the conductive layer 3
A common conductive layer 38 is present in the area facing the second terminals of 2, 34 and 36 and the power device.

The outgoing input signal lines 51, 53 and 55 are
Of the plurality of conductive layers on the first main surface 41, it is connected to the conductive layer 32 at the input side end portion in the forward direction. The return input signal lines 52, 54, and 56 are connected to positions on the common conductive layer 38 that face the conductive layer 32 at the input end. The outgoing output signal line 57 is connected to the conductive layer 36 at the output side end portion in the forward direction among the plurality of conductive layers on the second main surface 42. The output signal line 58 on the return path is connected to the conductive layer 3 at the end on the output side in the forward direction.
6 is connected to a position on the common conductive layer 38 opposed to 6. In FIG. 3, arrows 60 to 66 show signal flows in the respective signal lines. As described above, the common conductive layer 38 is the conductive layer 3
2, 34 and 36 and the second terminal of the power device connecting the adjacent conductive layers are present in a region facing each other, the forward path and the return path of the current flowing through the circuit face each other with the substrate 30 in between, and thus the current flows. Since the magnetic fluxes generated as a result cancel each other out, the inductance can be reduced. Therefore, the substrate 30
Is effective in reducing the inductance as it becomes thinner.

FIG. 4 shows another embodiment of the present invention, in which the substrate 30 is viewed from the first main surface 41 side. FIG. 5 shows FIG.
6 is a diagram of the substrate 30 viewed from the second main surface 42 side in the example of FIG. Components corresponding to those in FIGS. 1 to 3 are denoted by the same reference numerals.

In the circuit shown in FIG. 1, for example, a path from the input signal line 53 to the output signal line 57 via T31 and T32 and a path from the input signal line 51 to the output signal line 57 via T11 and T12. And, the length of the route is different. Therefore, as described above, even when the forward path and the return path of the signal are opposed to each other with the substrate sandwiched therebetween, the amount of the inductance in the two paths is slightly different depending on the inductance existing in the path, which may cause imbalance. Therefore, the embodiment shown in FIG. 4 improves this.

On the first main surface 41, a plurality of conductive layers 32,
34 and 36 are provided in parallel, but at this time, each conductive layer is provided in an arc shape on the first main surface 41. The plurality of power devices on the conductive layer 38 are arranged symmetrically with respect to the conductive layer 38, and the plurality of input signal lines 51, 53 and 55 are arranged and connected so as to be symmetrical with respect to the plurality of power devices. It It is preferable that the arrangement intervals of the plurality of power devices in each conductive layer are sequentially narrowed toward the output signal line 57, and preferably the power devices are arranged radially from the connection portion of the output signal line 57. . As a result, the difference in the length of the path from the input signal line to the output signal line via each power device is reduced, and thus the imbalance of the inductance existing in the circuit wiring can be effectively reduced. Of course, ideally, the difference between the paths of the signals should be zero.

FIG. 6 shows still another embodiment of the present invention,
It is the figure which looked at substrate 30 from the 1st principal surface 41 side. As compared with FIG. 4, the conductive layer 36 has a fan shape, and the output signal line 57 is connected to the apex portion of the fan. According to this, the difference in distance between each emitter of the IGBTs of T12 to T52 closest to the output signal line 57 and the connection portion of the conductive layer 36 of the output signal line 57 becomes smaller and the symmetry increases, so that the inductance is increased. The distribution unbalance is further reduced. Figure 6
In the embodiment shown in (1), since the conductive layer 36 has a fan shape, the common conductive layer 38 on the second main surface 42 is also provided in a shape corresponding to the conductive layer 36 in the same manner as described above.

In the embodiment shown in FIGS. 1 to 6, the pair of input signal lines 51 and 52 are the forward path and the backward path of the input signal, respectively, which are arranged in parallel and generate each other when a current flows. It is better to cancel the magnetic fields. Similarly, 1
The pair of input signal lines 53 and 54 and 55 and 56, and the pair of output signal lines 57 and 58 may also be arranged in parallel so as to cancel the magnetic fields generated by each other. These can reduce the inductance. Each signal line is provided with a thin insulating layer on the surface, for example, and the conductive portion is exposed only at the portion connected to the conductive layer. The exposed portion is connected to the conductive layer with solder. The thinner the surface insulating layer is, the more effectively the magnetic fluxes of each pair cancel each other when the pair of input signal lines 51 and 52 are arranged in parallel and a current is passed, so that the effect of reducing the inductance increases. If a load is not provided before the output signal line, the output signal line 57
And 58 may be short circuited.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described herein, and various modifications and changes can be made as necessary without departing from the gist of the present invention. It will be apparent to those skilled in the art that changes can be made. For example, in the above-described embodiments, it is assumed that a power supply is connected to the input side, and there is an example in which a plurality of power supplies can be provided, so a plurality of input signal lines are provided. You may make it provide several lines. The power device may be a thyristor having a cathode terminal and an anode terminal, and in this case, one may be the first terminal and the other may be the second terminal.

[0024]

According to the power control circuit of the present invention, since the forward path and the return path of the signal are formed so as to correspond to each other with the substrate sandwiched therebetween, when the currents flow, the magnetic fields of the signals are canceled and the inductance is reduced. To be done. Further, it is possible to reduce the imbalance of the inductance of the circuit wiring.

[Brief description of drawings]

FIG. 1 is a view of a substrate on which a power control circuit of the present invention is mounted, viewed from a first main surface side.

FIG. 2 is a view of a substrate on which a power control circuit of the present invention is mounted, viewed from the second main surface side.

FIG. 3 is a sectional view taken along a broken line 8 in FIGS. 1 and 2.

FIG. 4 is a view of a substrate as viewed from a first main surface side in another embodiment of the present invention.

FIG. 5 is a diagram of a substrate as viewed from a second main surface side in another embodiment of the present invention.

FIG. 6 is a view of a substrate as seen from the first main surface side in still another embodiment of the present invention.

FIG. 7 is a circuit diagram showing an example of an element characteristic measuring circuit.

FIG. 8 is a circuit diagram showing an example of a power control circuit.

[Explanation of symbols]

 8 Broken line indicating the position of the cross section of FIG. 3 20 Power control circuit 22 First gate drive circuit 24 Second gate drive circuit 26 Input terminal 28 Output terminal 30 Substrate 32 Conductive layer 34 Conductive layer 36 Conductive layer 38 Common conductive layer 41 1 main surface 42 second main surface 51 forward input signal line 52 return input signal line 53 forward input signal line 54 return input signal line 55 forward input signal line 56 return input signal line 57 forward output signal line 58 Return signal line 60-66 Arrow indicating the traveling direction of signal T11-T51 First row IGBT T12-T52 Second row IGBT S31, S32 Collector contact surface of IGBT

Claims (3)

[Claims] 1. A substrate having first and second main surfaces facing each other, a plurality of conductive layers provided in parallel on the first main surface, and a conductive layer in which respective first and second terminals are adjacent to each other. A plurality of power devices connected to each other in the forward direction, and the terminals of the power device and the plurality of power devices that are provided on the second main surface and that are present between the conductive layers to connect the adjacent conductive layers. The second corresponding to the conductive layer of
A common conductive layer provided in a region on the main surface, the forward path of the input signal line is connected to the conductive layer at the input side end in the forward direction, and the conductive layer at the input side end faces the conductive layer. The return path of the input signal line is connected to a position on the common conductive layer, the forward path of the output signal line is connected to the conductive layer at the output side end portion in the forward direction, and the conductivity at the output side end portion in the forward direction is connected. A power control circuit, wherein a return path of the output signal line is connected to a position on the common conductive layer facing the layer. 2. The plurality of conductive layers on the first main surface are formed in an arc shape, and the plurality of power devices are provided in the forward direction from the conductive layer at the input side end portion in the forward direction via the plurality of power devices. 2. The power control circuit according to claim 1, wherein the difference in the length of each path to the conductive layer at the output side end is reduced. 3. One of the packages of the power device
The power control circuit according to claim 1 or 2, wherein a contact surface electrically connected to the first terminal provided on the main surface is brought into contact with the conductive layer.