JPH08273392A - Semiconductor memory and its test method - Google Patents

Abstract

PURPOSE: To reduce the cost by detecting the short circuit of word line in a short time prior to die sort test thereby shortening the die sort time. CONSTITUTION: A plurality of word lines WL1-WLn are arranged in stripe on a memory cell array 13. Upon receiving a control signal CR from a pad 21, an address signal switching circuit 11 delivers an address signal for selecting every other word line in place of a normal address signal A. Consequently, a decoder 12 is alternately arranged with a word line being applied with a high potential and a word line being applied with a low potential. A detection circuit 14 detects the variation of potential owing to short circuit of at least one word line being applied with a high or low potential. Upon detection of potential variation, two detection pads 24, 25 are short-circuited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing the test time of a semiconductor memory device using a die sorter.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device having a stripe-shaped word line, a defect (a short circuit or the like) in the word line has been found by a function check at the time of die-sorting.

However, in this function check, it is necessary to sequentially select all the addresses and compare the obtained value with the expected value. Therefore, until the defective word line is selected, the defect of the word line cannot be found, the die-sort time becomes long, and the cost increases.

[0004]

As described above, conventionally,
Since the defect of the word line has been found by the function check at the time of diat, there is a drawback that the die-sort time becomes long and the cost increases.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to perform a work before performing a die-sort test.
This is to detect the defect of the lead wire in a short time and perform the die-sort test only for the good product, thereby shortening the die-sort time and reducing the cost.

[0006]

In order to achieve the above object, the semiconductor memory device of the present invention has a plurality of word lines arranged in stripes and the plurality of word lines every other line. A means for selecting a word line to which a high potential is applied and a word line to which a low potential is applied alternately arranged;
It is connected to the word line to which the high potential is applied or the word line to which the low potential is applied, and the potential change of at least one word line is detected to detect the adjacent word line. And a detection circuit capable of inspecting a short circuit.

When the control signal is input, the means changes the address signal to a normal address signal and outputs an address signal for selecting every other one of the plurality of word lines, and the address signal switching circuit. And a decoder for selecting a word line based on the address signal from the switching circuit.

In the detection circuit, the gate is connected to the word line to which the high potential is applied or the word line to which the low potential is applied, and the source or the drain is between two detection terminals. It is composed of a plurality of MOS transistors connected to.

A method of testing a semiconductor memory device according to the present invention is
A plurality of word lines arranged in stripes are selected every other line, and a word line to which a high potential is applied and a word line to which a low potential is applied are arranged alternately to obtain the high potential. A short circuit between adjacent word lines is detected by detecting a potential change in at least one of the word lines to which a voltage is applied or a word line to which a low potential is applied. Equipped with the process of.

The semiconductor memory device testing method of the present invention is
Furthermore, an external voltage is applied between the two detection terminals,
A series of steps for inspecting a short circuit between adjacent word lines by short-circuiting the two detection terminals based on the potential change and detecting a current flowing between the two detection terminals is provided. .

[0011]

According to the above construction, a word line (selected word line) to which an address signal for selecting every other word line is applied to the decoder and a high potential is applied. Alternatively, by connecting a detection circuit to a word line (non-selected word line) to which a low potential is applied and detecting a change in the potential of at least one word line, Testing for defects (shorts, etc.).

That is, in the prior art, all the addresses had to be sequentially selected in the function check at the time of die-sorting, whereas in the present invention, a control signal is applied and a current flowing between the detection terminals is supplied. The defect of the word line can be confirmed only by detecting

Therefore, it is possible to easily and quickly test the wire line, and it is sufficient to perform the die-sort test only on the products that pass the test result, so that the die-sort time can be shortened. The cost can be reduced significantly.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the concept of the semiconductor memory device of the present invention.

A control signal pad 21, a first power supply pad 22 and a second power supply pad 23 are connected to the address signal switching circuit 11. A high potential (for example, 5V) VDD is applied to the first power supply pad 22, and the second power supply pad 2
A low potential (for example, 0V) VSS is applied to 3. The control signal pad 21 is supplied with a control signal CR for controlling switching between the address signal A in the normal state and the address signal in testing the defect of the word line.

When the control signal CR is input when testing the defect of the word line, the address signal switching circuit 11 supplies to the decoder 12 an address signal which can select every other word line. give.

For example, the decoder 12 includes odd-numbered word lines WL1, WL3, ... WL of the memory cell array 13.
(N-1) is selected and these word lines WL1, WL
3, ... WL (n-1) potential is high potential (for example, 5 V) V
Set to DD.

Further, the decoder 12 deselects the even-numbered word lines WL2, WL4, ... WLn of the memory cell array 13, and these word lines WL1, WL3 ,.
The potential of (n-1) is set to a low potential (for example, 0V) VSS.

Non-selected word lines of the memory cell array 13, that is, even-numbered word lines WL2, WL4, ... WL.
The detection circuit 14 is connected to n. Detection circuit 1
4 is an even-numbered word line WL2, WL4, ... W
The potential of Ln is detected, and if at least one word line exceeds the predetermined potential (threshold value), a detection signal indicating that there is a defect (short circuit, etc.) in the word line is output. .

That is, in a good semiconductor memory device,
All the non-selected word lines have the low potential VSS, but in the defective semiconductor memory device in which the adjacent word lines are short-circuited, the potential of the non-selected defective word line rises. To do.

The selected word lines of the memory cell array 13, that is, odd-numbered word lines WL1, WL3, ... WL.
The detection circuit 14 may be connected to (n-1). In this case, the detection circuit 14 uses these odd-numbered word lines WL.
1, WL3, ... WL (n-1) are detected, and if there is at least one word line below a predetermined potential (threshold value), there is a defect (short circuit, etc.) in the word line. A detection signal indicating the effect is output.

That is, in a good semiconductor memory device,
All the selected word lines have the high potential VDD, but in the defective semiconductor memory device in which the adjacent word lines are short-circuited, the potential of the defective word line rises.

FIG. 2 shows the address signal switching circuit 11 of FIG.
FIG. This address signal switching circuit is used when the decoder 12 of FIG. 1 is composed of an AND circuit (logical product) as shown in FIG.

Every other word line is selected, that is, an odd-numbered word line WL1, WL3, ... Of the memory cell array.
When WL (n-1) is selected (where n is an even number), address signals A1, A2, A5, A6 ... A (2n-
1) and A2n may be set to "H" level (however, n is an odd number).

Therefore, the signal lines for supplying the address signals A1 and A2 are connected to the power supply pad 2 to which the high potential VDD is applied.
2 is connected via MOS transistors (switches) T11 and T21. Similarly, the address signal A (2n-
Signal lines 1) and A2n (where n is an odd number) are also connected to the power supply pad 22 to which the high potential VDD is applied via a MOS transistor (switch).

However, one of the signal lines for supplying the address signals A3 and A4 is connected to the power supply pad 23 to which the low potential VSS is applied. For example, the signal lines for supplying the address signals A3 and A4 are connected to the power supply pad 23 to which the low potential VSS is applied via MOS transistors (switches) T31 and T41. Similarly, address signals A (2n-1) and A2n (where n is an even number)
As for the signal line that supplies the signal, one of the signal lines has a low potential VS.
The power supply pad 23 to which S is applied is connected via a MOS transistor (switch).

ON / OFF of the MOS transistors T11, T21 ... Is controlled by a control signal CR. That is, the MOS transistors T11, T21 ... Cut off the normal address signal A during the inspection of the word line,
An address signal for selecting every other word line as described above is output.

FIG. 4 shows an example of the detection circuit of FIG. This detection circuit includes non-selected word lines, for example, even-numbered word lines WL2, WL4 of the memory cell array.
... Used when WLn is connected to the detection circuit.

That is, the gate of the MOS transistor T2 is connected to the word line WL2, and the source / drain terminal is connected between the detection pads 24 and 25. Similarly, the gate of the MOS transistor Tn is the word line W
It is connected to Ln, and the source / drain terminal is connected between the detection pads 24 and 25.

Each MOS transistor preferably has the same structure as the transistor forming the memory cell. Normally, the word lines WL2, WL4, ... WLn are
Since they are not selected and have the low potential VSS, the MOS transistors T2, T4, ... Tn are all off.

However, two word lines adjacent to each other,
For example, when the word lines WL3 and WL4 are short-circuited, the resistance R raises the potential of the word line WL4 from the low potential VSS to an intermediate potential between the high potential VDD and the low potential VSS.

When the potential of the word line WL4 exceeds the threshold value of the MOS transistor T4, the MOS transistor T2 is turned on, so that the detection pads 24 and 2 are connected.
5 is short-circuited.

Therefore, if a predetermined voltage is applied between the detection pads 24 and 25 in advance, the detection pads 24 and 2 are detected.
By detecting the current flowing during 5, the short circuit of the word line of the memory cell can be tested.

When at least one of the two word lines adjacent to each other is short-circuited, at least one MOS transistor is always turned on, so that a current flows between the detection pads 24 and 25. That is, the short circuit of the word line can be detected in a short time.

FIG. 5 shows the address signal switching circuit 11 of FIG.
It shows another example. This address signal switching circuit is used when the decoder 12 of FIG. 1 is composed of an OR circuit (logical sum) as shown in FIG.

Every other word line is selected, that is, odd-numbered word lines WL1, WL3, ... Of the memory cell array.
When WL (n-1) is selected (where n is an even number), address signals A1, A2, A5, A6 ... A (2n-
1) and A2n may be set to "L" level (however, n is an odd number).

Therefore, the signal lines for supplying the address signals A1 and A2 are connected to the power supply pad 2 to which the low potential VSS is applied.
3 via MOS transistors (switches) T11 and T21. Similarly, the address signal A (2n-
Signal lines 1) and A2n (where n is an odd number) are also connected to the power supply pad 23 to which the low potential VSS is applied via a MOS transistor (switch).

However, one of the signal lines for supplying the address signals A3 and A4 is connected to the power supply pad 22 to which the high potential VDD is applied. For example, the signal lines for supplying the address signals A3 and A4 are connected to the power supply pad 22 to which the high potential VDD is applied, via MOS transistors (switches) T31 and T41. Similarly, address signals A (2n-1) and A2n (where n is an even number)
As for the signal line that gives the
The power supply pad 22 to which D is applied is connected via a MOS transistor (switch).

ON / OFF of the MOS transistors T11, T21 ... Is controlled by a control signal CR. That is, the MOS transistors T11, T21 ... Cut off the normal address signal A during the inspection of the word line,
An address signal for selecting every other word line as described above is output.

[0040]

As described above, the semiconductor memory device of the present invention has the following effects. An address for selecting every other word line is given to the decoder, and a detection circuit is connected to the selected word line or non-selected word line, and the potential of the word line concerned is connected. By detecting the change of the test line, it is tested whether or not there is a defect (short circuit, etc.) in the word line.

Therefore, in the prior art, all addresses had to be sequentially selected in the function check at the time of die-sorting, whereas in the present invention, a control signal is applied and a current flowing between the detection terminals is supplied. The defect of the word line can be confirmed only by detecting

In other words, it is possible to easily and quickly test the wire line, and it is sufficient to perform the die-sort test only on the products that pass the test result, so that the die-sort time can be shortened. The cost can be reduced significantly.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing an example of an address signal switching circuit of FIG.

FIG. 3 is a circuit diagram showing an example of the decoder shown in FIG.

FIG. 4 is a circuit diagram showing an example of the detection circuit of FIG.

5 is a circuit diagram showing another example of the address signal switching circuit of FIG.

6 is a circuit diagram showing another example of the decoder shown in FIG.

[Explanation of symbols]

11: address signal switching circuit, 12: decoder, 13: memory cell array, 14: detection circuit, 21: control signal pad, 22: power supply (VDD) pad, 23: power supply (VSS) pad, 24, 25: Detection pad, T11, T21, T12, T22, T31, T41, T
32, T42: N channel type MOS transistor (switch), T2, T4, ... Tn: N channel type MOS transistor (detection switch), I: Inverter. WL1 to WLn: word lines.

Claims (5)

[Claims] 1. A plurality of word lines arranged in a stripe pattern and a plurality of every other word lines are selected, and a word line to which a high potential is applied and a word line to which a low potential is applied. At least one word line connected to the word line to which the high potential is applied or the word line to which the low potential is applied, A semiconductor memory device comprising: a detection circuit capable of inspecting a short circuit of an adjacent word line by detecting a potential change of the line. 2. The address signal switching circuit for outputting an address signal for selecting every other one of the plurality of word lines instead of a normal address signal when a control signal is input, 2. A semiconductor memory device according to claim 1, further comprising a decoder for selecting a word line based on an address signal from an address signal switching circuit. 3. The detection circuit has a gate connected to the word line to which the high potential is applied or the word line to which the low potential is applied, and has two sources or drains for detection. A semiconductor memory device comprising a plurality of MOS transistors connected between terminals. 4. A plurality of word lines arranged in stripes are selected every other line, and word lines to which a high potential is applied and word lines to which a low potential are applied are alternately arranged. And the word line to which the high potential is applied or the word line to which the low potential is applied.
A method for testing a semiconductor memory device, characterized in that a change in potential of at least one word line among the word lines is detected to inspect a short circuit between adjacent word lines. 5. A voltage is externally applied between the two detection terminals, the two detection terminals are short-circuited based on the potential change, and a current flowing between the two detection terminals is detected. 5. The method for testing a semiconductor memory device according to claim 4, wherein a short circuit between adjacent word lines is inspected.