JP2950194B2 - Semiconductor memory device and its initial failure test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mask ROM, EP
The present invention relates to a semiconductor memory device such as a ROM and an EEPROM, and more particularly to a semiconductor memory device that facilitates an initial failure test and an initial failure test method thereof.

[0002]

2. Description of the Related Art Mask ROMs have become
It has become very difficult to analyze chip failures. For example,
NAND type mask RO made by submicron rule
It is very difficult to optically observe the M chip to find a defect. Normally, for screening, an electrical check (die sort) is performed to determine whether there is a defective bit by reading memory data before cutting a chip from a wafer. At this time, even if there is a defect of a plurality of bits, it is not easy to determine whether the defect is a writing defect of a memory cell, a word line defect, or a bit line defect. It is possible to perform a scramble process of reassembling to a bit pattern corresponding to the layout on the actual chip, and calculate whether a defect of a plurality of bits is along the word line direction or the bit line direction by calculation. take time. In particular, short-circuit failure of a bit line cannot be predicted except by observing a fail bit, and simple determination is difficult.

[0003]

As described above, in the conventional semiconductor memory device, failure analysis becomes difficult due to miniaturization of elements. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory device that facilitates initial failure analysis of a bit line and an initial failure test method thereof.

[0004]

SUMMARY OF THE INVENTION The present invention provides a memory cell array in which memory cells are arranged at intersections of a plurality of word lines and bit lines, a word line selection circuit for selectively driving word lines, and a bit line. In a semiconductor memory device having a sense amplifier circuit for reading line data and a column selection circuit for selectively connecting a bit line to the sense amplifier circuit, an unselected bit adjacent to a selected bit line selected by the column selection circuit A level detection circuit that detects the level of a line to detect the presence or absence of a short circuit between bit lines; and a non-selected bit line adjacent to the selected bit line is selected in synchronization with the column selection circuit to provide the level detection circuit. And an auxiliary column selection circuit to be connected.

The present invention is also an initial failure test method when the memory cell array is constituted by NAND type memory cells, wherein all word lines of a selected memory block are set to "H" level, A circuit detects the level of the selected bit line and conducts a continuity test of the bit line. At the same time, the level detection circuit detects a level of a non-selected bit line adjacent to the selected bit line and performs a short circuit test between adjacent bit lines. It is characterized by performing.

[0006]

According to the present invention, there is provided a level detection circuit for detecting the level of a non-selected bit line adjacent to a selected bit line selected by a column selection circuit to detect the presence or absence of a short circuit between bit lines, By providing an auxiliary column selection circuit that selects a non-selected bit line adjacent to the line in synchronization with the column selection circuit and connects to the level detection circuit, short-circuit failure of the bit line can be easily tested. According to the initial failure test method of the present invention,
When the memory cell array is composed of NAND type memory cells, all word lines of the selected memory block are set to the “H” level, and the level of the selected bit line is detected by the sense amplifier circuit to conduct a bit line conduction test. At the same time, the level detection circuit can detect the level of a non-selected bit line adjacent to the selected bit line and perform a short-circuit test between the bit lines.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a NAN according to an embodiment of the present invention.
2 is a block diagram of a main part of a D-type mask ROM. As illustrated, a plurality of word lines WL (WL0, WL1,
..) And bit lines BL (BL0, BL1,...), Each having a memory cell arranged therein, a memory cell array 11 in which data is mask-programmed, a word line selection circuit 12 for selectively driving the word line, a bit line And a sense amplifier circuit 14 for reading data of the selected bit line.

At the end of the bit line BL of the memory cell array 11 on the side opposite to the sense amplifier circuit 14, there is provided a level detection circuit 16 for detecting the potential level of a non-selected bit line. An auxiliary column selection circuit 15 for connecting a non-selected bit line adjacent to the bit line selected by the column selection circuit 13 to this level detection circuit 16
Is provided.

FIG. 2 shows an example of a circuit configuration of each section in FIG. 1 in the case of an 8-stage NAND type mask ROM. The sense amplifier circuit 14 includes two NMOS transistors QN1 and QN2 connected in series between a node N1 connected to a bit line selected by the column selection circuit 13 and VDD,
The CMOS inverter I1 which negatively feeds back the potential of the node N1 to the common gate of these two NMOS transistors QN1 and QN2, and the PMOS transistor QP1 provided between the connection node N2 of the two NMOS transistors QN1 and QN2 and VDD. It is configured. The node N2 is connected to a current mirror type differential amplifier (not shown).

The column selection circuit 13 selects an arbitrary bit line of the memory cell array 11 and selects a sense amplifier circuit 14
Connected to the input node N1. In FIG. 2, an NMOS transistor QN that connects the bit line BLi to the sense amplifier input node N1 is used as the column selection circuit 13.
3, only QN4 is illustrated. Normally, since one column is constituted by a plurality of bit lines, a select gate transistor is inserted between each bit line and the NAND cell block, but this is omitted in FIG.

The auxiliary column selection circuit 15 connects an unselected bit line adjacent to the bit line selected by the column selection circuit 13 to the level detection circuit 16. FIG.
Then, the two NMOS transistors QN5 and QN4 of the column selection circuit 13 are turned on at the same time as the auxiliary column selection circuit 15 to select the bit line BLi + 1 adjacent to the bit line BLi when the bit line BLi is selected. , QN6 only are shown.

A level detection circuit 16 for detecting the level of an unselected bit line includes a negative feedback C of the sense amplifier circuit 14.
A CMOS inverter I2 having the same configuration as the MOS inverter I1 is used. The output node of the CMOS inverter I2 is connected to a current mirror type CMOS differential amplifier circuit using NMOS transistors QN7 and QN8 as drivers and PMOS transistors QP2 and QP3 as active loads. As the reference voltage VREF of this differential amplifier circuit,
REF = VDD− | Vtp | (Vtp is a PMOS transistor Q
P4 threshold voltage).

With such a configuration, at the time of die sorting after the wafer process is completed, the bit lines BL
Is checked for initial failure. That is, a bit line is sequentially selected by the column selection circuit 13 for each predetermined memory block, and an "H" level signal is applied to all the word lines WL0 to WL7 for the memory block each time the bit line is selected. The bit line is at almost zero potential in the unselected state,
When, for example, the bit line BLi is selected by the column selection circuit 13, this bit line BL
Li stabilizes at a potential of about 1V.

The NMOS transistor QN2 is provided to stabilize the bit line to about 1 V when the bit line is selected, regardless of the basic operation of the sense amplifier circuit. The main element for detecting the current attraction of the selected bit line is the PMO of the sense amplifier circuit 14.
This is the S transistor QP1. When there is current draw,
The potential drop due to the channel resistance of the PMOS transistor QP1 functions to cause the potential of the node N2 to drop.
The CMOS inverter I1 performs negative feedback control on the NMOS transistors QN1 and QN2 in a direction to suppress the potential change of the node N1, and keeps the potential of the node N1 at about 1 V regardless of whether or not current is drawn.

The bit line BL is set by the column selection circuit 13.
When i is selected and the word lines WL0 to WL7 become "H" in this state, all the memory transistors are turned on. As a result, if the bit line BLi including the contact portion of the selected bit line BLi is normal, a slight drop in the potential of the node N1 occurs as a result of the current drawing by the memory transistor, and this is detected by the sense amplifier circuit 14. become. For example, the contact of the bit line BLi is defective, and the NAND cell block is electrically connected to the bit line BLi.
When not connected to Li, there is no current draw, and there is no reduction in the potential of the node N1. As described above, NAN
A continuity test of the D cell block is performed.

At the same time as the continuity test, a short-circuit test between bit lines is performed. That is, when the selected bit line BLi is connected to the sense amplifier 13, the adjacent non-selected bit line BLi + 1 is simultaneously connected to the input node N3 of the level detection circuit 16. The unselected bit line BLi + 1 is at almost zero potential as described above. This unselected bit line BLi
Unlike the sense amplifier circuit 14, the level detection circuit 16 to which +1 is connected does not have a bit line charging unit. Therefore, the unselected bit line BLi + 1 is connected to the adjacent selected bit line BLi.
As long as it is not short-circuited with i, it is kept at the ground potential even when the level detection circuit 16 is connected. That is, the level detection circuit 16
There is no output change.

When the unselected bit line BLi + 1 is short-circuited with the selected bit line BLi, the unselected bit line BLi
+1 is raised by the potential of the node N1 of the sense amplifier circuit 14 to about 1V. And inverter I
When the output of the differential amplifier 2 falls below the reference voltage VREF, the output of the current mirror type differential amplifier circuit is inverted. As a result, it is detected that the unselected bit line BLi + 1 is short-circuited with the selected bit line BLi.

As described above, according to this embodiment, the initial defect check of the bit line can be easily performed by adding the auxiliary column selecting circuit and the level detecting circuit to the ordinary NAND type mask ROM configuration. it can. In the defect check mode, all the word lines of a predetermined memory block are driven to the “H” level, and a short-circuit test between the bit lines can be performed simultaneously with the continuity test of the bit lines.

The present invention is not limited to the above embodiment. For example, in the embodiment, the NAND type mask ROM has been described.
The present invention can be similarly applied to a PROM or an EEPROM, or to a case where a NOR type memory cell configuration is used.

[0020]

As described above, according to the present invention, by adding an auxiliary column selecting circuit and a level detecting circuit, it is possible to obtain a semiconductor memory device which can easily check the initial failure of a bit line. be able to. Further, according to the initial failure test method of the present invention, all the word lines of a predetermined memory block can be driven to "H" level to conduct a bit line conduction test and a short circuit test between bit lines at the same time.

[Brief description of the drawings]

FIG. 1 shows a main configuration of a mask ROM according to an embodiment of the present invention.

FIG. 2 shows a specific circuit configuration of the embodiment.

[Explanation of symbols]

11: memory cell array, 12: word line selection circuit, 1
3 ... column selection circuit, 14 ... sense amplifier circuit, 15 ...
Auxiliary column selection circuit, 16... Level detection circuit.

Claims (2)

(57) [Claims] 1. A memory cell array in which memory cells are arranged at intersections of a plurality of word lines and bit lines, a word line selection circuit for selectively driving word lines, and a sense amplifier circuit for reading bit line data. A column selection circuit for selectively connecting a bit line to the sense amplifier circuit, wherein the level of a non-selected bit line adjacent to the selected bit line selected by the column selection circuit is detected and A level detection circuit that detects the presence or absence of a short circuit between lines; and an auxiliary column selection circuit that selects an unselected bit line adjacent to the selected bit line in synchronization with the column selection circuit and connects to the level detection circuit. A semiconductor memory device comprising: 2. The method according to claim 1, wherein said memory cell array comprises NAND memory cells, wherein all word lines of a selected memory block are set to “H” level. Detecting the level of the selected bit line by the sense amplifier circuit and performing a continuity test on the bit line;
At the same time, an initial failure test method for a semiconductor memory device, wherein a level of a non-selected bit line adjacent to the selected bit line is detected by the level detection circuit to perform a short-circuit test between adjacent bit lines.