JPH08272639A - Test circuit and test method for microcomputer - Google Patents

Abstract

PURPOSE: To provide a test circuit/method for a microcomputer which uses a single terminal that is used as only an output terminal in a normal operation mode as a test mode setting input terminal and also uses the output buffer of the terminal used as the input terminal in a selection test that is carried out by an LSI tester. CONSTITUTION: This test circuit/method includes a noise elimination part 2 which eliminates the noises when the output signal of an output buffer 1 is compulsively fixed at a power supply potential or a ground potential, a delay element 3 which delays the input signal of the buffer 1 by a time equal to the delay time of the part 2, an inverter 4, a discordance detection part 5 which compares the output of the element 3 with that of the part 2 and outputs a discordance signal if the coincidence is not secured between both outputs, a counter circuit part 6 which counts an discordance signals, and a storage circuit 7 which stores the overflow signal that is produced based on the counting result of the part 6. Then an output terminal 9 is fixed at a power supply or ground potential via an LSI tester, and a test mode is set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer test circuit and a test method, and more particularly to a microcomputer test circuit and a test method for preventing malfunction of a test mode due to influence of noise or variation in manufacturing process.

[0002]

2. Description of the Related Art In recent years, the number of input / output terminals has increased as a result of the high integration and multifunction of microcomputers, and it has become necessary to use these terminals efficiently.

Therefore, for example, when testing a microcomputer, the function of the internal circuit is confirmed while the internal circuit is in the test mode, and the electrical characteristics of the input / output buffer that interfaces with the external circuit of the microcomputer are also measured. It is necessary to confirm. In order to shift to this test mode, a test terminal as an input terminal for supplying the control signal from the outside and a test mode setting section for shifting to the test mode in response to the control signal supplied are provided. Although the test terminal may be provided independently, it is often shared with other input terminals in order to use the terminal efficiently as described above.

An example of a conventional test mode setting unit of this type is described in Japanese Patent Laid-Open No. 62-62060.
FIG. 6 showing a circuit diagram of a test mode setting unit described in the publication.
, A first series connection circuit of the N-channel depletion MOS transistor D1 and the N-channel depletion MOS transistor D2 inserted between the power supply potential and the ground potential, and the N-channel depletion MOS transistor. A second series connection circuit of a transistor D3 and an N-channel enhancement MOS transistor N1, and gate electrodes of the transistors D1 and D2 are commonly connected to a series connection point A of the first series connection circuit, respectively. The gate electrode is second
Series connection point B of the series connection circuit and the test mode output terminal O
The gate electrodes of the transistors D2 are commonly connected to the UTs, connected to the test terminal IN, and supplied to the internal circuit through the signal line test.

This circuit normally uses the input terminal IN during the operation.
A low level (for example, 0V voltage) is supplied to a logic level from a high level (for example, 5V voltage).

Since the transistor D1 operates as an active load element, when a high level is supplied to the gate electrode of the transistor D2, this transistor becomes conductive,
The potential of the drain connection point A becomes low level.

Therefore, the transistor D3 whose gate electrode is connected to the connection point A becomes non-conductive, and the connection point B of the drain thereof becomes high level to bring the internal circuit into the normal operation state.

On the other hand, to enter the test mode, a sufficiently negative voltage (for example, -5V) is supplied to the input terminal IN. Due to this negative voltage, the transistor D2 becomes non-conductive, and the potential at the connection point A becomes high level. Therefore, the transistor D3 becomes conductive and the potential of the connection point B becomes low level. When the on-resistance between the drain and source connection points of the transistor D3 is designed to be extremely small, the connection point B is +5.
Since the state of V is switched to the state of 0V and the test mode signal is supplied from the test mode output terminal OUT to the internal circuit, the internal circuit enters the test mode state.

Therefore, in order to manage the diffusion manufacturing conditions more finely, to add a step of confirming the test mode setting operation by the pre-shipment test, and to configure two types of enhancement type and depletion type MOS transistors on the same semiconductor chip. In addition, since the conditions such as the diffusion manufacturing process becoming more complicated than the normal process overlap, the manufacturing cost increases.

In the conventional test circuit and test method, the on-resistance between the drain electrode and the source electrode of the enhancement type MOS transistor is made small, and normally the supply voltage (0 to 5V) is applied with the reverse characteristic voltage (-5V). By doing so, the test mode is set. Therefore, due to variations in diffusion conditions in mass production, the resistance value when conducting between the drain electrode and the source electrode of the enhancement-type MOS transistor deviates from the expected value at the time of design, and during normal operation, noise causes the test mode. On the other hand, there is a drawback that the test mode cannot be set even if -5 V is applied.

An example of a case in which the above-mentioned drawbacks are alleviated and a test terminal and another input terminal are shared is disclosed in Japanese Patent Laid-Open No. 2-19.
931 gazette. Referring to FIG. 7, which is a block diagram showing the test mode control method described in the publication,
The external terminals 300a to 300n are connected to the input terminal of the decoding circuit 301, and the output end out is the processing circuit 302.
Is connected to one input end of the OR gate 303. The output terminal of the other input terminal of the OR gate 303 is connected to the reset terminal R of the timer 304.
An OR gate 305 in which the overflow output terminal OVF of the timer 304 and the reset signal line RESET are connected
Is connected to the reset input terminal S of the processing circuit 302, and the test mode setting signal 306 is output from the output terminal Q thereof.

In this configuration, when the test mode is set, the external terminals 300 such as a plurality of IO ports are set.
A specific pattern signal composed of a plurality of bits for setting the test mode is supplied to a to 300n.

The decode circuit 301 decodes this pattern, and if the signal pattern is a test mode setting signal, an output is generated from the output terminal OUT, and the processing circuit 302, which is, for example, a flip-flop, is set at this output to generate a Q output. , The dirt becomes the test mode setting signal and sets the microcomputer to the test mode.

The output of the decoding circuit 301 is the OR gate 3.
It is supplied to the timer 304 via 03 and is reset, and counting of the clock φ is started. When the timer 304 measures a preset time, it generates an overflow output OVF, which resets the processing circuit 302, so that the test mode setting signal 306 disappears.

However, before that, the external terminals 300a-30
When the test signal is supplied to 0n and the test of the microcomputer is started, the decode circuit 301 produces the decoded output of this test signal, which is generated by the timer 304.
To reset the processing circuit 22 to the set state.

By including a specific pattern everywhere in the test signal and resetting it before the timer 304 overflows, the processing circuit 302 can be kept in the set state during the test.

After the test is completed, the reset signal RESET is supplied to the OR gates 33 and 305 to reset the timer 304 and the processing circuit 302.

[0018]

In the above-mentioned conventional example,
While sharing multiple test terminals with other input terminals,
If you do not enter the test mode unless you input specific data consisting of multiple bits from these multiple pins, it is unlikely that you will accidentally enter the test mode, and even if you accidentally enter the test mode, the test signal If you do not enter, it will return to the normal mode after a certain period of time.

However, the basic function of the input terminal and the input buffer connected to this input terminal (not shown but of course arranged) is that the input signal is the desired signal or unexpected noise. Regardless of whether it exists, it will be transmitted to the internal circuit.

Therefore, a plurality of input terminals and a decoding circuit are required to identify the input noise or the unnecessary signal due to the erroneous operation. In addition, if the test mode is mistakenly entered, it is necessary to wait until the timer overflows in order to return to the normal operation mode.

On the other hand, in order to enter the test mode and continue the state, it is necessary to insert a specific pattern at a certain interval in the test program, and shortening the test time is an extremely important factor. It is a loss time that cannot be ignored in the computer manufacturing process. For example, the process in which the test mode is used before the shipment of one microcomputer is usually, before and after wafer warehousing, assembling / sorting, and high temperature sorting, warehousing and unloading sorting, and the number of insertions of a specific pattern x The number of times of sorting x time is extra lost time.

To reduce this loss time, the timer time may be shortened, but if it is shortened, the number of specific pattern insertions must be increased.
Compression is difficult.

The object of the present invention was made in view of the above-mentioned drawbacks, and in the selection test by the LSI tester, one terminal used as an input terminal for setting a test mode and only as an output terminal in normal operation. And its output buffer are used to provide a plurality of input terminals for identifying an unnecessary signal, a plurality of control data for entering a test mode, and a microcomputer test circuit and test method that do not require these identification circuits. To do.

[0024]

The test circuit and test method for a microcomputer of the present invention are characterized by an input buffer for receiving a supply signal from the outside, an output buffer for outputting a processing result of an internal circuit, and a function of both of them. And a test mode setting unit for setting the state of the internal circuit to any one of an operation mode, a reset mode or a test mode in response to a mode setting signal supplied from the outside. In the micro computer, during the operation of the output buffer, the output terminal is forcibly fixed from the outside to either the power supply potential or the ground potential for a predetermined period and the test mode setting unit is set to the test mode. It is to have a test mode shift means for shifting.

Further, the test mode transition means forcibly fixes the output terminal to the ground potential for a predetermined period within the high level period when the output of the output buffer is at the high level, and the fixing operation thereof. It is possible to provide a function to detect and store that the test has been performed a predetermined number of times, and to shift to the test mode when the predetermined number of times is reached.

Further, the test mode transition means can forcibly fix the output terminal to the power supply potential only for a predetermined period within the low level period when the output of the output buffer is at the low level.

Furthermore, the setting result may be stored only in the storage means, and a function of shifting to the test mode according to the stored content may be provided.

The test mode setting section used in the test mode transition means includes a noise removing section for removing noise when the output signal of the output buffer is forcibly fixed to the ground potential, and the output buffer of the output buffer. A delay circuit section that delays the input signal by a delay time equal to the delay time of the noise removal section and outputs the inverted polarity signal is compared with this delay circuit section output signal and the noise removal section output signal. It has a mismatch detection section that outputs, a counting circuit section that counts the mismatch signal, and a storage circuit section that stores an overflow signal generated as a result of the counting, and shifts to the test mode by the storage circuit output signal, The test mode can be released by resetting the memory circuit unit and the counting circuit unit.

Further, the test mode setting section used in the test mode transition means outputs a signal when the output signal of the output buffer is forcibly fixed to the power supply potential and an input signal of the output buffer to a predetermined delay time. The output signal of the delay circuit unit that delays by only the comparison signal has a coincidence detection unit that outputs a coincidence signal if the output signals of the delay circuit unit are equal to each other, and a memory circuit unit that stores the coincidence signal. However, the test mode can be released by resetting the memory circuit unit. It can also be excluded.

The microcomputer test method of the present invention is characterized in that an input buffer receives an externally supplied signal and supplies it to an internal circuit, and outputs the processing result of this internal circuit from the output buffer to the outside to output these inputs and outputs. A buffer group having an input / output buffer having both functions, and a test mode setting means for setting the state of the internal circuit to either an operation mode, a reset mode or a test mode in response to a mode setting signal supplied from the outside. In a microcomputer test method for confirming predetermined electrical characteristics of the internal circuit and the buffer group using, when a high level is output from the output buffer to the output terminal, a part of the high level period Only LS
When the output terminal is forcibly fixed to a low level by the I tester and a high level is output from the output buffer to the output terminal, the output terminal is forced by the LSI tester for a part of the low level period. Is fixed to the high level, and the signal of the output terminal fixed to the low level or the high level for a part of this period is waveform-shaped by the noise removing means, and the input signal of the output buffer is delayed by a delay equal to the delay time of the noise removing means. Delayed by the delay means, the inverted signal of the delayed output signal and the output signal of the noise removal means are compared by the mismatch detection means, and if they are not equal, a mismatch signal is output, and the mismatch signal is counted by the counting means. And the overflow signal generated as a result of counting is stored in the storage means,
The output signal of the storage means causes the test mode setting means to shift the internal circuit to the test mode, and the storage means and the counting means are reset by a predetermined signal supplied from the internal circuit, whereby the test mode setting means. Is to cancel the test mode.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In contrast to the conventional microcomputer test circuit and test method described above, according to the present invention, one terminal used only as an output terminal during normal operation is used in an electrical characteristic test using an LSI tester. The difference is that it is used as a terminal for setting the test mode.

First, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a circuit diagram showing a first embodiment of the present invention, FIG. 1B is a circuit diagram of a noise removing unit used in FIG. 1A, and FIG. It is a timing chart for.

Referring to FIG. 1A, in this test circuit, the output signal of the output buffer 1 is forcibly forced to the power supply potential VD.
The noise eliminator 2 that eliminates noise when fixed to D or the ground potential GND, the delay element 3 that delays the input signal of the output buffer 1 by a delay time equal to the delay time of the noise eliminator 2, and the polarity is inverted. An inverter 4 that outputs a signal, a mismatch detection unit 5 that compares two input signals and outputs a mismatch signal if they are not equal, an up-counter counting circuit unit 6 that counts the mismatch signals, for example, A latch storage circuit section 7 having a reset function, a terminal 8 is connected to the input terminal of the input buffer 1, and one input terminal of the mismatch detection section 5 is connected via the delay element 3 and the inverter 4. Is also connected. The output terminal of the output buffer 1 is connected to the output terminal 9 and the input terminal I of the noise removal unit 2, and the output terminal O thereof is connected to the other input terminal of the mismatch detection unit 5.

The output terminal of the mismatch detection section 2 is connected to the count signal input terminal D of the counting circuit section 6, and the count signal output terminal OVF is connected to the set terminal S of the storage circuit section 7. The output terminal Q of the storage circuit section 7 is connected to the terminal 10 as a test test mode setting circuit output, and the test mode release signal line is connected to the reset terminal C of the storage circuit section 7 and the counting circuit section 6 from the terminal 11. It consists of different configurations.

The noise eliminator 2 used here is a known circuit. Referring to FIG. 1B, the configuration is such that the terminal I is connected to the delay element 201, the AND gate 202 and the NOR gate 203. , The delay element 2 is provided at the other input end of the AND gate 202 and the NOR gate 203.
The output terminal of 01 is connected. The output terminal of the AND gate 202 is connected to the NOR gate 204 of the flip-flop composed of the NOR gates 204 and 205, and the NOR gate 203.
Of the NOR gate 2 are connected to the NOR gate 205 as set and reset lines, respectively.
The output of 04 is connected to the terminal O via the inverter 206.

Next, the operation of this embodiment will be described with reference to FIG. 2 in addition to FIGS. 1 (a) and 1 (b).

When the waveform supplied from the internal circuit to the terminal 8 is at the low level for a predetermined period as shown in FIG. 2A, the waveform observed at the external terminal 9 is inverted by the output buffer 1 and is further driven and overdriven. The waveform has a shoot and an undershoot (Fig. 2 (b)).

During the period in which a high level is output among such waveform outputs, the LSI tester operates the external terminal 9
Is temporarily shorted to the ground potential GND, a low level period occurs while the output waveform becomes dull due to a transient phenomenon (FIG. 2 (d)).

This waveform corresponds to the delay element 2 of the noise removing section 2.
After being delayed by time t at 01, AND gate 202 performs a logical product and both ends are high level (see FIG. 2).
(E)) is ORed in the OR gate 203 and both ends are at a low level (FIG. 2 (f)). Of these signals, the flip-flop of the next stage is set at the rising timing of the output signal of the AND gate 202 from the low level to the high level, and the OR gate 2
The output signal of No. 03 is reset at the timing of rising from the low level to the high level, and an output signal having a waveform shaped is obtained (FIG. 2 (g)). The output signal of the noise removing unit 2 becomes one input of the mismatch detecting unit 5.

Similarly, the signal supplied from the internal circuit (see FIG.
(A)) is delayed from the output buffer 1 by the delay element 3 and the inverter 4 whose delay time is designed in advance so that the delay time becomes equal to that of the noise removing section 2 (FIG. 2 (h)). Is the other input of the mismatch detection unit 5.

Therefore, the mismatch detection section 5 inverter 4
Then, the signals of the noise detection unit 2 are compared with each other to generate a high level signal in the non-coincidence period (FIG. 2 (i)), which is supplied as an input signal of the counting circuit unit 6.

To make the delays of the signals of both inputs of the above-mentioned mismatch detection section 5 equal, for example, the signal delay times in FIGS. 2G and 2H are different and the rising timings are Xnsec. Assuming that there is a phase difference, the mismatch detection unit 5 detects mismatch points of Xnsec at the first rising edge and the last falling edge of the waveforms of (g) and (h) of FIG.
Therefore, non-coincidence points are generated at three positions, that is, both ends and the central part, and three non-coincidence signals, which should be one originally, are generated, and these three pulses are counted by the counting circuit unit 6. This causes inconvenience. That is, if the phases of the signals of both inputs of the mismatch detection section 5 are deviated, it is meaningless that the noise removal section 2 has shaped the waveform.

In the counting circuit section 6, the supplied high level signal in the non-coincidence period is counted each time. The counting circuit unit 6 is inserted in order to further reduce the possibility of accidental malfunction by passing through the counting circuit 6 even if a malfunction due to noise occurs.

The operation up to this point is repeatedly executed until an overflow occurs. That is, the output terminal 9 is repeatedly short-circuited to the ground potential GND by the LSI tester.

Latch 7 when an overflow signal occurs
Takes in this signal and holds its state, and is notified from the output terminal Q to the internal circuit as a test mode setting signal via the terminal 10.

The test mode release signal is supplied from the internal circuit via the terminal 11, and the contents of the latch 7 and the counting circuit section 6 are cleared.

The terminal 11 is also used as a reset input for initialization of the microcomputer.

As described above, the test of the microcomputer incorporating the test mode setting circuit of this embodiment is LS.
Performed by I Tester. When the external terminal 9 is forcibly short-circuited to the ground potential GND while outputting a high level, a direct current flows through the output buffer 1. However, in an LSI tester, a resistance element or reverse current prevention is generally provided between the external terminal and the ground potential GND. Inserting the clamping diode for is easily set by the program,
It does not damage the output buffer 1.

Next, referring to FIG. 3 which shows the circuit diagram of the test mode setting circuit of the second embodiment, the difference from the first embodiment is that the delay of the noise removing section 2 in the first embodiment is different. The inverter 4 and the counting circuit unit 6 of the circuit unit are omitted, and the match detection unit 12 is used instead of the mismatch detection unit 5. Since the other constituent elements are the same as those in the first embodiment, the same constituent elements are designated by the same reference numerals.

That is, in the circuit of the second embodiment, the terminal 8 is connected to the input terminal of the input buffer 1 and
It is also connected to one input end of the coincidence detection unit 12 via the delay element 3. The output end of the output buffer 1 is connected to the output terminal 9 and the other input end of the coincidence detection unit 12.

The output terminal of the coincidence detecting section 12 is connected to the storage circuit section 7.
Of the storage circuit section 7 is connected to the terminal 10 as the output of the test test mode setting circuit, and the reset terminal C of the storage circuit section 7 is connected to the test mode release signal line of the terminal 11. The configuration is connected from.

In the first embodiment, noise generated in the external output signal, which is the output of the microcomputer itself, does not affect the microcomputer itself. Was needed. Further, the counting circuit section 6 is for reducing the possibility of accidental malfunction by passing through the counting circuit 6 even if malfunction due to noise occurs.

The test circuit of the second embodiment having the above-described configuration has a smaller drive capability of the output buffer 1 than the first embodiment, and the output waveform of the external terminal 9 has almost no overshoot or undershoot. If it does not occur, the above consideration can be omitted, and the same effect can be expected by simplifying the circuit configuration.

The test method of the microcomputer incorporating the test circuit of the first or second embodiment described above is as follows:
Referring to FIG. 4 showing an outline of the measurement system of the LSI tester and FIGS. 5A and 5B showing timing charts for explaining the test method, FIG. Device (DUT), here, a measurement system having only one pin of the microcomputer 24.

During normal function operation measurement, L
The SI tester supplies a signal to the DUT 24 based on the test pattern. This test pattern is generated through the driver control circuit 15 by the driver (DRV) 18 which generates the voltage of the input level VIH / VIL to the preprogrammed input buffer.

On the other hand, the signal output from the DUT 24 to the LSI tester is supplied to the two comparators 19 and 20. These signals are output levels VOH / VOL of the output buffer pre-programmed in the comparator.
And the high level and low level values are determined.

The signal of this judgment result is compared with the expected value of the test pattern by the comparator control circuit 16,
It is determined whether the DUT 24 is working properly.

When measuring the DC characteristics, the DC measuring circuit 1
7 to Sense 22 and Force (FORC)
E) 21 is connected to DUT 24. FORCE is DU
It is a circuit that supplies a predetermined measurement voltage to T24, and SE
NSE is a circuit that receives the output of the DUT 24 and measures its voltage value.

For connection to the DUT 24, only one of the driver 18, the comparators 19 and 20, or the DC measuring circuit 17 is selected by the multiplexer 23.

FIG. 5 (a) showing a timing chart for explaining the test method when the output buffer is a Hibel output.
5 (a) is a waveform expected to be supplied from the DUT 24 to the comparators 19 and 29 in the normal operation, and FIG. 5 (a) shows the waveform in this embodiment. A waveform showing that 0V is set in advance in the DC measurement circuit 17 of the LSI tester in order to forcibly supply a low level to the output terminal 9 of the output buffer to enter the test mode, FIG. DC measuring circuit 17
In order to connect 0 to supply a preset 0V to the output terminal 9, the multiplexer 25 is connected to the DC measuring circuit 17
Control signal 2 provided to select
5 (a (d)) is the waveform actually output from the DUT 24 as a result of 0 V being selectively supplied to the output terminal 9, and FIG. 5 (a (e)) is the waveform actually output from the DUT 24. 7 is a waveform of a multiplexer control signal 25 supplied to cause the multiplexer 25 to select the comparator control circuit 16 in order to measure the high level of the output waveform.
When the multiplexer control signal is at a high level, the DUT 24 is connected to any of the comparators 19 and 20 or the DC measuring circuit 17.

Therefore, the high level periods in FIGS. 3C and 3E must be controlled exclusively.

In this embodiment, the DC measuring circuit 17 is connected by the high level signal of the multiplexer control signal (C) during the disconnection period of the comparators 19 and 20.

At this time, since the DC measuring circuit 17 is preset to 0V, that is, the ground potential GND level, the actual output waveform of the DUT 17 during the period in which the DC measuring circuit 17 is connected is short-circuited to the ground potential GND. Then, a waveform as shown in FIG.

On the other hand, in the diagram (d), while the DUT 24 is outputting a high level, the multiplexer control signal (e) outputs a low level to disconnect the connection with the comparators 19 and 20.

Further, FIG. 5 is a timing chart for explaining a test method when the output buffer is low-bell output.
Referring to (b), FIG. 5 (b) is a waveform expected to be supplied from the DUT 24 to the comparators 19 and 29 in the normal operation.
In order to forcibly supply the high level to the output terminal 9 of the output buffer in the present embodiment to enter the test mode,
A waveform showing that + 5V is set in the DC measurement circuit 17 of the LSI tester in advance, FIG. 5B shows that the DC measurement circuit 17 is connected and the preset + 5V is supplied to the output terminal 9. , DC in the multiplexer 25
The waveform of the multiplexer control signal 25 supplied to select the measurement circuit 17, FIG. 5 (b (d)) is a waveform actually output from the DUT 24 as a result of selectively supplying +5 V to the output terminal 9, 5 (b (e)) is DUT24
The multiplexer control signal 25 supplied to cause the multiplexer 25 to select the comparator control circuit 16 in order to measure the low level of the waveform actually output from the multiplexer 25.
Is the waveform of.

Therefore, also in this case, the high level periods in FIGS. 3C and 3E must be controlled exclusively.

At this time, since the DC measuring circuit 17 is set to + 5V, that is, the power supply potential VDD level in advance, the actual output waveform of the DUT 17 during the period when the DC measuring circuit 17 is connected is pulled to the power supply potential VDD. Then, the waveform is generated as shown in Fig. 2D.

On the other hand, in FIG. 9D, the multiplexer control signal (e) outputs a low level while the DUT 24 is outputting a low level, whereby the connection with the comparators 19 and 20 is disconnected.

By repeating the above control on the LSI tester, the DUT 24 can be set to the test mode.

[0070]

As described above, according to the present invention, the waveform shaping circuit for removing noise when the output signal of the output buffer is forcibly fixed to the power supply potential or the ground potential, and the input signal of the output buffer are waveform-shaped. A delay circuit that delays by a delay time equal to the delay time of the shaping circuit, inverts the polarity, and outputs the result.
The delay circuit output signal and the waveform shaping circuit output signal are compared, and if they are equal, a coincidence detection circuit that outputs a coincidence signal, a counting circuit that counts the coincidence signal, and a storage circuit that stores an overflow signal generated as a result of counting are provided. The test mode transition method is such that when the output of the output buffer is high level, the output terminal is forcibly fixed to the ground potential for a predetermined period within the high level period, and when the output of the output buffer is low level. , By forcibly fixing the output terminal to the power supply potential for a predetermined period within the low-level period, the fact that the fixing operation has been performed a predetermined number of times is detected and stored, and the test mode is entered when the predetermined number is reached. Therefore, as the input terminal for setting the test mode, one terminal that is used only as an output terminal during normal operation and its output buffer are used. It is possible to provide a microcomputer with a reduced production cost which does not require a plurality of control data and these identification circuit for entering the plurality of input terminals and the test mode for identifying a main signal.

During operation, the output terminal is connected to the ground potential GND.
Short-circuiting to etc. is a basic prohibition for handling semiconductor elements, and it is unlikely that it will be implemented by the user. Therefore, the present invention is very effective as a pre-shipment test method performed by the manufacturer.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing a first embodiment of the present invention. FIG. 1B is a circuit diagram of the noise removing unit used in FIG.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a circuit diagram of a test mode setting circuit according to a second embodiment.

FIG. 4 is a diagram showing an outline of a measurement system of an LSI tester.

FIG. 5A is a timing chart for explaining a test method when the output buffer is a Hibel output. (B) is a timing chart for explaining a test method when the output buffer is low-bell output.

FIG. 6 is a circuit diagram of an example of a conventional test mode setting unit.

FIG. 7 is a block diagram of an example of a conventional test mode control method.

[Explanation of symbols]

1 Output Buffer 2 Noise Removal Section 3,201 Delay Element 4,206 Inverter 5 Mismatch Detection Circuit 6 Counting Circuit Section (Up Counter with Clear Function) 7 Storage Circuit Section (Latch with Reset Terminal) 8, 10, 11 Terminals (Internal Signal) Input) 9,306 Output terminal 10 terminal (Test mode setting signal output) 11 terminal (Test mode release signal input) 12 Match detection circuit 15 Driver control circuit 16 Comparator control circuit 17 DC measurement circuit 18 Driver (DRV) 19, 20 Comparator (CMP) 21 FORCE 22 SENSE 23 Multiplexer 24 DUT 25 Multiplexer control signal 202 AND 203, 204, 205 NOR D1, D2, D3 Depletion type MOS transistor N1 Enhancement type MOS transistor IN Test terminal OUT Test mode output terminal 300a to 300n External terminal 301 Decoding circuit 302 Processing circuit 303, 305 OR gate 304 Timer

Claims (7)

[Claims] 1. A buffer group including an input buffer receiving an externally supplied signal, an output buffer outputting the processing result of an internal circuit, and an input / output buffer having both functions, and a mode setting signal externally supplied. In response to a test mode setting section for setting the state of the internal circuit to any one of an operation mode, a reset mode or a test mode; A microcomputer having a test mode shift means for shifting the test mode setting unit to the test mode by externally forcibly fixing the power supply potential or the ground potential to a predetermined period. Test circuit. 2. The test mode transition means forcibly fixes the output terminal to the ground potential for a predetermined period within the high level period when the output of the output buffer is at the high level, and the fixing operation thereof. 2. The test circuit for the microcomputer according to claim 1, further comprising a function of detecting and storing that the test has been performed a predetermined number of times, and transitioning to the test mode when the predetermined number of times is reached. 3. The micro according to claim 2, wherein the test mode transition means forcibly fixes the output terminal to the power supply potential for a predetermined period within the low level period when the output of the output buffer is low level. Computer test circuit. 4. The test circuit for a microcomputer according to claim 2, wherein the setting result is stored only in a storage means, and a function of shifting to the test mode is provided according to the stored content. 5. The test mode setting section used for the test mode transition means, a noise removing section for removing noise when the output signal of the output buffer is forcibly fixed to the ground potential, and the output buffer of the output buffer. A delay circuit section that delays the input signal by a delay time equal to the delay time of the noise removal section and outputs the inverted polarity signal is compared with this delay circuit section output signal and the noise removal section output signal. It has a mismatch detection section that outputs, a counting circuit section that counts the mismatch signal, and a storage circuit section that stores an overflow signal generated as a result of the counting, and shifts to the test mode by the storage circuit output signal, 3. The test circuit for a microcomputer according to claim 1, wherein the memory circuit unit and the counting circuit unit are reset to release the test mode. . 6. The test mode setting unit used in the test mode transition means sets a signal when the output signal of the output buffer is forcibly fixed to a power supply potential and an input signal of the output buffer to a predetermined delay time. The output signal of the delay circuit section that delays by just the comparison signal has a coincidence detection circuit that outputs a coincidence signal if they are equal, and a storage circuit section that stores the coincidence signal. The storage circuit output signal shifts to the test mode. 4. The test circuit for a microcomputer according to claim 1, wherein the memory circuit unit is reset to release the test mode. 7. A buffer group in which an input buffer receives an externally supplied signal, supplies it to an internal circuit, outputs the processing result of this internal circuit from the output buffer to the outside, and the input / output buffer has both functions of input and output. And a test mode setting means for setting the state of the internal circuit to any one of the operation mode, the reset mode or the test mode in response to a mode setting signal supplied from the outside. In a microcomputer test method for confirming a predetermined electrical characteristic, when a high level is output from the output buffer to the output terminal, the output terminal is forced by the LSI tester for a part of the high level period. Is fixed to low level and high level is output from the output buffer to the output terminal. In the low level period, the output terminal is forcibly fixed to the high level by the LSI tester only for a part of the low level period, and the signal of the output terminal fixed to the low level or the high level for the part period is the noise removing means. The waveform is shaped, the input signal of the output buffer is delayed by the delay means by a delay time equal to the delay time of the noise removal means, and the inversion signal of the delayed output signal and the output signal of the noise removal means are detected to be inconsistent. If they are not equal, a non-coincidence signal is output, the non-coincidence signal is counted by the counting means, an overflow signal generated as a result of the counting is stored in the storage means, and the test mode setting means is output by the output signal of the storage means. The internal circuit is shifted to the test mode, and a predetermined signal supplied from the internal circuit is used. A test method for a microcomputer, wherein the storage means and the counting means are reset and the test mode setting means releases the test mode.