JPH08272335A - Ac discharge type matrix system plasma display panel driving device - Google Patents

Abstract

PURPOSE: To enlarge a selection margin of a pixel cell without reducing a voltage level of a reset pulse by preventing discharge between row electrode pair caused by only a wall charge provided in the cell and lefting the wall charge of a proper amount in the cell until a scan pulse is applied. CONSTITUTION: In a display device 18, a row electrode drive pulse generation circuit 10a applies the voltage levels responding to the pulses to corresponding row electrodes X1 -Xn , Y1 -Yn in response to various pulses supplied from a read- out timing signal generation circuit 7a. When the pixel cell before the pixel data are written is reset, by that further discharge is made to be generated in the cell having the wall charge, and the wall charge of the cell is reduced forcedly until a prescribed amount, as a result, the wall charge amount provided in the cell is reduced, no discharge between row electrode pair is generated only by the wall charge provided in the cell. Thus, the cell holds the wall charge of a required amount, that is, the proper amount until the scan pulse is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for an AC discharge type matrix type plasma display panel (hereinafter referred to as PDP).

[0002]

2. Description of the Related Art As is well known, PDPs have recently been studied as one of thin secondary screen displays, and one of them is an AC discharge type matrix PDP having a memory function. Are known. The structure of a display device including such a PDP is shown.

Such a display device comprises a signal processing section A for processing a so-called composite video signal as an input signal, and a display section B for receiving a drive signal from the signal processing section A and displaying a two-dimensional screen. . In the signal processing unit A,
The A / D converter 3 converts the input composite video signal into, for example, 8-bit pixel data. On the other hand, the timing pulse generating circuit 2 generates various timing pulses based on the horizontal and vertical synchronizing signals extracted from the input composite video signal by the sync separating circuit 1. The A / D converter 3 operates in synchronization with these timing pulses. The memory control circuit 5 supplies write and read pulses synchronized with the timing pulse from the timing pulse generation circuit 2 to the frame memory 4 to sequentially read pixel data from the A / D converter 3 into the frame memory 4. To the output processing circuit 6 of the next stage.

The read timing signal generating circuit 7 generates a timing signal corresponding to the supply timing of the pixel data pulse and supplies it to the output processing circuit 6. The read timing signal generation circuit 7 also generates various timing signals corresponding to the driving state of each pixel cell and supplies these to the row electrode drive pulse generation circuit 10. Output processing circuit 6
Supplies pixel data to the pixel data pulse generation circuit 12 in synchronization with the timing signal from the read timing signal generation circuit 7.

On the other hand, the PDP 11 has column electrodes D1, D2,
D3 ... Dm-1 and Dm and a row electrode X which is orthogonal to the column electrode and which forms a row by forming a pair with Xi and Yi
1, X2, X3, X4 ... Xn and Y1, Y2, Y3, Y
4 ... Yn-1 and Yn. These column electrode and row electrode pairs face each other with a dielectric (not shown) in between to form a pixel cell.

The pixel data pulse generation circuit 12 generates a pixel data pulse corresponding to each pixel data supplied from the output processing circuit 6 and applies it to each of the column electrodes D1 to Dm. The row electrode drive pulse generating circuit 10 responds to the timing pulse from the read timing signal generating circuit 7 by applying a reset pulse having a high voltage level to all the row electrodes X.
Applied to 1 to Xn and Y1 to Yn. Next, in response to the timing signal from the read timing signal generating circuit 7, a scanning pulse for selecting a light emitting or non-light emitting cell is applied to the row electrodes Y1 to Yn. Next, the row electrode drive pulse generation circuit 10 generates a sustain pulse having a potential for maintaining the light emitting state based on the written data in response to the timing signal from the read timing signal generation circuit 6 to generate the sustain pulse of the PDP 11. Row electrodes Y1 to Yn and row electrodes X1 to
Apply to Xn respectively. At this time, sustain pulses are applied to the X and Y electrodes at mutually shifted timings.

Next, the driving operation of the PDP 11 having such a configuration will be described with reference to FIG. The row electrode driving pulse generating circuit 10 to initialize each cell, at the same time the application of a reset pulse RPx of negative voltage at time t ₁ in each of the row electrodes X1 to Xn, the row electrodes Y1 -Yn
A positive voltage reset pulse RPy is applied to each of them to generate a discharge between the row electrode pair Xi and Yi. Next, the pixel data pulse generation circuit 12 applies a positive pixel data pulse corresponding to the pixel data in each row from the time t ₄ to the column electrode D1.
To Dm are sequentially applied.

In the figure, at time t ₄ , the scanning pulse SP and the first-row pixel data pulse are simultaneously applied to the first-row electrode Y 1. At this time, since the cells have wall charges in advance, the first charges are generated due to the potential difference generated by the wall charges and the scanning pulse SP and the pixel data pulse.
Discharge emission occurs in the selected cell in the row. Then, the row electrode driving pulse generating circuit 10 at time t _5,
The positive sustain pulse IA is applied to each of the row electrodes X1 to Xn at the same timing. Further, the row electrode drive pulse generation circuit 10 causes the positive sustain pulse I at time t ₆ .
B is applied to each of the row electrodes Y1 to Yn at the same timing.

That is, at the time t _{1 as} described above,
When the potential difference between Xi and Yi due to the reset pulse in the cell exceeds the discharge start voltage, discharge occurs, and the electric charge generated by this discharge remains on the boundary between the dielectric and the electrode to form wall charge. Since the wall charges remain in the dielectric of the cell due to the discharge of the cell, the discharge can be performed again by applying a voltage lower than the above-mentioned discharge start voltage. Therefore, after the discharge light emission is selected by applying the scan pulse SP and the pixel data pulse DP, the sustaining pulse IA of a relatively small voltage level applied to the X electrode at time t ₅ causes
The discharge light emission again occurs in the first row. At this time, this re-discharge also ends in an instant, but the sustain pulse IB applied to the Y ₁ electrode at time t ₆ causes discharge light emission in the first row again. While such operation is shown in FIG. As, until the erase pulse KP is applied at time t _7, the light emitting state of the discharge is repeatedly executed by the cell is continued by applying a plurality of sustain pulses.

[0010]

In the PDP having the above-mentioned structure, the reset pulse applied at the time of initializing, that is, resetting the cell, in order to stably discharge,
Since it is necessary to take a large potential difference between the row electrode pair Xi and Yi, the voltage level of the reset pulse is considerably higher than the levels of the scan pulse and the sustain pulse. However, when the potential difference between the pair of row electrodes Xi and Yi is increased, the wall charges remain excessively. Therefore, for example, when the potential difference between the row electrodes Xi and Yi returns to zero at time t ₂ , the wall of the cell has Row electrodes Xi, Y
A discharge may occur during i and a significant amount of wall charge may disappear, for example at time t ₃ , before the scan pulse is applied. Therefore, since the amount of wall charges remaining in the cell is small, there is a problem that the selection margin between the cell selected to emit light and the non-light emitting cell is reduced by writing the pixel data at time t ₄ .

In view of the above problems, it is an object of the present invention to provide a driving device for an AC discharge matrix type PDP which allows a large selection margin of pixel cells without reducing the voltage level of a reset pulse. Is.

[0012]

A driving device for an AC discharge type matrix PDP according to the present invention comprises a plurality of row electrode pairs, each pair extending in parallel to each other in the horizontal direction, and a pair of the row electrode pairs. A plurality of column electrodes extending vertically through a dielectric layer to form pixel cells in the vicinity of intersections with the row electrode pairs, and row electrode driving means for supplying a reset pulse and a scan pulse to the row electrode pairs. And a row electrode driving means for applying a first reset pulse having a predetermined polarity to one row electrode of the row electrode pair and the other row electrode driving means. A second reset pulse having a potential opposite to the predetermined polarity and having a potential difference from the potential of the first reset pulse that exceeds the discharge start voltage between the row electrode pair is applied to the electrodes. A wall charge is generated in each of the pixel cells, and then a rear edge portion of the second reset pulse with respect to the other row electrode has a front edge portion that is close in time to the second reset pulse. Applies a third reset pulse having an opposite polarity and having a potential for generating a discharge between the row electrode pair to reduce the amount of charge possessed by each of the pixel cells, and then scan the row electrode pair. A pulse is applied.

[0013]

According to the present invention, the row electrode driving means applies the first reset pulse having the predetermined polarity to one of the row electrodes of the row electrode pair, and simultaneously applies the second reset having the opposite polarity to the predetermined polarity to the other row electrode. By applying a pulse, a discharge is generated between the pair of row electrodes to generate a wall charge amount in each pixel cell, and in time proximity to the end of application of the second reset pulse, a second reset is applied to the other row electrode. By applying a third reset pulse having a polarity opposite to that of the pulse, the row electrode pair is forcibly discharged to reduce and hold the charge amount of the pixel cell, and then the scan pulse is applied to the row electrode pair.

[0014]

Embodiments of the present invention will be described with reference to FIGS. FIG. 3 shows a display device 18 including a driving device according to the present invention and a PDP driven by the driving device.
Shows the configuration of. The display device 18 includes a read timing signal generation circuit 7a and a row electrode drive pulse generation circuit 10
Except for a, the display device has the same structure as the conventional display device shown in FIG. Note that, in FIG. 3, the components having the same reference numerals as those in FIG. 1 have the same functions as the components in FIG.

The read timing signal generation circuit 7a generates and supplies a timing signal corresponding to the supply timing of the pixel data pulse to the output processing circuit 6. Further, the read timing signal generation circuit 7a initializes the cell as a pulse for driving the pixel cell to the row electrode drive pulse generation circuit 10a, and first and second for generating wall charges in the cell. Reset pulse RP1, RP
2, a third reset pulse RP3 for reducing the generated wall charges to a desired amount, a scan pulse EP for writing pixel data to select light emission, a sustain pulse SP for maintaining discharge light emission, and discharge light emission The erase pulse KP for stopping is generated and supplied.

The row electrode drive pulse generation circuit 10a responds to various pulses supplied from the read timing signal generation circuit 7 and applies a voltage level corresponding to the pulse to the corresponding row electrodes X1 to Xn and Y1 to Yn. To do. FIG.
2 is a configuration diagram showing details of the PDP 11 and is denoted by reference numeral 2
Reference numeral 0 indicates a plurality of pixel cells of an AC surface discharge type PDP having a three-electrode structure driven by the driving device according to the present invention. The pixel cell 20 includes a front glass substrate 22 and a rear glass substrate 24 made of transparent glass, which face each other in parallel with a gap of 100 to 200 μm therebetween, and extend in parallel to each other in the vertical direction of the rear substrate 24 and are adjacent to each other. Partition walls 26 and 2 that meet
A discharge space 28 is defined by 6 and 6.

The front substrate 22 serves as a display surface, and a plurality of row electrodes Xi, Yi (i = 1, 2, ... And tin oxide (SnO) are formed by vapor deposition of tin oxide (SnO) and the like in a horizontal direction with a film thickness of about several hundreds of nm. In order to enhance the conductivity of the row electrodes Xi and Yi,
The metal bus electrodes αi and βi, which are narrower than the widths of the row electrodes Xi and Yi, are used as auxiliary electrodes for the row electrodes Xi and
It is formed in close contact with Yi. Further, two row electrodes Xi and Yi adjacent to each other are paired to form a row electrode pair (Xi, Yi
Yi). Next, a dielectric layer 30 having a film thickness of about 10 μm is formed so as to cover these row electrodes Xi and Yi, and magnesium oxide (M
A MgO layer 32 made of gO) is laminated to have a film thickness of approximately several hundred nm.

On the other hand, in the rear substrate 24, the front substrate 2
The partition wall 26 formed to maintain the gap between the two is formed by using, for example, a thick film printing technique, and the longitudinal direction is the row electrodes Xi, Y.
They extend in a direction orthogonal to i and are formed in parallel with each other so as to have a width of 50 μm and an interval of 300 μm, for example.
Further, the column electrodes Dj (j = 1,2, ..., m) made of, for example, aluminum (Al) or an aluminum alloy are arranged between the partition walls 26, 26 adjacent to each other in the extending direction of the row electrodes Xi, Yi. It is formed in a film thickness of about 100 nm in the orthogonal direction. This column electrode Dj is made of a metal having a high reflectance, such as Al or an Al alloy, and therefore has a wavelength band of 38.
It has a reflectance of 80% or more at 0 to 650 nm.
The column electrode Dj is not limited to Al or Al alloy, and can be made of an appropriate metal or alloy such as Cu or Au having high reflectance.

Further, a phosphor film 36 is formed as a light emitting layer with a film thickness of, for example, 10 to 30 μm while covering each column electrode Dj. As described above, each electrode Xi, Yi, D
The front substrate 22 and the rear substrate 24 on which the dielectric layer 30 and the light emitting layer 36 are formed are sealed and the discharge space 28 is evacuated, and the moisture on the surface of the MgO layer 32 is removed by baking. . Next, the discharge space 28 is filled and sealed with a rare gas such as Ne.Xe gas or He.Xe gas.

In this way, the pair of row electrodes Xi, Y
A discharge space surrounded by i and a column electrode Dj orthogonal to the row electrode is defined as one pixel cell Pi, j, and the pixel cell Pi, j excites the phosphor by the discharge between the electrodes Xi, Yi, Dj. It emits light. That is, in each pixel cell, the start, maintenance and erasure of light emission of the pixel cell Pi, j are controlled by the voltage application between the electrodes Xi, Yi and Dj.

The operation of the above configuration will be described with reference to FIGS. FIG. 5 is a diagram showing changes over time of various pulses applied to the PDP, and FIG. 6 shows the potential of the row electrode pair Xi, Yi and the column electrode Dj and the state of the amount of electric charge in one pixel cell Pi, j. It is a figure showing a model. Figure 5
As shown in FIG. 5, the PDP repeatedly displays one subfield including a pixel cell reset period (a), a cell writing period (b), a sustain discharge period (c), and a full erase period (d). Do it dynamically.

In the reset period (a), all the row electrodes Xi are reset at time t ₁ as shown in FIG. 6A in order to collectively initialize the pixels for which the previous subfield has finished.
, Yi, a reset pulse is applied. That is, a negative potential -Vx having a high voltage level of -150V, for example, is applied to the row electrode Xi as the first reset pulse RP1, and at the same time, a positive potential + Vy having a high voltage level of + 150V, for example, is applied to the row electrode Yi. Second reset pulse R
It is applied as P2. At this time, a pair of row electrodes Xi, Y
When the first potential difference | Vx + Vy | generated at i exceeds the discharge start voltage between the row electrode pairs, the cell starts discharge.
This discharge is instantly terminated, and the first amount of wall charges generated by the discharge remains in the dielectric layer as shown in FIG. 6 (2).

Next, the corresponding first electrodes to the row electrodes Xi and Yi
And immediately after the application of the second reset pulse,
At time t ₂ , only one row electrode of the row electrode pair, for example, all the row electrodes Xi, is supplied with the positive potential + Vz having the opposite polarity to the first reset pulse, which is the third reset pulse RP3.
As shown in FIG. 6C, the voltage is applied. This third
The reset pulse RP3 has a voltage level smaller than the potential difference between the first and second reset pulses described above. Further, the third reset pulse is applied such that the leading edge portion is close to the trailing edge portion of the first reset pulse on the time axis.

At this time, since the row electrode Xi has wall charges generated by the discharge due to the application of the first and second reset pulses, the cell starts discharging again even if the voltage level of the third reset pulse is small. To do. Such discharge ends in an instant. Further, this discharge has a smaller potential difference between the row electrodes Xi and Yi than the discharges caused by the first and second reset pulses. Therefore, the wall charges remaining on each row electrode at time t ₃ due to the discharge are as shown in FIG. It becomes smaller than the first amount as shown in 4).

The application of the third reset pulse RP3 can be performed close to the end of the application of the second reset pulse on the time axis. Further, in the above operation, the third reset pulse is applied to the row electrode Xi, but instead of this, the third reset pulse can be applied to the row electrode Yi. In this case, the third reset pulse has a polarity opposite to that of the second reset pulse (negative polarity in FIG. 5), and a leading edge portion adjacent to the trailing edge portion of the second reset pulse on the time axis. With a pulse.

In the next section (b), the pixel data is supplied at time t ₄ , the pixel data pulse DP1 corresponding thereto is applied to the column electrode, and the scanning pulse EP is applied to the row electrode Y1. It By the pixel data pulse and the scan pulse, when the cell is caused to emit light in the next section (c) according to the supplied data signal, the wall charge is maintained, or the cell is not turned on in the next section (c). When emitting light, the wall charges are extinguished. In this manner, the pixel data for display is written in the PDP 11 one after another by the corresponding pixel data pulse and scan pulse sequentially supplied to each of the column electrode Di and the row electrode Yi.

Next, in the section (c), the row electrode Xi
, Yi are alternately applied to the sustaining pulse SP, so that the pixel data written in the section (b) is held. At this time, only the cells in which the wall charge is stored in the previous section (b) are applied with the sustain pulse, and the row electrode X is generated by the charge energy of the wall charge itself and the energy of the sustain pulse.
Discharge occurs between 1 and Y1 to cause the cell to emit light. On the other hand, in the cell in which the wall charges have been erased, the potential difference Vs generated in the cell only by the sustain pulse is lower than the discharge start voltage, so that the discharge is not generated in the cell, and therefore the cell does not emit light.

Next, when the erase pulse KP is applied to all the row electrodes Yi at time t ₅ , the light emission discharge of the cells is stopped and all the pixel data written in the cells are erased in the section (b). To be done. As described above, the driving device of the present invention generates the wall charges in each pixel cell in the section (a) to hold an appropriate amount, and sequentially writes the pixel data in each pixel cell in the section (b), The cells are discharged and displayed based on the pixel data written in c), and display is performed in the interval (d).
The display is stopped at.

Further, the above-mentioned driving device, when initializing (resetting) the pixel cell before writing the pixel data, causes further discharge in the cell having the wall charge to forcibly reduce the wall charge of the cell to a desired amount. As a result, the amount of wall charges possessed by the cell becomes smaller than the above-mentioned first amount, so that the discharge between the row electrode pairs is not generated only by the wall charges possessed by the cell. Thus, the cell can hold a desired or appropriate amount of wall charge until a scan pulse is applied.

In the above embodiment, the first and second
The voltage level of the reset pulse is not limited to 150V, but may be an appropriate voltage level for preventing excessive wall charge from remaining in the cell. Also, the voltage levels of the first and second reset pulses can be set to different absolute values.

[0031]

According to the present invention, the first reset pulse is applied to one row electrode of the row electrode pair and the second reset pulse having the opposite polarity to the first reset pulse is applied to the other row electrode. Discharge to generate wall charges in the cell, and close to the end of application of the second reset pulse on the time axis to apply the third reset pulse having the opposite polarity to the second reset pulse to the other row electrode. Then, the discharge is generated between the row electrode pairs to reduce the wall charge amount generated by the previous discharge, so that the discharge between the row electrode pairs caused only by the wall charge of the cell is prevented and the scan pulse is applied. An appropriate amount of wall charge can remain in the cell until it is removed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a display device including a plasma display panel.

FIG. 2 is a diagram showing operation waveforms of a conventional plasma display panel driving device.

FIG. 3 is a configuration diagram showing an embodiment of a display device including a plasma display panel to which the present invention is applied.

FIG. 4 is an exploded perspective view of pixel cells forming a plasma display panel driven by the driving device of the present invention.

FIG. 5 is a diagram showing operation waveforms according to an embodiment of a driving device of the present invention.

6 (1) to (4) are time-series diagrams illustrating models of potentials and charge amounts of row electrode pairs and column electrodes driven by the driving device shown in FIG.

[Explanation of symbols for main parts]

Xi, Yi row electrodes Dj column electrodes 10a Row electrode drive pulse generation circuit as row electrode drive means 11 PDP

Claims (2)

[Claims] 1. A plurality of row electrode pairs, each pair extending in parallel to each other in the horizontal direction, and a pair of row electrode pairs extending in the vertical direction of the row electrode pair via a dielectric layer. A driving device for an AC discharge type matrix type plasma display panel, comprising: a plurality of column electrodes forming pixel cells near intersections; and a row electrode driving means for supplying a reset pulse and a scanning pulse to the row electrode pair, The row electrode driving means applies a first reset pulse having a predetermined polarity to one of the row electrodes of the row electrode pair, and has a polarity opposite to the predetermined polarity to the other row electrode and the first reset pulse of the first reset pulse. A second reset pulse having a potential whose potential difference from the potential exceeds the discharge start voltage between the pair of row electrodes is applied to generate a wall charge in each of the pixel cells, and then to the other row electrode. The rear edge of the second reset pulse has a front edge adjacent on the time axis and the second
A third reset pulse having a polarity opposite to that of the reset pulse and having a potential for generating a discharge between the row electrode pairs is applied to reduce the charge amount of each of the pixel cells, and then the row electrode pair is applied. An apparatus for driving an AC discharge type matrix type plasma display panel, characterized in that the scanning pulse is applied to the. 2. The driving device according to claim 1, wherein the third reset pulse has a voltage level smaller than a potential difference between the first and second reset pulses.