JPH08264962A - Manufacture of multilayer wiring board - Google Patents

Manufacture of multilayer wiring board

Info

Publication number
JPH08264962A
JPH08264962A JP11255896A JP11255896A JPH08264962A JP H08264962 A JPH08264962 A JP H08264962A JP 11255896 A JP11255896 A JP 11255896A JP 11255896 A JP11255896 A JP 11255896A JP H08264962 A JPH08264962 A JP H08264962A
Authority
JP
Japan
Prior art keywords
benzocyclobutene resin
resin
conductor wiring
wiring board
benzocyclobutene
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11255896A
Other languages
Japanese (ja)
Other versions
JP2917909B2 (en
Inventor
Naonori Orito
直典 下戸
Koji Matsui
孝二 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8112558A priority Critical patent/JP2917909B2/en
Publication of JPH08264962A publication Critical patent/JPH08264962A/en
Application granted granted Critical
Publication of JP2917909B2 publication Critical patent/JP2917909B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Abstract

PURPOSE: To solve problems which used to happen when a polyimide resin layer of high curing temperature is used as an interlayer insulating film, wherein a conductor wiring mainly formed of Cu low in wiring resistance is used. CONSTITUTION: A first process wherein a conductor wiring layer 12 whose main component is copper is formed on a board 11, and benzocyclobutene resin 13 is applied onto the conductor wiring layer 12, a second process wherein a pattern forming resin layer is formed on the benzocyclobutene resin 13, and a viahole is provided to the benzocyclobutene resin 13, and a third process wherein the benzocyclobutene resin 13 is heated and cured at a temperature of 200 deg.C or so are provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は集積度の高いLSI
実装用基板に関して、微細かつ高多層配線ができ、高密
度実装が可能な多層配線基板の製造方法に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated LSI.
The present invention relates to a method for manufacturing a multi-layer wiring board which enables fine and high multi-layer wiring and enables high-density mounting.

【0002】[0002]

【従来の技術】従来、この種の多層配線基板は、配線抵
抗の低いCuを主成分とする導体配線と、ポリイミド樹
脂からなる導体配線の層間絶縁体から構成されている。
2. Description of the Related Art Conventionally, a multilayer wiring board of this type is composed of a conductor wiring containing Cu having a low wiring resistance as a main component, and an interlayer insulator of the conductor wiring made of a polyimide resin.

【0003】図2に従来技術による多層配線基板の構成
図を示す。
FIG. 2 is a block diagram of a conventional multilayer wiring board.

【0004】基板21の表面に導体層22が設けられ
る。この導体層22はCr/Pd/Cu、あるいはCr
/Cu/Cr膜などの複数層構成を有している。そして
全表面に感光製を有したポリイミド樹脂層間絶縁膜23
をコーテイングし、光によりビアホール24が形成され
る。この上にさらに導体配線層25が形成される。
A conductor layer 22 is provided on the surface of the substrate 21. This conductor layer 22 is made of Cr / Pd / Cu or Cr.
It has a multi-layer structure such as / Cu / Cr film. The polyimide resin interlayer insulating film 23 having a photosensitive surface on all surfaces
And the via hole 24 is formed by light. A conductor wiring layer 25 is further formed thereon.

【0005】[0005]

【発明が解決しようとする課題】上述した従来の多層配
線基板は、層間絶縁体に用いているポリイミド樹脂の硬
化温度が高く、また硬化中において脱水反応があり、さ
らには硬化膜の吸水性が大きいので、配線抵抗の低いC
uを主成分とする導体配線を用いた場合、Cu配線の酸
化、腐食などを引き起こす欠点がある。
In the conventional multilayer wiring board described above, the curing temperature of the polyimide resin used for the interlayer insulator is high, a dehydration reaction occurs during the curing, and the water absorption of the cured film is high. Since it is large, C has low wiring resistance
The use of the conductor wiring containing u as a main component has a drawback of causing oxidation and corrosion of the Cu wiring.

【0006】さらには層間絶縁体にポリイミドを用いて
いるため、Cuイオンがポリイミド樹脂絶縁体中に拡散
してしまい。このためイオンのマイグレーションを引き
起こし、絶縁性が著しく低下するという欠点もある。
Further, since polyimide is used as the interlayer insulator, Cu ions diffuse into the polyimide resin insulator. For this reason, there is a drawback that the migration of ions is caused and the insulating property is significantly lowered.

【0007】このため層間絶縁体にポリイミド樹脂を用
いた従来の多層配線基板では、Cuを主成分とする導体
配線を用いるにあたり、長期信頼性に欠くという問題点
がある。
Therefore, in the conventional multilayer wiring board using the polyimide resin as the interlayer insulator, there is a problem that the long-term reliability is insufficient when using the conductor wiring containing Cu as a main component.

【0008】一方エレクトロニクス機器の高性能、高機
能化の要求に対し、高速伝送に対応した材料が必要とな
る。高速伝送では特性インピーダンスを整合させ、かつ
信号の伝播遅延時間の短縮が要求されている。信号伝播
遅延時間Tは
On the other hand, in response to the demand for high performance and high functionality of electronic equipment, materials compatible with high-speed transmission are required. In high-speed transmission, it is required to match the characteristic impedance and shorten the signal propagation delay time. The signal propagation delay time T is

【数1】 で示される(ただし、C:光速、ε:層間絶縁体の誘電
率、K:定数)。すなわち層間絶縁体の誘電率が低いほ
ど信号伝播遅延時間は短縮され、高速化が実現される。
[Equation 1] (Where C is the speed of light, ε is the dielectric constant of the interlayer insulator, and K is a constant). That is, the lower the dielectric constant of the interlayer insulator, the shorter the signal propagation delay time, and the higher the speed.

【0009】上述した従来の多層配線基板は、層間絶縁
体に用いているポリイミド樹脂の誘電率が3.5程度と
なっており、信号伝播遅延時間が長くなるという欠点が
ある。なお誘電率は、ASTMD150の測定法におい
て、106 Hzの周波数での値を用いる。
In the above-mentioned conventional multilayer wiring board, the dielectric constant of the polyimide resin used for the interlayer insulator is about 3.5, and there is a drawback that the signal propagation delay time becomes long. As the dielectric constant, a value at a frequency of 10 6 Hz is used in the measuring method of ASTM D150.

【0010】[0010]

【課題を解決するための手段】前述したように、配線抵
抗の低いCuを主成分とした導体配線を用いるにあた
り、ポリイミド樹脂を層間絶縁膜として用いた場合、諸
問題が発生している。これらの問題を解決するため鋭意
工夫を行なった。
As described above, various problems have occurred when a polyimide resin is used as an interlayer insulating film when using a conductor wiring mainly composed of Cu having a low wiring resistance. Intensive efforts were made to solve these problems.

【0011】その結果、配線抵抗の低いCuを主成分と
する導体配線とベンゾシクロブテン樹脂からなる層間絶
縁体を有する構成からなる多層配線基板が前述の問題点
を解決し、またこのような多層配線基板は、基板表面に
設けられたCuを主成分とする導体配線層上にベンゾシ
クロブテン樹脂を塗布する工程と、前記ベンゾシクロブ
テン樹脂上にパターン形成用の樹脂層を設けて前記ベン
ゾシクロブテン樹脂にビアホールを形成する工程と、前
記ベンゾシクロブテン樹脂を200℃程度の温度におい
て加熱硬化させる工程とから製造することが可能である
ことが見いだされた。
As a result, a multilayer wiring board having a structure having a conductor wiring containing Cu as a main component and having a low wiring resistance and an interlayer insulator made of benzocyclobutene resin solves the above-mentioned problems, and such a multilayer wiring board is formed. In the wiring board, a step of applying a benzocyclobutene resin on a conductor wiring layer containing Cu as a main component provided on a surface of the board, and a resin layer for forming a pattern on the benzocyclobutene resin are provided. It has been found that it is possible to manufacture from a step of forming a via hole in butene resin and a step of heating and curing the benzocyclobutene resin at a temperature of about 200 ° C.

【0012】このベンゾシクロブテン樹脂は200℃、
もしくはそれ以下で硬化させることができ、また硬化膜
は耐湿性にも優れている。このためCu導体配線層上
に、直接ベンゾシクロブテン樹脂を形成し、ベンゾシク
ロブテン樹脂層間絶縁体を構成することにより、Cu配
線の酸化、腐食を防ぐことができる。
This benzocyclobutene resin has a temperature of 200 ° C.
Alternatively, it can be cured at a lower temperature, and the cured film has excellent moisture resistance. Therefore, by forming the benzocyclobutene resin directly on the Cu conductor wiring layer to form the benzocyclobutene resin interlayer insulator, oxidation and corrosion of the Cu wiring can be prevented.

【0013】またはまず低温で膜が形成可能なベンゾシ
クロブテン樹脂で導体配線を介して、そのあとにポリイ
ミド樹脂絶縁体などを形成することにより導体配線の酸
化を防ぐことができる。またポリイミド樹脂絶縁体中へ
のCuイオン拡散を防ぎ、イオンのマイグレーションに
よる絶縁性の低下も防ぐことができる。
Alternatively, oxidation of the conductor wiring can be prevented by first forming a film of benzocyclobutene resin capable of forming a film at a low temperature through the conductor wiring and then forming a polyimide resin insulator or the like. Further, it is possible to prevent Cu ion diffusion into the polyimide resin insulator and prevent deterioration of insulation due to ion migration.

【0014】さらには硬化したベンゾシクロブテン樹脂
は耐湿性にも優れていることから、長期的な導体配線の
酸化、腐食を防ぐことができる。
Furthermore, since the cured benzocyclobutene resin has excellent moisture resistance, it is possible to prevent long-term oxidation and corrosion of the conductor wiring.

【0015】一方、ベンゾシクロブテン樹脂の誘電率は
2.6と従来のポリイミドよりも低く、これを層間絶縁
体として用いることにより、信号伝播遅延時間を短縮す
ることができる。
On the other hand, the dielectric constant of benzocyclobutene resin is 2.6, which is lower than that of conventional polyimide, and by using this as an interlayer insulator, the signal propagation delay time can be shortened.

【0016】[0016]

【発明の実施の形態】次に本発明について図面を参照し
て説明する。図1は層間絶縁体にベンゾシクロブテン樹
脂を有する本発明の一実施例の構成図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a constitutional view of an embodiment of the present invention having a benzocyclobutene resin as an interlayer insulator.

【0017】シリコン、サフアイア、あるいはアルミナ
などを主成分とするセラミツクなどからなる基板11の
表面に、Cuを主成分とする導体配線層12が設けられ
る。そして全表面にベンゾシクロブテン樹脂絶縁体13
をコーテイングしたのち、この表面にフオトレジストで
パターン形成させ、ベンゾシクロブテンをエツチングす
ることにより、ビアホール14を得ることができ、エツ
チングにはプラズマエツチャーを用いることができ、ガ
スはCF4 とO2 、あるいはSF6 とO2 混合ガスが適
当である。
A conductor wiring layer 12 containing Cu as a main component is provided on the surface of a substrate 11 made of ceramics containing silicon, sapphire, or alumina as a main component. And the benzocyclobutene resin insulator 13 on the entire surface
After coating, a via hole 14 can be obtained by forming a pattern on this surface with a photoresist and etching benzocyclobutene, a plasma etcher can be used for etching, and gases of CF 4 and O 2 can be used. 2 or a mixed gas of SF 6 and O 2 is suitable.

【0018】ビアホール形成後、ベンゾシクロブテン樹
脂絶縁体13を200℃で硬化した後、導体配線層15
は、全表面にCuスパツタ膜を形成しエツチングして得
るか、あるいは全表面にCrスパツタ膜を形成したの
ち、Cuスパツタ膜あるいはめっきCu箔を形成するこ
とにより得ることができる。
After forming the via hole, the benzocyclobutene resin insulator 13 is cured at 200 ° C., and then the conductor wiring layer 15 is formed.
Can be obtained by forming a Cu sputter film on the entire surface and etching, or by forming a Cr sputter film on the entire surface and then forming a Cu sputter film or a plated Cu foil.

【0019】[0019]

【発明の効果】以上説明したように、本発明の多層配線
基板の製造方法は、導体配線の層間絶縁体にベンゾシク
ロブテン樹脂を有する多層配線基板を、ベンゾシクロブ
テン樹脂を200℃で硬化させることによって、従来よ
り低温のプロセスで多層配線基板を製造することができ
る。又この方法によって得られた多層配線基板は、Cu
導体配線の酸化、腐食を防ぎ、またCuイオンのマイグ
レーションによる絶縁性の低下を防ぐことができる効果
がある。
As described above, according to the method of manufacturing a multilayer wiring board of the present invention, the multilayer wiring board having the benzocyclobutene resin as the interlayer insulator of the conductor wiring is cured at 200 ° C. with the benzocyclobutene resin. As a result, the multilayer wiring board can be manufactured by a process at a lower temperature than in the past. The multilayer wiring board obtained by this method is Cu
There is an effect that the conductor wiring can be prevented from being oxidized and corroded, and the insulation property can be prevented from being deteriorated due to migration of Cu ions.

【0020】これにより配線抵抗の低いCuを主成分と
する導体配線を有した微細かつ高多層配線を形成するこ
とができ、高密度実装が可能な多層配線基板を提供する
ことができる。
As a result, it is possible to form a fine and multi-layered wiring having a conductor wiring mainly composed of Cu having a low wiring resistance, and it is possible to provide a multi-layered wiring board capable of high-density mounting.

【0021】またベンゾシクロブテン樹脂は誘電率が
2.6と低く、これを層間絶縁体として用いることによ
り、信号伝播遅延時間が短縮されるという効果もある。
The benzocyclobutene resin has a low dielectric constant of 2.6, and the use of this as an interlayer insulator also has the effect of shortening the signal propagation delay time.

【図面の簡単な説明】[Brief description of drawings]

【図1】層間絶縁体にベンゾシクロブテン樹脂を用いる
本発明によって製造される一実施例の構成図である。
FIG. 1 is a constitutional view of an embodiment produced by the present invention using a benzocyclobutene resin as an interlayer insulator.

【図2】従来技術による多層配線基板の構成図である。FIG. 2 is a configuration diagram of a multilayer wiring board according to a conventional technique.

【符号の説明】[Explanation of symbols]

11,21 基板 12,15,22,25 導体配線層 13 ベンゾシクロブテン樹脂絶縁体 14,24 ビアホール 23 ポリイミド樹脂絶縁体 11, 21 Substrate 12, 15, 22, 25 Conductor wiring layer 13 Benzocyclobutene resin insulator 14, 24 Via hole 23 Polyimide resin insulator

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】Cuを主成分とする導体配線を有し、ベン
ゾシクロブテン樹脂を導体配線の層間絶縁体に用いるこ
とを特徴とする多層配線基板の製造方法であって、基板
表面に設けられたCuを主成分とする導体配線層上にベ
ンゾシクロブテン樹脂を塗布する工程と、前記ベンゾシ
クロブテン樹脂上にパターン形成用の樹脂層を設けて前
記ベンゾシクロブテン樹脂にビアホールを形成する工程
と、前記ベンゾシクロブテン樹脂を200℃程度の温度
において加熱硬化させる工程とを有することを特徴とす
る多層配線基板の製造方法。
1. A method for manufacturing a multilayer wiring board, comprising a conductor wiring containing Cu as a main component, and using benzocyclobutene resin as an interlayer insulator of the conductor wiring, the method being provided on a substrate surface. A step of applying a benzocyclobutene resin on a conductor wiring layer containing Cu as a main component, and a step of providing a resin layer for pattern formation on the benzocyclobutene resin and forming a via hole in the benzocyclobutene resin. And a step of heating and curing the benzocyclobutene resin at a temperature of about 200 ° C., the method for manufacturing a multilayer wiring board.
JP8112558A 1996-05-07 1996-05-07 Method for manufacturing multilayer wiring board Expired - Fee Related JP2917909B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8112558A JP2917909B2 (en) 1996-05-07 1996-05-07 Method for manufacturing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8112558A JP2917909B2 (en) 1996-05-07 1996-05-07 Method for manufacturing multilayer wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP29602590A Division JPH0719973B2 (en) 1990-10-31 1990-10-31 Multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH08264962A true JPH08264962A (en) 1996-10-11
JP2917909B2 JP2917909B2 (en) 1999-07-12

Family

ID=14589685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8112558A Expired - Fee Related JP2917909B2 (en) 1996-05-07 1996-05-07 Method for manufacturing multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2917909B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016640A (en) * 2006-07-06 2008-01-24 Consortium For Advanced Semiconductor Materials & Related Technologies Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02257664A (en) * 1988-11-10 1990-10-18 Microelectron Center Of North Carolina Integrated circuit clip package and its formation method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02257664A (en) * 1988-11-10 1990-10-18 Microelectron Center Of North Carolina Integrated circuit clip package and its formation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016640A (en) * 2006-07-06 2008-01-24 Consortium For Advanced Semiconductor Materials & Related Technologies Semiconductor device

Also Published As

Publication number Publication date
JP2917909B2 (en) 1999-07-12

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