JPH08264641A - Dielectric isolation substrate and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a dielectric isolation substrate in which no void or no autodoping occurs and which has excellent insulator isolation. CONSTITUTION: A high purity silicon layer 13, a low-melting point silicon oxide layer 14 and a glass layer 16 obtained by sootlike substance containing SiO2 as a main ingredient by burning a raw material containing silicon compound as a main ingredient in an oxy-hydrogen flame are sequentially deposited on a semiconductor substrate in which isolating grooves are formed. Further, a support board 15 for holding the substrate is placed on the layer 16, heat treated, the substance is sintered to be transferred to the layer 16 to connect the substrate to the board 15. Then, when the other surface of the substrate is polished and cleaned, a dielectric isolation substrate in which the insulator isolation of high quality is provided and which has a plurality of insular semiconductor layers 11 is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method of manufacturing the same, and more particularly to a substrate and a dielectric isolation technique relating to a dielectric isolation method suitable for manufacturing a highly functional or high performance semiconductor device.

[0002]

2. Description of the Related Art Dielectric isolation technology, which is known as a method for isolating semiconductor single crystal regions from each other, has a very good insulation isolation between devices as compared with standard junction isolation technology, and limits the application circuit. It is suitable for high-voltage and high-current power ICs because it has a small amount. EPIC (Epitaxial Passivated Integrated Circuit) is a typical dielectric isolation method.
Although the cuit) method is known, various other methods have been studied due to problems with large-diameter wafers and manufacturing costs. One of them is SOI (Silicon On Insulator) technology for manufacturing a substrate by bonding a plurality of semiconductor substrates together. As a method for bonding substrates, for example, Japanese Patent Laid-Open No.
There are methods disclosed in JP-A-1-242033 and JP-A-62-177938.

[0003]

As shown in FIG. 1, a conventional substrate manufactured by this kind of bonding method is usually an island-shaped semiconductor layer 11 covered with an insulating film 12 such as SiO _2. Are adhered to the support substrate 15 by the glass layer 13. According to this manufacturing method, a large-diameter wafer with less warpage can be obtained at a relatively low cost, but there are still problems. In particular, depending on the manufacturing conditions and the thickness of each layer, voids (holes) may be generated in the groove, which may cause peeling or chipping (chips) of the substrate in the device manufacturing process and reduce the yield. Become.

Further, in such a structure, since the glass layer is exposed on the surface of the finally obtained dielectric isolation substrate,
Impurities such as boron and phosphorus contained in the glass layer diffuse into the surroundings during the subsequent device process and contaminate the furnace.
A phenomenon (autodoping) in which impurities diffuse from the surface of the element portion to a semiconductor layer for element formation is likely to occur, and predetermined electrical characteristics may not be obtained, which may cause a problem when forming a special element.

Further, in Japanese Patent Publication No. 58-45182, a polysilicon layer is provided between the insulating film and the glass layer, which has an effect of preventing impurities from the glass layer from diffusing into the island-shaped semiconductor layer. There is a description of the dielectric isolation substrate. In this substrate, although the diffusion into the island-shaped semiconductor layer, which is the element formation region, is small, impurities are diffused into the polysilicon to lower the resistance value. Insulation separation may deteriorate. Also,
In particular, impurities exist in the grain boundaries of polysilicon, but it is difficult to remove them even by cleaning, and if polysilicon is exposed on the surface of the element part, the same phenomenon as the above-mentioned autodoping occurs and there is a problem. is there.

It is an object of the present invention to solve the above-mentioned drawbacks of the conventional dielectric isolation substrate, and to provide a substrate which is free from voids and does not undergo autodoping and has good insulation and isolation.

[0007]

The present invention provides a dielectric isolation substrate in which a plurality of island-shaped semiconductor layers separated from each other and a supporting substrate supporting the island-shaped semiconductor layers are bonded by a glass layer. A dielectric isolation substrate, characterized in that a high-purity silicon oxide layer and a low-melting-point silicon oxide layer are interposed between the layer and the glass layer.

In the present invention, it is particularly preferable that, of the above-mentioned silicon oxide layers, the low-melting-point silicon oxide layer is not exposed on the element formation surface.

Furthermore, the present invention is also a method for manufacturing a dielectric isolation substrate, which comprises a step of forming a high-purity silicon oxide layer on the surface of a semiconductor substrate having a groove for isolation on one surface, SiO obtained by a step of forming a low melting point silicon oxide layer on the surface of a pure silicon oxide layer and burning a raw material containing a silicon compound as a main component on the surface of the low melting point silicon oxide layer in an oxyhydrogen flame. A step of depositing a soot-like substance containing ₂ as a main component, and another holding substrate to be bonded is placed on the deposition of the soot-like substance, and heat treatment is performed,
Sintering the soot-like substance deposit to bond the semiconductor substrate and the supporting substrate, and polishing the other surface of the semiconductor substrate to form a plurality of island-shaped semiconductor layers. It has a feature.

In the present invention, it is particularly preferable that after the low-melting-point silicon oxide layer is formed, heat treatment is performed to flatten the surface of the low-melting-point silicon oxide layer, and then the soot-like substance is deposited. Here, the flatness of the surface does not have to be perfectly flat, and may be such that the low-melting-point silicon oxide layer melts and flows.

The high-purity silicon oxide layer of the present invention is formed by a CVD method (chemical vapor deposition method) by a thermochemical reaction between an organic silicon compound and ozone, has very few impurities, and is an electrically insulating material. It is a layer having characteristics similar to quartz. When forming a high-purity silicon oxide layer, for example, when a mixed gas of an organosilicon compound such as tetraethoxysilane and ozone is supplied into a reaction tube, the surface of the silicon substrate held in the reaction tube and heated to 300 ° C. to 600 ° C. The reaction occurs at the temperature and silicon oxide is generated. This silicon oxide is piled up to form a high-purity silicon oxide layer. The thickness of this layer is usually 1 to 20 μm, and is set to such a thickness that the glass layer and the low melting point silicon layer are not exposed at the dielectric separation portion of the element formation surface when the dielectric separation is performed by grinding and polishing later. Is preferred.

On the other hand, the low melting point silicon oxide layer is formed by a CVD method (chemical vapor deposition method) by a thermochemical reaction between an organic silicon compound and ozone, like the high purity silicon oxide layer. Impurities such as phosphorus, boron, arsenic, antimony, and germanium are 0.5 with respect to SiO ₂ .
~ 30% (mol%), preferably 3-20% (mol
%) Is included. Since the melting point is lowered by containing such impurities, the surface can be easily flattened by heat treatment after the deposition. The formation of the low-melting-point silicon oxide layer is performed by forming a compound such as phosphorus oxychloride, boron trichloride, borane (BH ₃ , B ₂ H ₆ ), arsine, etc. It is carried out by forming a silicon oxide containing impurities on the surface of the substrate by supplying the same into the reaction tube together with the organic silicon compound and ozone and reacting in the same manner. The thickness of this layer is usually 1 to 60 μm.
Therefore, when the surface is flattened by heat treatment later, it is necessary to fill the groove when melted so that the surface is approximately flattened.

[0013]

In the present invention, the high-purity silicon oxide layer is deposited on the surface of the semiconductor substrate in which the groove is formed, and further the low melting point silicon oxide layer is deposited. Here, the high-purity silicon oxide layer is completely and completely filled up to the tip of the groove. If such a high-purity silicon oxide layer or low-melting-point silicon is not provided, a void is likely to occur at the tip of the groove, but the high-purity silicon oxide layer causes voids to occur at this tip even in the subsequent process. Never.

In the present invention, the high purity silicon oxide layer is exposed at the dielectric isolation portion for isolating each island-shaped semiconductor layer on the element formation surface, and the glass layer and the low melting point silicon oxide layer are not exposed. In the above, impurities such as boron and phosphorus do not diffuse from the surface into the process atmosphere. That is, it is possible to effectively prevent the furnace from being contaminated during the device process and autodoping.

Further, in the present invention, when the low melting point silicon oxide layer is formed and then heat-treated to flatten the surface, the bonding with the glass layer is performed on a substantially flat surface. The generation of voids can be further suppressed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings.

One embodiment of the present invention has the structure shown in FIG. 2 and is manufactured as follows. First, FIG.
As shown in (a), a groove for separation is formed on the surface of the silicon substrate. This silicon substrate 10 is, for example, N-type, has a resistivity of 10 to 30 Ω · cm, and has a plane orientation <100> plane 4
It is a silicon substrate having an inch diameter and a thickness of 525 μm. The V groove is formed by forming a thermal oxide film and then photoetching it to form a mask pattern, and the region where Si is exposed is 90 parts by weight of a 20% aqueous solution of KOH, 5 parts by weight of isopropyl alcohol and n-. It can be produced by etching with a so-called anisotropic etching solution containing 5 parts by weight of butyl alcohol at a temperature of 80 ° C. The groove depth is about 28 μm and the groove width is about 40 μm. After that, the process of depositing the next high-purity silicon oxide layer may be performed, but in order to ensure the insulation isolation, in the present invention, subsequently, the substrate in which the groove is formed is thermally oxidized to form the V groove. It is particularly preferable to form a SiO ₂ film (thermal oxide film) as the insulating film 12 on the surface of the substrate with a thickness of about 0.5 to 2.0 μm.

Next, as shown in FIG. 3B, a high-purity silicon oxide layer 13 is formed by a CVD method by a thermochemical reaction between tetraethoxysilane and ozone. This layer has a thickness of about 8 μm.

Next, as shown in FIG. 3C, a low melting point silicon oxide layer 14 is formed. This layer is formed by using tetraethoxysilane, about 10 mol% of boron trichloride or diborane (B ₂ H ₆ ) based on tetraethoxysilane,
And ozone by using a CVD method by thermochemical reaction. That is, the low melting point silicon oxide layer is composed of silicon oxide doped with boron as an impurity. At this time, as the amount of boron increases, the melting point of this silicon layer decreases, so the amount of boron is adjusted appropriately according to the manufacturing process. Further, this low melting point silicon oxide film is 20
It is about μm.

Next, when this substrate is heat-treated at 850 ° C., the low melting point silicon layer is melted and flattened, as shown in FIG. 3D. The heat treatment temperature can be appropriately selected according to the amount of boron added.

Next, as shown in FIG. 4, SiO ₂ obtained by burning a raw material containing a silicon compound as a main component in an oxyhydrogen flame on the surface of the flattened low melting point silicon oxide layer 14 as the main component. To deposit soot-like substances. Specifically, for example, gaseous SiCl ₄ (supply amount 210 ml /
min) and gaseous BCl ₃ (supply rate 105 ml / m
in) to hydrogen (0.85 l / min) and oxygen (5 l / min)
(min) of a soot-like substance obtained by decomposing and supplying it into a combustion flame (oxyhydrogen flame) having a thickness of 100 μm on the surface of the semiconductor substrate having the V groove. Then, a silicon substrate 15, which is a separately prepared support substrate, is superposed on the deposition of soot-like substances and heated to 1280 ° C. in an oxygen atmosphere in a heating furnace, and the soot-like substances are sintered. Then, the glass layer 16 was uniformly vitrified at the same time when the volume contracted to a thickness of 10 μm, and the two silicon substrates were evenly bonded to each other (FIG. 4A).

Finally, as shown in FIG. 4 (b), the semiconductor substrate is polished from the back surface until the grooves are exposed, and a plurality of island-shaped semiconductors are isolated as islands as element formation regions. Obtain the layer 11. That is, a dielectric isolation substrate having a high-purity silicon oxide layer and a low-melting point silicon oxide layer interposed between the island-shaped semiconductor layer and the glass layer can be obtained. In particular,
In this case, the plurality of island-shaped semiconductor layers and the high-purity silicon oxide layer are exposed on the element formation surface, but the low melting point silicon oxide layer is not exposed on the element formation surface.

Table 1 shows the amount of warpage of this dielectric isolation substrate and the occurrence of voids. As described above, the substrate according to the present invention has a small amount of warp, and no void is observed. The amount of warpage is ASTM (F65
7-80), and the presence or absence of voids is checked with an ultrasonic image exploration apparatus (UH Pulse 200 manufactured by Olympus Co.) before polishing, and the surface is observed with an optical microscope after polishing. Examined. In addition, the impurity concentration of the separation portion 20 on the surface of the substrate, that is, the portion of the surface of the high-purity silicon oxide layer in this case was measured.
It turned out to be low. Furthermore, this substrate is
When heat-treated at 100 ° C. for 40 hours, as shown in Table 3, both before and after the heat-treatment, the resistivity was infinite and the performance as a separation region was high.

Comparative Example 1 The same conventional dielectric isolation substrate as shown in FIG. 1 was prepared in the same manner as in Example 1 except that the high purity silicon oxide layer and the low melting point silicon oxide layer were not deposited. It was made.

{Comparative Example 2} In Example, instead of the step of depositing a high-purity silicon oxide layer on a grooved substrate, further depositing a low melting point silicon oxide layer, and then performing heat treatment to planarize the same, After depositing a polysilicon layer of 35 μm on the substrate, the polysilicon layer was ground and planarized until the polysilicon layer became 5 μm.
A conventional dielectric isolation substrate was prepared.

The evaluation results of Comparative Example 1 and Comparative Example 2 are shown in Tables 1 to 3 together with the examples.

[0027]

[Table 1]

[0028]

[Table 2]

[0029]

[Table 3]

[0030]

According to the present invention, since the isolation portion of each island-shaped semiconductor layer is filled with the high-purity silicon oxide layer and the low-melting-point silicon oxide layer, no void is generated. Therefore, the dielectric isolation substrate can be manufactured with good yield without causing chipping or cracking during grinding / polishing. Further, when a step of heat-treating the low-melting-point silicon oxide layer to flatten it is added, there is a feature that no void is generated even if the glass layer is thinned.

Further, when only the high-purity silicon oxide layer is exposed at the surface separation portion, there is no impurity contamination from the substrate during the device process. Further, since the isolation portion on the surface is an insulator and the resistance value does not change even by the heat treatment of the device process, the performance as a dielectric isolation element is high. Further, since there is no grain boundary in the separation portion, impurities can be removed very easily by cleaning during the device process.

[Brief description of drawings]

FIG. 1 is a diagram showing a dielectric isolation substrate manufactured by a conventional dielectric isolation technique.

FIG. 2 illustrates one embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the present invention.

FIG. 4 is a diagram showing a manufacturing process of the present invention.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 11 island-shaped semiconductor layer 12 insulating film (thermal oxide film of silicon) 13 high-purity silicon oxide layer 14 low-melting-point silicon oxide layer 15 supporting substrate 16 glass layer

Claims (4)

[Claims] 1. A dielectric isolation substrate in which a plurality of island-shaped semiconductor layers separated from each other and a support substrate supporting the island-shaped semiconductor layers are adhered by a glass layer, and the island-shaped semiconductor layer and the glass layer are interposed between the island-shaped semiconductor layers and the glass layer. A dielectric isolation substrate, characterized in that a high-purity silicon oxide layer and a low-melting-point silicon oxide layer are interposed. 2. A plurality of island-shaped semiconductor layers and the high-purity silicon oxide layer are exposed on the element formation surface, and the low melting point silicon oxide layer is not exposed on the element formation surface. Item 2. The dielectric isolation substrate according to Item 1. 3. A step of forming a high-purity silicon oxide layer on the surface of a semiconductor substrate having a separation groove on one surface, and a low-melting-point silicon oxide layer formed on the surface of the high-purity silicon oxide layer. And a step of depositing a soot-like substance containing SiO ₂ as a main component, which is obtained by burning a raw material containing a silicon compound as a main component in an oxyhydrogen flame, on the surface of the low-melting-point silicon oxide layer. A step of placing another supporting substrate to be bonded on the deposition of the soot-like substance, performing heat treatment, and sintering the deposit of the soot-like substance to bond the semiconductor substrate and the supporting substrate. And a step of polishing the other surface of the semiconductor substrate to form a plurality of island-shaped semiconductor layers, the method for manufacturing a dielectric isolation substrate. 4. A step of forming a high-purity silicon oxide layer on the surface of a semiconductor substrate having a separation groove on one surface, and a low-melting-point silicon oxide layer formed on the surface of the high-purity silicon oxide layer. And a step of flattening the low melting point silicon oxide layer by heat treatment, and burning the raw material containing a silicon compound as a main component in an oxyhydrogen flame on the surface of the flattened low melting point silicon oxide layer. A step of depositing a soot-like substance containing SiO ₂ as a main component obtained by the above, and another supporting substrate to be bonded is placed on the deposit of the soot-like substance, and the soot-like substance is heat-treated. And a step of bonding the semiconductor substrate and the supporting substrate by sintering a deposit of a particulate material, and a step of polishing the other surface of the semiconductor substrate to form a plurality of island-shaped semiconductor layers. Method for manufacturing a dielectric isolation substrate.