JPH08264611A - Silicon wafer, manufacture of silicon single crystal to obtain wafer and evaluating method therefor - Google Patents

Abstract

PURPOSE: To manufacture a high integrated circuit having high integration degree in high yield by using a silicon wafer having the specific ratio of signal intensity due to the crystal defect in the wafer cleaned after a rear surface is mirror processed to the crystal defect volume density. CONSTITUTION: A silicon single crystal 8 picked up by a Czochralski method is subjected to a slicing, lapping and etching and mirror processing to manufacture a silicon wafer. After the rear surface of the wafer is mirror processed, it is cleaned, and the crystal defect in the wafer is measured by a crystal defect evaluating apparatus. Then, the silicon wafer in which the signal intensity due to the crystal defect and the volume density distribution of the crystal defect satisfy (the defect density of signal intensity of 4V or more)/(the defect density of signal intensity of 2V or more) >0.2 is obtained. Thus, the device having high integration degree can be manufactured with high yield.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon wafer used for manufacturing a semiconductor integrated circuit, and particularly to a highly integrated 1M wafer.
The present invention relates to the above integrated circuit wafer, a method for manufacturing a silicon single crystal for obtaining the wafer, and an evaluation method thereof.

[0002]

2. Description of the Related Art A silicon single crystal manufactured by the Czochralski method (hereinafter referred to as the CZ method) is used as a well-known crystal defect evaluation apparatus Optical Precipitates Profiler (hereinafter referred to as OPP).
Is described). The size, quality, and density of crystal defects existing inside the silicon single crystal can be known by measuring with. That is, the OPP is a measuring device characterized by using two synchronized infrared laser beams, and two laser beams arranged with a feeling of about 1 mm are incident from the wafer surface and transmitted through the wafer by a counter detector. Receive light rays.

Further, two laser beams are scanned within the wafer surface. When one of the laser beams hits a crystal defect, it is possible to obtain information about the size and quality of the defect as an in-plane distribution of the wafer by converting the phase difference between the laser beam not hitting the crystal defect and the other laser beam into signal intensity. it can. Further, the volume density of crystal defects can be obtained from the scanning range of the laser beam, the spread of the laser beam in the depth direction, and the number of crystal defects detected within the area scanned by the laser.

As a well-known crystal defect evaluation method using an infrared laser, an infrared scattering tomograph method is described in JP-A-6-112292. However, the infrared scattering tomography method is characterized by using one infrared laser, and is a method of detecting scattered light of laser light due to crystal defects by a detector installed at an angle of 90 degrees with respect to the incident direction. OPP using transmitted light of infrared laser
In principle, it is very different. Therefore, the crystal defects detected by the OPP and the crystal defects detected by the infrared scattering tomography are different.

The presence of crystal defects detected by OPP inside the silicon wafer has a detrimental effect on the device. Therefore, in order to manufacture a device with high yield, a wafer with few crystal defects detected by OPP is required. Moreover, such a crystal manufacturing method is required. However, such technology did not exist.

[0006]

Therefore, the present invention provides a high-quality silicon wafer having a high manufacturing yield and excellent electrical performance when used in an integrated circuit having a high degree of integration, and a high-quality silicon wafer It is an object of the present invention to provide a method for producing a silicon single crystal for obtaining it, and a method for evaluating the same.

[0007]

The present invention for achieving the above object provides a silicon wafer produced by slicing, lapping, etching and mirror-finishing a silicon single crystal pulled by the Czochralski method. When the back surface of the silicon wafer is mirror-finished and washed, and the crystal defects existing inside the silicon wafer are measured by a crystal defect evaluation apparatus, the signal intensity and the crystal defect volume density due to the crystal defects are (signal intensity is 4 V The above defect density) / (signal intensity is 2V
It is a silicon wafer characterized by satisfying the above defect density)> 0.2.

Further, the present invention for achieving the above object provides a method of pulling a silicon single crystal by the Czochralski method, wherein a cooling rate between 1200 ° C. and 1000 ° C. in a cooling process after solidification of the single crystal is performed. 2.0 ° C /
Or less, and the minimum value of the cooling rate is 1.0 ° C /
It is a method for producing a silicon single crystal, which is characterized by setting the amount to be equal to or less than a minute.

Further, the method for producing a silicon single crystal of the present invention is characterized in that, in the cooling process, the cooling rate between 1000 ° C. and 800 ° C. is set to 0.6 ° C./min or more.

Further, according to the present invention for achieving the above object, a wafer is cut out to a predetermined thickness from a silicon single crystal pulled by the Czochralski method, and lapping, etching and mirror finishing are performed to obtain a silicon wafer. When the back surface of the silicon wafer was mirror-finished and then washed and the crystal defects existing inside the silicon wafer were measured by a crystal defect evaluation apparatus, the signal intensity and the crystal defect volume density due to the crystal defects were as follows: The above defect density) / (signal intensity is 2V
It is a method for evaluating a silicon single crystal characterized by evaluating the quality and electrical characteristics of a silicon wafer by calculating the ratio of the above defect density).

[0011]

The inventors of the present invention have carefully studied the relationship between the signal yield and volume density of crystal defects detected by OPP and the device yield. As a result, the highly integrated device yield exists in the OPP. It was found that there is a strong correlation between the crystal defects having a signal intensity of 4 V or more and the volume density ratio of the crystal defects having a signal intensity of 2 V or more.

Hereinafter, the function of the present invention will be described in detail with respect to the breakdown voltage of the gate oxide film and the pn junction leak, which are important for the device yield, and the relation between the crystal defects detected by OPP.

First, the gate oxide film is obtained by oxidizing a silicon wafer in an oxidizing atmosphere at about 1000 ° C. to form SiO _2, and if a crystal defect exists in the silicon wafer, it is an inclusion of the gate oxide film. That is, it is known that it becomes a weak spot and deteriorates the withstand voltage. However, with the recent increase in device integration, the gate oxide film thickness during device formation on a silicon wafer is becoming thinner.
The thickness of about m, but the recent 4M, 16MDR
AM is about 10 to several nm.

Along with this, with respect to crystal defects that deteriorate the withstand voltage of the gate oxide film, those having a smaller size than before have come to be regarded as a problem. Specifically, when the gate oxide film thickness is 20 nm, a crystal defect having a size of about 12 nm is allowed, but when the gate oxide film thickness is 10 nm, only a size of about 5 nm is allowed. It was If a defect having a size larger than this is present in the oxide film, a defective switching operation is caused and the device yield is reduced.

Next, regarding the pn junction leakage,
As the device becomes highly integrated, the area of the capacitor per memory decreases and the absolute value of the capacity decreases.
Also, due to the need for low power consumption of devices, it is necessary to lengthen the time of refresh operation (timely injecting memory in order to keep the memory), and therefore, it has become necessary to prevent even a small leak current. However, if there is a deep level (generation / recombination center of an electron-hole pair) due to the depletion layer at the pn junction interface, a leak current will flow, though little by little, and the charge will be leaked.

In order to prevent pn junction leakage, it has been conventionally performed to improve cleanliness and prevent metal contamination, but in the future, crystal defects of silicon wafers will be reduced as much as possible to prevent leakage. It is required to reduce the cause.

From the above two viewpoints, when pulling a silicon single crystal under various conditions and examining the crystal defects which can be detected by OPP, depending on the pulling condition of the single crystal, the signal intensity of OPP and the volume density of crystal defects are increased. It has been found that there are various distributions. Furthermore, when the relationship between the device yield and the device yield is investigated using the silicon wafers made from these silicon single crystals, defects having a relatively high OPP signal intensity have a small adverse effect on the device yield and defects having a relatively low signal intensity are found. It was found that the device yield was greatly affected.

The formation mechanism of defects detected by OPP, their properties, and the influence on the device yield can be explained as follows.

That is, the interstitial silicon and the vacancies introduced at the solidification interface become supersaturated in the subsequent cooling process, alternately react and aggregate, and form a complex with oxygen which is also supersaturated. These defects are detected by the OPP, and the signal strength of the OPP depends on the size and morphology of these defects. According to the experiments conducted by the present inventors, a defect having a relatively high signal intensity when measured by OPP (a defect having a signal intensity of 4 V or higher) is easily erased by heat treatment.

From this, the oxide film forming step at about 900 ° C. to 1000 ° C. in the device process,
It disappears relatively easily in the well diffusion process at about 00 to 1250 ° C., no inclusions remain in the oxide film, and p
No deep level of crystal defects is left in the depletion layer at the n-junction interface. Therefore, even if such a defect exists in the silicon single crystal or the silicon wafer before the device process, it disappears during the device process, so that there is no adverse effect and a high device yield results.

On the contrary, a defect having a relatively small OPP signal intensity (generally, a defect having a signal intensity of 4 V or less) is stable against heat treatment, and therefore 90 in the device process.
Oxide film formation process from 0 ℃ to 1000 ℃ or 1100 ℃
Since it is difficult to dissolve even in the well diffusion process from about 1250 ° C. to 1250 ° C., it leaves an inclusion in the oxide film or leaves a deep level due to crystal defects in the depletion layer at the pn junction interface. Therefore, when a silicon wafer containing a large number of such defects is used as a substrate and a device is formed on the substrate, an insulation failure due to an oxide film withstand voltage may occur, or a leak current may increase, resulting in many refresh failures. As a result, the device yield decreases.

On the other hand, the size of these defects can be controlled by the present inventors by controlling the cooling rate of the single crystal after solidification during pulling of the silicon single crystal within a predetermined range. Found out. For example, when the cooling rate from 1200 ° C. to 1000 ° C. in the cooling process after solidification is decreased, crystal defects having an OPP signal intensity of 4 V or more increase, and when the cooling rate from 1000 ° C. to 800 ° C. is increased, the OPP signal becomes 4 V. The following crystal defects are increased.

A preferred cooling rate range for obtaining the OPP signal intensity and density distribution of the present invention is that the cooling rate between 1200 ° C. and 1000 ° C. during the cooling process of the single crystal after solidification is 2.0 ° C. / It is to be within a range of minutes or less, and the minimum value of the cooling rate during this is 1.0 ° C./minute or less. Also,
As a more preferable range of the cooling rate, the cooling rate between 1200 ° C. and 1000 ° C. in the cooling process of the single crystal after solidification is within the range of 2.0 to 0.2 ° C./min, and The minimum value is 1.0 to 0.2 ° C / min or less, and the cooling rate between 1000 ° C and 800 ° C is 0.6 ° C / min or more.

It should be noted that in the cooling process of the single crystal after the solidification,
The lower limit of the cooling rate between 200 ° C and 1000 ° C is set to 0.2.
The reason for setting the temperature to ° C is that if the cooling rate is slower than this, it takes a long cooling time during the production of the silicon single crystal, which deteriorates the productivity and is not practical. Further, it is more preferably 0.4 ° C./min or more. Also, 100
The reason for defining the cooling rate between 0 ° C. and 800 ° C. is that crystal defects having an OPP signal intensity of 4 V or less are not increased as described above.

Since the signal intensity of OPP strongly depends on the number of surface particles of a silicon wafer to be measured and the state of the back surface of the wafer, when measuring OPP, a silicon single crystal is sliced, lapped, etched, and then mirror-polished. In addition to the general silicon wafer manufacturing process described above, it is indispensable to polish the back surface of the silicon wafer to a mirror surface and further remove surface particles by cleaning (for example, ammonia cleaning).

The thus prepared silicon wafer was measured by OPP, and the density of defects having a signal intensity of 4 V or more was calculated as follows:
A silicon wafer having a defect density of V or more)> 0.2 is a silicon wafer having excellent electrical performance.

Further, the ratio of the defect density of a silicon wafer obtained from a silicon single crystal is (the density of defects having a signal intensity of 4 V or more) / (the signal intensity is 2).
It is possible to easily evaluate the quality and electrical properties of the silicon single crystal by determining the defect density of V or more).

[0028]

【Example】

<Embodiment 1> FIG. 1 shows a pulling apparatus by the CZ method to which the present invention is applied. In the figure, a graphite crucible 3 is rotatably arranged in a chamber 2 having a gas inlet (not shown) and an exhaust port 1, and a quartz glass crucible 4 is fitted in the crucible 3. The graphite crucible 3 and the quartz glass crucible 4 had a size of 16 inches. On the other hand, above these crucibles, a pulling wire (not shown) for holding the seed crystal by the chuck 5 is arranged at the tip, and the heater 6 and the carbon fiber molded heat insulating material are arranged around the crucible. Material 7 is arranged. Further, in order to control the cooling rate of the silicon single crystal after solidification within a predetermined range, a downwardly expanding heat reflecting material 9 was attached in an arrangement surrounding the silicon single crystal 8 in the furnace.

The heat reflecting material 9 is made of a carbon fiber formed heat insulating material. After loading and melting 45 kg of polycrystalline silicon into the quartz glass crucible 4, a 6-inch size silicon single crystal was pulled at a pulling rate of 1.0 to 1.2 mm / min. The range could be controlled as shown in.

This silicon single crystal was sliced, chamfered, lapped and etched by a usual processing method and then surface-polished to prepare a silicon wafer. Furthermore, when the crystal defects existing inside the wafer were measured by OPP (manufactured by HYT), the results shown in Table 1 and Table 2 were obtained.

On top of that, a 200-layer gate electrode having a diameter of 5 mm and having an upper layer of aluminum and a lower layer of 200 was formed.
Individually, for each of these MOS diodes,
A DC voltage of a polarity in which majority carriers are injected from the substrate silicon is applied between the aluminum layer and the electrode on the back surface of the substrate silicon, and the voltage is stepwise converted into an electric field of 0.25 MV / cm at each step. 200 mse
The leak current when gradually increasing with the holding time of c was measured, and the value of the applied voltage when the leak current became 1 μA / cm ² was 6 MV / cm or less, 6 to 8 MV / c.
m, 8 MV / cm or more, classified into three ranges, Table 2
It was shown to.

A 6-inch mirror-polished silicon wafer was prepared by the same method from the same silicon single crystal, and 200 dynamic RAMs having a design rule of 1.3 μm were formed on the mirror-polished silicon wafer. Time until next charge injection) 512 cycles /
When the bit failure was measured for 8 msec, the refresh main failure rate was as shown in Table 2.

<Embodiment 2> FIG. 2 shows a CZ to which the present invention is applied.
It is a pulling device by the law. In the figure, a graphite crucible 3 is rotatably arranged in a chamber 2 having a gas inlet (not shown) and an exhaust port 1, and a quartz glass crucible 4 is fitted into the crucible 3. The graphite crucible 3 and the quartz glass crucible 4 had an 18-inch size.

On the other hand, a pulling wire (not shown) for holding the seed crystal by the chuck 5 is arranged at the tip of the crucible above the crucible, and the heater 6 and the carbon fiber are provided around the crucible 3. A molded heat insulating material 7 is arranged. Further, in order to control the cooling rate of the silicon single crystal within a predetermined range after solidification, a crystal heating heater 10 having an inner diameter of 300 mm and a height of 100 mm is attached in such a manner as to surround the silicon single crystal 8 in the furnace, and is pulled up. Electric power of 7 kW was supplied over the entire period from the formation of the head to the formation of the tail.

After 55 kg of polycrystalline silicon was loaded and melted in the quartz glass crucible 4, an 8-inch size silicon single crystal was pulled at a pulling rate of 0.8 to 1.0 mm / min. Was controllable within the range shown in Table 1.

This silicon single crystal was sliced, chamfered, lapped and etched by a usual processing method, and then mirror-polished to prepare a silicon wafer. Further, the back surface of the wafer was mirror-polished and washed with an ammonia-based cleaning solution. The crystal defects existing inside the wafer are O
When measured with PP (manufactured by HYT), the results shown in Tables 1 and 2 were obtained.

An oxide film having a thickness of about 25 nm was formed on the 8-inch silicon wafer, and 368 two-layer gate electrodes each having an upper layer of aluminum and a lower layer of 5 mm in diameter were formed on the oxide film. For each of these MOS diodes, a DC voltage of the polarity in which majority carriers are injected from the substrate silicon is applied between the aluminum layer and the electrode on the back surface of the substrate silicon, and the voltage is stepwise converted into an electric field of 0. The leak current was measured at 25 MV / cm increments at each storage time of 200 msec, and the leak current was measured to be 1 μA /
The value of the applied voltage when it reaches cm ² is 6 MV / cm or less,
It is classified into three ranges of 6 to 8 MV / cm and 8 MV / cm or more, and shown in Table 2.

An 8-inch mirror-polished silicon wafer was prepared from the same silicon single crystal by the same method, and 368 dynamic RAMs with a design rule of 1.3 μm were formed on the mirror-polished silicon wafer, and a refresh time (certain charge injection) was performed. From the time until the next charge injection) was set to 512 cycles / 8 msec and the bit failure was measured, the refresh failure rate was as shown in Table 2.

<Embodiment 3> FIG. 3 shows C to which the present invention is applied.
It is a pulling device by the Z method. In the figure, a chamber 1 equipped with a gas inlet (not shown) and an outlet 1
A graphite crucible 3 is rotatably arranged in the glass crucible 1, and a quartz glass crucible 4 is fitted in the crucible 3. The graphite crucible 3 and the quartz glass crucible 4 had an 18-inch size. On the other hand, above these crucibles, a pulling wire (not shown) for holding the seed crystal by the chuck 5 is arranged at the tip, and the heater 6 and the carbon fiber molded heat insulating material 7 are arranged around the crucible. Are arranged.

Further, in order to control the cooling rate of the silicon single crystal within a predetermined range after solidification, the silicon single crystal 8 in the furnace is arranged so as to surround the inner diameter of 260 nm and the height of 100 m.
A crystal heating heater 10 having a size of m was attached, and 15 kW of electric power was supplied over the entire period from the head formation to the tail formation. Further, the water cooling chamber 11 of this pulling device is formed in a right angle, not in a dome shape, so that the crystal is cooled from directly above the crystal heating heater 10. After 50 kg of polycrystalline silicon was loaded and melted in the quartz glass crucible 4, a 6-inch size polycrystalline silicon was pulled at a pulling rate of 0.9 to 1.1 mm / min. The range could be controlled as shown in.

This silicon polycrystal was sliced, chamfered, lapped and etched by a usual processing method, and then mirror-polished to prepare a silicon wafer. Further, the back surface of the wafer was mirror-polished and washed with an ammonia-based cleaning agent. The crystal defects existing inside the wafer are OPP
When measured by (manufactured by HYT), the results shown in Table 1 and Table 2 were obtained.

An oxide film having a thickness of about 25 nm was formed on the 6-inch size silicon wafer, and 200 two-layer gate electrodes each having an upper layer of aluminum and a lower layer of 5 mm in diameter were formed on the oxide film. For each of these MOS diodes, a DC voltage of the polarity in which majority carriers are injected from the substrate silicon is applied between the aluminum layer and the electrode on the back surface of the substrate silicon, and the voltage is converted into an electric field of 0.25 MV in steps. The leak current was measured in the case of gradually increasing each step for 200 msec in each step, and the leak current was 1 μA / c.
The value of the applied voltage at m ² is 6 MV / cm or less,
It is classified into three ranges of 6 to 8 MV / cm and 8 MV / cm or more, and shown in Table 2.

Further, an 8-inch size mirror-polished silicon wafer was manufactured from the same silicon single crystal by the same method, and 200 dynamic RAMs having a design rule of 1.3 μm were formed thereon, and a refresh time (certain charge injection) was performed. From the time until the next charge injection) was set to 512 cycles / 8 msec and the bit failure was measured, the refresh failure rate was as shown in Table 2.

<Embodiment 4> FIG. 4 shows C to which the present invention is applied.
It is a pulling device by the Z method. In the figure, a chamber 1 equipped with a gas inlet (not shown) and an outlet 1
A graphite crucible 3 is rotatably arranged in the glass crucible 1, and a quartz glass crucible 4 is fitted in the crucible 3. The graphite crucible 3 and the quartz glass crucible 4 were 22 inches in size. On the other hand, above these crucibles, a pull-up wire (not shown) for holding the seed crystal by the chuck 5 is arranged at the tip, and the crucible 3
Heater 6 and carbon fiber molded heat insulating material 7 around
Are arranged.

Further, in order to control the cooling rate of the silicon single crystal within a predetermined range after solidification, the silicon single crystal 8 in the furnace is arranged so as to surround the inner diameter of 280 nm and the height of 70 mm.
The crystal heating heater 10 of the size was attached, and the electric power of 15 kW was supplied over the entire period from the head formation to the tail formation. Further, the heat insulating material 12 is arranged so as to surround the heater so that the heat of the heater efficiently hits the silicon crystal 8. 10 in this quartz glass crucible 4
After loading and melting 0 kg of polycrystalline silicon, an 8-inch size silicon polycrystalline was pulled at a pulling rate of 0.7 to 0.9 mm / min, and the cooling rate was controlled within the range shown in Table 1. did it. This silicon polycrystal was sliced, chamfered, lapped and etched by a usual processing method, and then mirror-polished to prepare a silicon wafer. Further, the back surface of the wafer was mirror-polished and washed with an ammonia-based cleaning agent. The crystal defects existing inside this wafer were measured by OPP (manufactured by HYT).
The result is shown in.

An oxide film having a thickness of about 25 nm was formed on this 8-inch silicon wafer, and 368 two-layer gate electrodes each having an upper layer of aluminum and a lower layer of 5 mm in diameter were formed on the oxide film. For each of these MOS diodes, a DC voltage of the polarity in which majority carriers are injected from the substrate silicon is applied between the aluminum layer and the electrode on the back surface of the substrate silicon, and the voltage is converted into an electric field of 0.25 MV in steps. The leak current was measured in the case of gradually increasing each step for 200 msec in each step, and the leak current was 1 μA / c.
The value of the applied voltage at m ² is 6 MV / cm or less,
It is classified into three ranges of 6 to 8 MV / cm and 8 MV / cm or more, and shown in Table 2.

An 8-inch mirror-polished silicon wafer was prepared from the same silicon single crystal by the same method, and 368 dynamic RAMs with a design rule of 1.3 μm were formed on the mirror-polished silicon wafer, and a refresh time (charge injection) was performed. From the time until the next charge injection) was set to 512 cycles / 8 msec and the bit failure was measured, the refresh failure rate was as shown in Table 2.

<Embodiment 5> FIG. 5 shows C to which the present invention is applied.
It is a pulling device by the Z method. In the figure, a chamber 1 equipped with a gas inlet (not shown) and an outlet 1
A graphite crucible 3 is rotatably arranged in the glass crucible 1, and a quartz glass crucible 4 is fitted in the crucible 3. The crucible 3 made of graphite and the crucible 4 made of quartz glass had a size of 20 inches. On the other hand, above these crucibles, a pull-up wire (not shown) for holding the seed crystal by the chuck 5 is arranged at the tip, and the crucible 3
Heater 6 and carbon fiber molded heat insulating material 7 around
Are arranged.

Further, in order to control the cooling rate of the silicon single crystal after solidification within a predetermined range, the silicon single crystal 8 in the furnace is arranged so as to surround the inner diameter of 260 nm and the height of 100 m.
A crystal heating heater 10 having a size of m was attached, and 15 kW of electric power was supplied over the entire period from the head formation to the tail formation. Further, the heat insulating material 12 is arranged so as to surround the heater so that the heat of the heater efficiently hits the silicon crystal 8. Further, the water cooling chamber 11 of this pulling device is formed in a right angle, not in a dome shape, so that the crystal is cooled from directly above the crystal heating heater 10. After loading and melting 75 kg of polycrystalline silicon into the quartz glass crucible 4, a 6-inch size polycrystalline silicon was pulled at a pulling rate of 0.8 to 1.0 mm / min. The range could be controlled as shown in.

This silicon polycrystal was sliced, chamfered, lapped and etched by a usual processing method, and then mirror-polished to prepare a silicon wafer. Further, the back surface of the wafer was mirror-polished and washed with an ammonia-based cleaning agent. The crystal defects existing inside the wafer are OPP
When measured by (manufactured by HYT), the results shown in Table 1 and Table 2 were obtained.

Further, an oxide film having a thickness of about 25 nm was formed on the 6-inch size silicon wafer, and 200 two-layer gate electrodes having a diameter of 5 mm and having an upper layer of aluminum and a lower layer doped thereon were formed on the oxide film. For each of these MOS diodes, a DC voltage of the polarity in which majority carriers are injected from the substrate silicon is applied between the aluminum layer and the electrode on the back surface of the substrate silicon, and the voltage is converted into an electric field of 0.25 MV in steps. The leak current was measured in the case of gradually increasing each step for 200 msec in each step, and the leak current was 1 μA / c.
The value of the applied voltage at m ² is 6 MV / cm or less,
It is classified into three ranges of 6 to 8 MV / cm and 8 MV / cm or more, and shown in Table 2.

An 8-inch mirror-polished silicon wafer was prepared from the same silicon single crystal by the same method, and 200 dynamic RAMs with a design rule of 1.3 μm were formed on the mirror-polished silicon wafer, and a refresh time (charge injection) was performed. From the time until the next charge injection) was set to 512 cycles / 8 msec and the bit failure was measured, the refresh failure rate was as shown in Table 2.

<Comparative Example 1> FIG. 6 shows a pulling apparatus by the CZ method applied to this comparative example. In the figure, a graphite crucible 3 is rotatably arranged in a chamber 2 having a gas inlet (not shown) and an exhaust port 1.
A quartz glass crucible 4 is fitted in the crucible 3. The graphite crucible 3 and the quartz glass crucible 4 had a size of 16 inches. On the other hand, above these crucibles, a pull-up wire (not shown) for holding the seed crystal by the chuck 5 is arranged at the tip, and the crucible 3
Heater 6 and carbon fiber molded heat insulating material 7 around
Are arranged.

After loading and melting 45 kg of polycrystalline silicon into the quartz glass crucible 4, a 6-inch size polycrystalline silicon was pulled at a pulling rate of 0.8 to 1.3 mm / min. Was controllable within the range shown in Table 1.

This silicon polycrystal was sliced, chamfered, lapped and etched by a usual processing method, and then mirror-polished to prepare a silicon wafer. Further, the back surface of the wafer was mirror-polished and washed with an ammonia-based cleaning agent.
The crystal defects existing inside the wafer are converted into OPP (HY
The results were as shown in Tables 1 and 2 when measured by T.

An oxide film having a thickness of about 25 nm was formed on the 6-inch size silicon wafer, and 200 two-layer gate electrodes each having an upper layer of aluminum and a lower layer of 5 mm in diameter were formed on the oxide film. For each of these MOS diodes, a DC voltage of the polarity in which majority carriers are injected from the substrate silicon is applied between the aluminum layer and the electrode on the back surface of the substrate silicon, and the voltage is converted into an electric field of 0.25 MV in steps. The leak current was measured in the case of gradually increasing each step for 200 msec in each step, and the leak current was 1 μA / c.
The value of the applied voltage at m ² is 6 MV / cm or less,
It is classified into three ranges of 6 to 8 MV / cm and 8 MV / cm or more, and shown in Table 2.

Also, an 8-inch size mirror-polished silicon wafer was manufactured from the same silicon single crystal by the same method, and 200 dynamic RAMs with a design rule of 1.3 μm were formed on the mirror-polished silicon wafer, and a refresh time (certain charge injection) was performed. From the time until the next charge injection) was set to 512 cycles / 8 msec and the bit failure was measured, the refresh failure rate was as shown in Table 2.

<Comparative Example 2> FIG. 7 shows a pulling apparatus by the CZ method applied to this comparative example. In the figure, a graphite crucible 3 is rotatably arranged in a chamber 2 having a gas inlet (not shown) and an exhaust port 1.
A quartz glass crucible 4 is fitted in the crucible 3. The graphite crucible 3 and the quartz glass crucible 4 had an 18-inch size. On the other hand, above these crucibles, a pull-up wire (not shown) for holding the seed crystal by the chuck 5 is arranged at the tip, and the crucible 3
Heater 6 and carbon fiber molded heat insulating material 7 around
And a radiation screen 13 on the inverted cone that surrounds the crystal 8 is arranged upward from the solidification interface. After 50 kg of polycrystalline silicon was loaded and melted in the quartz glass crucible 4, a 6-inch size polycrystalline silicon was pulled at a pulling rate of 1.3 to 1.7 mm / min. The range could be controlled as shown in.

This silicon polycrystal was sliced, chamfered, lapped and etched by a usual processing method and then mirror-polished to prepare a silicon wafer. Further, the back surface of the wafer was mirror-polished and washed with an ammonia-based cleaning agent.
The crystal defects existing inside the wafer are converted into OPP (HY
The results were as shown in Tables 1 and 2 when measured by T.

Further, an oxide film having a thickness of about 25 nm was formed on this 6 inch size silicon wafer, and 200 two-layer gate electrodes each having an upper layer of aluminum and a lower layer of 5 mm in diameter were formed thereon, For each of these MOS diodes, a DC voltage of the polarity in which majority carriers are injected from the substrate silicon is applied between the aluminum layer and the electrode on the back surface of the substrate silicon, and the voltage is converted into an electric field of 0.25 MV in steps. The leak current was measured in the case of gradually increasing each step for 200 msec in each step, and the leak current was 1 μA / c.
The value of the applied voltage at m ² is 6 MV / cm or less,
It is classified into three ranges of 6 to 8 MV / cm and 8 MV / cm or more, and shown in Table 2.

Also, a 6-inch size mirror-polished silicon wafer was prepared from the same silicon single crystal by the same method, and 200 dynamic RAMs having a design rule of 1.3 μm were formed on the mirror-polished silicon wafer, and a refresh time (charge injection) was performed. From the time until the next charge injection) was set to 512 cycles / 8 msec and the bit failure was measured, the refresh failure rate was as shown in Table 2.

[0062]

[Table 1]

[0063]

[Table 2]

[0064]

Industrial Applicability The silicon wafer of the present invention is a silicon wafer having few harmful crystal defects causing an oxide film withstand voltage failure and a pn junction failure at the time of device formation, and can manufacture a highly integrated device with a high yield. It is suitable for.

Further, according to the crystal defect evaluation method of the present invention, a complicated heat treatment is not performed by using a commercially available OPP,
The electrical properties of a silicon wafer can be evaluated easily and simply, and nondestructively. Therefore, for example, when this method is used for quality control and shipping inspection of a silicon wafer at the silicon wafer manufacturing stage, the wafer manufacturing yield can be improved.

[Brief description of drawings]

FIG. 1 is a drawing showing a schematic configuration of a single crystal pulling apparatus used in Example 1 of the present invention.

FIG. 2 is a drawing showing a schematic configuration of a single crystal pulling apparatus used in Example 2 of the present invention.

FIG. 3 is a drawing showing a schematic configuration of a single crystal pulling apparatus used in Example 3 of the present invention.

FIG. 4 is a drawing showing a schematic configuration of a single crystal pulling apparatus used in Example 4 of the present invention.

FIG. 5 is a drawing showing a schematic configuration of a single crystal pulling apparatus used in Example 5 of the present invention.

FIG. 6 is a drawing showing a schematic configuration of a single crystal pulling apparatus used in Comparative Example 1 of the present invention.

FIG. 7 is a drawing showing a schematic configuration of a single crystal pulling apparatus used in Comparative Example 2 of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Exhaust port 2 ... Water cooling chamber (dome type) 3 ... Graphite crucible 4 ... Quartz glass crucible 5 ... Seed crystal chuck 6 ... Heating heater 7 ... Insulating material 8 ... Silicon single crystal 9 ... Heat reflecting material 10 ... Crystal heating Heater 11 ... Water cooling chamber (flat ceiling) 12 ... Insulating material 13 ... Radiant screen

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyo Haga 3434 Shimada, Hikari City, Yamaguchi Prefecture Shin Nippon Steel Co., Ltd.

Claims (4)

[Claims] 1. A silicon wafer produced by slicing, lapping, etching and mirror-finishing a silicon single crystal pulled up by the Czochralski method. The back surface of the silicon wafer is mirror-finished and then washed to evaluate crystal defects. When the crystal defect existing inside the silicon wafer is measured by the device, the signal intensity and the crystal defect volume density due to the crystal defect are (defect density of 4 V or more of signal intensity) / (signal intensity of 2 V
A silicon wafer having the above defect density)> 0.2. 2. A method for pulling a silicon single crystal by the Czochralski method, wherein the temperature is from 1200 ° C. to 100 during a cooling process after solidification of the single crystal.
A method for producing a silicon single crystal, wherein the cooling rate between 0 ° C. is 2.0 ° C./min or less, and the minimum value of the cooling rate is 1.0 ° C./min or less. 3. The method for producing a silicon wafer according to claim 2, wherein in the cooling process, a cooling rate between 1000 ° C. and 800 ° C. is set to 0.6 ° C./min or more. 4. A silicon single crystal pulled up by the Czochralski method is cut into a wafer having a predetermined thickness, lapping, etching, and mirror-finished into a silicon wafer, and the back surface of the silicon wafer is mirror-finished and then washed. Then, when the crystal defects existing inside the silicon wafer were measured by the crystal defect evaluation device, the signal intensity and the crystal defect volume density due to the crystal defects were calculated as follows: (signal intensity is 4 V or more defect density) / (signal intensity is 2 V
A method for evaluating a silicon single crystal, characterized in that the quality and electrical characteristics of a silicon wafer are evaluated by calculating the ratio of the above defect densities.