JPH08264539A - Interconnection structure, semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain an interconnection structure having low contact resistance. CONSTITUTION: A multilevel interconnection 10 comprising Al alloy interconnection 8/thin Ti layer 5/thin TiN layer 6/thin Ti layer 7 is formed on an Si substrate 1. The multilevel interconnection 10 is covered with interlayer insulation layers 11-13 which are then etched by RIE using a resist pattern formed thereon as a mask thus making contact holes 15-17 reaching the thin Ti layer or the thin TiN layer. Furthermore, the resist is subjected to O2 plasma ashing and the thin Ti layer 7 is subjected to sputter etching thus exposing the thin TiN layer 6 on the bottom of the contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to aluminum (Al).
The present invention relates to a wiring structure mainly made of a conductive material such as, a semiconductor device having this wiring structure, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a multilayer wiring forming technique, a lower layer Al is used.
In order to connect the wiring and the upper wiring, a contact hole (also referred to as a via hole) communicating with the lower Al wiring is formed in the interlayer insulating film covering the lower Al wiring.

A silicon oxide-based film or a silicon nitride-based film is often used as the interlayer insulating film. To form a contact hole in such an insulating film, for example, a reaction using a fluorocarbon-based (CF-based) gas is performed. Reactive ion etching (RIE) is used.

However, when such a CF type gas is used, it is suitable for etching a contact hole, but when the formation of the contact hole is completed and the surface of the lower layer Al wiring is exposed, this surface becomes plasma. Exposed
Al and CF gas react to generate a reaction product. Such reaction products deteriorate the characteristics of the lower Al wiring and increase the contact resistance with the upper Al wiring. Moreover, in order to prevent this, a step of removing the reaction product is required.

As a method of solving such a problem, titanium nitride (TiN) / titanium (T) is formed on the surface of the lower Al wiring.
i) A technique in which a metal thin film having a laminated structure is formed and etching for forming a contact hole is finished when TiN is exposed is disclosed in Japanese Patent Laid-Open No. 6-275618 (H0).
1L21 / 3205).

[0006]

To form contact holes on a semiconductor substrate, a large number of contact holes are formed by one etching process instead of forming each contact hole individually. Depending on the unevenness of the underlying wiring layer, as shown in FIG.
There are different depths.

As described above, when simultaneously forming contact holes having different depths, the formation of shallow contact holes tends to be over-etched until the formation of deep contact holes is completed.

Therefore, even if the etching is terminated with TiN as in the conventional example, TiN has a relatively low etching selectivity with respect to the CF-based gas, so that the shallow contact hole which is over-etched reaches TiN. The thigh is etched and the Ti or Al wiring thereunder is exposed.

When the Al wiring is exposed, as described above, C
A reaction product with the F-based gas is produced.

Further, when Ti is exposed, an altered layer made of a CF polymer or a compound such as Ti-O, Ti-C or Ti-F is formed.

After the contact holes are formed, it is common to perform ashing (ashing) treatment using oxygen on the resist used as a mask (for example, ashing treatment of irradiating O ₂ plasma). If Ti is exposed by etching, the CF polymer or Ti formed on the surface of Ti by this ashing treatment
The altered layer such as -C is oxidized to generate a reaction product, which further increases the contact resistance.

FIG. 8 shows a Ti thin film formed on a substrate with CF ₄
9 is a photograph of a cross section of the substrate and the Ti film after being irradiated with O ₂ plasma after being slightly etched by RIE using SEM (Scanning Electron Microscope), and FIG. Instead, the SEM of the cross section of the substrate and the TiN thin film after the same treatment is performed.
It is a photograph observed in.

From both figures, the surface of the Ti thin film is exposed to the plasma by RIE and O ₂ plasma irradiation, and reaction products (a thin film portion moving in a white line near the surface) are generated on the surface of the Ti thin film. However, it can be seen that no reaction product is generated on the surface of TiN.

FIG. 10 is a graph showing the results of measuring the film thickness of the reaction product generated on the surface of the Ti film under the respective processing conditions. The reaction product is generated even by the processing only by RIE or O ₂ plasma irradiation. Occurs, but RIE and O ₂
It can be seen that the synergistic effect with the plasma causes the reaction product after RIE to grow significantly by the O ₂ plasma irradiation.

FIG. 11 shows the reaction product formed on the Ti surface by RIE using XPS (X-ray photoelectron spectroscopy: X-ray Ph
The results of analysis by otoelectron Spectroscopy)
Since C, O, and F spectra derived from i-C, Ti-O, and Ti-F can be seen, it can be seen that this reaction product is a film formed of these compounds.

FIG. 12 shows the result of XPS analysis of the reaction product formed on the Ti surface by the irradiation of O ₂ plasma after RIE, and O and F spectra due to Ti—O and Ti—F can be seen. From this, it is understood that this reaction product is a film composed of these compounds.

Incidentally, in FIG. 12, compared with FIG. 11, Ti--C
However, it is considered that Ti—C was oxidized by the O ₂ plasma irradiation and changed into Ti—O.

FIG. 13 shows T after irradiation with RIE + O ₂ plasma.
The results of sputter etching the surfaces of i and TiN using argon gas are shown. By this sputter etching, reaction products on the Ti surface are removed,
It can be seen that the contact resistance is also improved.

FIG. 14 shows a comparison of the contact resistances when the RIE + O ₂ plasma irradiation is applied to the Ti thin film and when the TiN thin film is applied under the condition that the areas of the contact holes (connection holes) are different.

From this figure, it can be seen that the TiN thin film has a lower contact resistance as a whole.

As described above, T
There is a large difference in contact resistance depending on whether iN or Ti is exposed.

Therefore, in the conventional example, in order to prevent Ti from being exposed even by overetching, Ti
It is necessary to make the film thickness of N sufficiently thick.
In addition to increasing the total film thickness as the lower layer wiring, the step difference in the underlying layer becomes severe, making it difficult to flatten the interlayer insulating film.
There is a risk that it will also hinder the formation of upper layer wiring.

In view of the above problems, the present invention provides a wiring structure, a semiconductor device, and a method for manufacturing a semiconductor device, in which a contact hole having a low contact resistance can be easily formed.

[0024]

According to a first aspect of the present invention, there is provided a wiring structure in which a second wiring having a reflectance lower than that of the first wiring is provided on the first wiring, and the second wiring is It is a laminate of two or more different conductive materials.

Further, in the wiring structure according to the second aspect, the conductive material of the lower layer is made of a material whose wiring characteristics are not easily deteriorated even by etching.

According to a third aspect of the present invention, in the wiring structure, the second wiring is a laminated body made of two or more different conductive materials, and the etching rate for a predetermined etchant is:
The conductive material in the upper layer is slower than the conductive material in the lower layer.

According to a fourth aspect of the present invention, there is provided a wiring structure in which the first wiring is made of a conductive material containing aluminum as a component, and the second wiring is a laminated body made of two or more different conductive materials. And a lower layer conductive material made of titanium nitride.

In the wiring structure according to a fifth aspect of the invention, a titanium layer is formed between the lower conductive material and the first wiring.

A semiconductor device according to a sixth aspect of the present invention is a semiconductor device having the wiring structure according to any one of the first to fourth aspects, an insulating film covering the wiring structure, and a bottom surface formed on the insulating film. And a contact hole reaching the conductive material in the lower layer.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the wiring structure according to any one of the first to fourth aspects is formed on a substrate, and the wiring structure is covered with an insulating film. A step of patterning a resist on the insulating film, and a step of etching the insulating film with an etching technique using the resist pattern as a mask to form a contact hole reaching the conductive material of the lower layer. It includes and.

Further, in the method of manufacturing a semiconductor device according to claim 8, the etching uses at least two kinds of techniques.

In the method of manufacturing a semiconductor device according to a ninth aspect, a step of covering the wiring with an insulating film and forming a contact hole reaching the wiring by using at least two kinds of etching techniques in the insulating film. And the step of performing.

In the method of manufacturing a semiconductor device according to a tenth aspect, a dry etching technique and a sputter etching technique are used together as the etching.

According to an eleventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the wiring structure according to any one of the first to fourth aspects is formed on a substrate, and the wiring structure is covered with an insulating film. A step of etching the insulating film by using a lithography technique and a first etching technique to form a contact hole reaching the laminated body, and a step of forming a contact hole on the surface of the laminated body by a second etching technique. Etching to expose the conductive material in the lower layer of the stacked body.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step using the first etching technique,
A step of ashing the resist used in lithography with an oxygen-based gas is provided between the step using the second etching technique and the step using the second etching technique.

According to a thirteenth aspect of the present invention, a method of manufacturing a semiconductor device uses a dry etching technique as the first etching technique and a sputter etching technique as the second etching technique.

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device, a CF type gas is used as an etchant during the dry etching.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor device, a step of forming a wiring structure by providing a conductive third wiring on the first wiring, and covering the wiring structure with an insulating film. A step of forming a contact hole that reaches the third wiring material by etching the insulating film by using a lithography technique and an etching technique, and at least the surface of the third wiring material is subjected to subsequent plasma irradiation or the like. And a step of transforming the material into a material that is not easily affected by the treatment.

According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device, a step of forming a wiring structure by providing a conductive third wiring on the first wiring, and covering the wiring structure with an insulating film. And a step of etching the insulating film to form a contact hole reaching the third wiring member by using a lithography technique and an etching technique, and at least the surface of the third wiring member is also irradiated with O ₂ plasma. And a step of transforming the material into a material that is not easily oxidized.

According to a seventeenth aspect of the present invention, in the method of manufacturing a semiconductor device, a step of forming a wiring structure by providing a conductive third wiring on the first wiring, and covering the wiring structure with an insulating film. A step of etching the insulating film by using a lithography technique and an etching technique to form a contact hole reaching the third wiring material, and a step of nitriding or carbonizing at least the surface of the third wiring material. It includes and.

Further, in the method of manufacturing a semiconductor device according to the eighteenth aspect, the third wiring is made of a material having a reflectance lower than that of the first wiring.

According to a nineteenth aspect of the present invention, in the method of manufacturing a semiconductor device, the first wiring is made of a conductive material containing aluminum as a component, and the third wiring is made of a conductive material containing titanium as a component. .

[0043]

According to the invention of claim 1 or 18, the resist is unlikely to be affected by reflected light during exposure.

According to the second aspect of the present invention, even if the etching reaches the conductive material in the lower layer by over-etching, the conductive material in the lower layer is not easily affected by the etchant used for the etching.

In the inventions according to claims 3, 4, and 7, even if over-etching, there is a possibility that the conductive material in the lower layer is etched because the conductive material in the upper layer having a slow etching rate is interposed. Low.

In the fifth aspect of the invention, since the Ti layer is formed between the conductive material in the lower layer and the first wiring, the oxide of the first wiring can be reduced.

According to the invention described in claim 6, it is possible to provide a semiconductor device having a wiring structure having the same effect as in claims 1 to 5.

In the invention described in claims 8 to 13, it is easy to control the etching to be stopped by the conductive material in the lower layer of the second wiring, for example, by selectively using the two kinds of etching techniques.

According to the thirteenth and fourteenth aspects of the present invention, even if a damage layer is formed at the bottom of the contact hole due to the effect of plasma irradiation during dry etching or resist ashing using oxygen, the subsequent damage may occur. This damaged layer can be removed by sputter etching.

According to the invention described in claims 15 to 19, at least the surface of the bottom of the contact hole is changed to a material which is not easily affected by the subsequent treatment such as O ₂ plasma irradiation such as resist ashing. Since various treatments such as nitriding treatment and carbonizing treatment are performed, reaction products are less likely to be generated at the bottom of the contact hole.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in a two-layer wiring will be described below with reference to the drawings. (First Embodiment) FIGS. 1 to 7 are sectional views showing a manufacturing process of a semiconductor device according to the first embodiment, which will be described below in order.

Step 1 (FIG. 1): A silicon oxide film 3 is formed on a single crystal silicon substrate 1 with a field oxide film 2 in between, and a metal wiring layer 4 is formed on the silicon oxide film 3. The metal wiring layer 4 is, for example, an aluminum alloy (Al-Si (1%)-Cu (0.5%)) having a thickness of 600 nm.
The formation is performed by using a magnetron sputtering method, and the conditions (example) are set to substrate temperature: 200 ° C., DC power: 9 kw, and pressure: 2 mTorr.

Further, on the metal wiring layer 4, a titanium (Ti) thin film 5, a titanium nitride (TiN) thin film 6 and Ti are formed.
The thin films 7 are sequentially laminated. The formation is performed by using a magnetron sputtering method, and the conditions (example) are: substrate temperature: 30
0 ° C., DC power: 9 kw, pressure: 2 mTorr, and deposited film thicknesses are Ti / TiN / Ti = 20 n, respectively.
m / 50 nm / 20 nm.

The Ti thin film 7 and the TiN thin film 6 function as so-called cap metals that prevent light from being reflected by Al in the lithography process and prevent reflected light from affecting the resist.

Contrary to the present embodiment, the TiN thin film 6 / Ti
The structure of the thin film 7 also has an effect of preventing reflected light, but Ti
It is much inferior to the / TiN structure.

Step 2 (FIG. 2): The metal wiring layer 4, the Ti thin film 5, the TiN thin film 6 and the Ti thin film 7 are patterned into a predetermined shape by a usual lithography technique and a dry etching technique (RIE method or the like), and a metal is formed. First wiring 8 made of wiring material and second wiring 9 made of Ti / TiN / Ti
And the laminated wiring 10 ...

Step 3 (FIG. 3): TEOS (Tetraet) is formed on the exposed silicon oxide film 3 and laminated wiring 10.
hyloxysilane or Tetraethylorthosilicate: Si (O
An interlayer insulating film 11 having a uniform film thickness (200 nm) is deposited by the plasma CVD method using C ₂ H ₅ ) ₄ ). The deposition condition (example) of the interlayer insulating film 11 is pressure: 9 Torr, T
EOS / O ₂ flow rate: 450/500 sccm, substrate temperature: 370 ° C., RF power: 2.5 W / cm ² ,
Deposition rate: about 850 nm / min.

On the interlayer insulating film 11, SOG (Spin
The interlayer insulating film 12 is formed by a spin coating method using On Glass).

A uniform film thickness (200 n) is formed on the interlayer insulating film 12 by the plasma CVD method using TEOS.
The interlayer insulating film 13 of m) is deposited. The deposition condition and deposition rate of the interlayer insulating film 13 are the same as those of the interlayer insulating film 11.

The interlayer insulating film 12 has excellent step coverage and flatness, and the surface of the interlayer insulating film 13 is substantially flat.

The interlayer insulating films 11 and 13 also have a function of preventing moisture contained in the interlayer insulating film (SOG) 12 from affecting other devices.

Step 4 (FIG. 4): Each of the interlayer insulating films 11 to 11
A resist pattern 14 is formed on the interlayer insulating film 13 to form a contact hole (via hole) in the interlayer insulating film 13.

Step 5 (FIG. 5): Using the resist pattern 14 as an etching mask, contact holes 15, 16 and 17 are formed by a normal RIE method. As etching conditions (example), pressure: 200 mTorr, gas flow rate: CHF ₃ / CF ₄ / Ar = 30/30/200 scc
m, RF power: 3.9 W / cm ² .

At this time, as described above, each of the interlayer insulating films 11 to 13 has a covering step property and a flatness so as to eliminate the step difference between the laminated wirings 10 ... Which is caused by the presence of the field oxide film 2 or the like. Since the excellent material is used, the depths of the contact holes 15 to 17 differ depending on the level difference of the laminated wiring 10.

That is, the contact hole 15 corresponding to the laminated wiring 10 on the field oxide film 2,
The depth of 17 is shallower than the contact hole 16 corresponding to the laminated wiring 10 located relatively below. Therefore, when the interlayer insulating films 11 to 13 are dry-etched to form the contact holes 15 to 17, the contact holes 15 and 17 are completed earlier than the contact hole 16.

That is, when the contact holes 15 and 17 are completed, the laminated wiring 10 at a high position is exposed, but at that time, the contact hole 16 is not completed yet. Therefore, until the contact holes 15 and 17 are completed and the contact hole 16 is completed, the laminated wiring 10 at a high position is exposed to the plasma of the etching gas and overetched.

The specific values will be described below.

The contact holes 15 and 17 have a depth of 400 nm, and the contact hole 16 has a depth of 1100 n.
At m, there is a difference of 700 nm.

When the contact holes 15 and 17 are completed, the metal exposed to plasma is the Ti thin film 7.
The etching selection ratio with respect to OS and SOG is about 25. Since the thickness of this Ti thin film 7 is 20 nm,
By the time the Ti thin film 7 is etched during the over-etching, the contact hole 16 is etched by 500 n.
Proceed m.

Since the etching selection ratio of the TiN thin film 6 to TEOS and SOG is about 10, the contact hole 16 is further etched by 200 nm, and when the formation is completed, the contact holes 15 and 17 are formed.
Is located at a position where the TiN thin film 6 is left by 30 nm.

Step 6 (FIG. 6): The resist pattern 14 used as the mask is removed by O ₂ plasma ashing. At this time, a reaction product due to plasma irradiation is generated on the surface of the Ti thin film 7 exposed at the bottom of the contact hole 16.

Step 7 (FIG. 7): Deep contact hole 1
In order to remove the Ti thin film 7 exposed on the bottom surface of 6, the contact holes 15 to 17 are further etched by 25 nm by sputter etching using argon (Ar). Ar sputtering is not very selective with respect to the material, and the formation of the deep contact hole 16 ends at the portion where the TiN thin film 6 is cut by 5 nm, and the shallow contact holes 15 and 17 are formed at the portion where the TiN thin film 6 remains at 5 nm. finish.

By using Ar sputtering as described above, the reaction product generated on the surface of the Ti thin film in step 6 is also removed, and the contact resistance is improved as shown in FIG. (Second Embodiment) Next, the manufacturing process of the semiconductor device according to the second embodiment will be sequentially described.

Since steps (1) to (4) of the second embodiment are the same as steps 1 to 4 of the first embodiment, the description thereof will be omitted.

The process (5) will be described below.

Step (5) (FIG. 5): Contact hole 1
The process up to forming 5 to 17 is the same as step 5 in the first embodiment.

In this state, the contact holes 15 to 17
The Ti thin film 7 or TiN thin film 6 exposed at the bottom of the nitriding layer is subjected to nitriding treatment to turn all the surface into TiN (TiN thin film
Does not change because it is originally nitrided).

The nitriding treatment is performed by irradiating with N ₂ plasma.

Step (6) (FIG. 6): The resist pattern 14 used as the mask is removed by O ₂ plasma ashing treatment. At this time, each contact hole 15-
All exposed at the bottom of 17 is a TiN thin film,
As is clear from the experimental results shown in FIG. 14, no reaction product is generated on the surface of the TiN thin film even by plasma irradiation.

Thus, the contact holes 15-17
By forming the TiN thin film at the bottom of the substrate, the reaction product is not generated by exposure to plasma. (Third Embodiment) Next, a manufacturing process of a semiconductor device according to the third embodiment will be sequentially described.

Since the steps 1 to 4 of the third embodiment are the same as the steps 1 to 4 in the first embodiment, the description thereof will be omitted.

The steps will be described below.

Process (FIG. 5): Contact hole 15 to
The process up to forming 17 is similar to the process 5 in the first embodiment.

In this state, the contact holes 15 to 17
The Ti thin film 7 or the TiN thin film 6 exposed at the bottom of is subjected to a carbonization treatment to convert all the surfaces into TiC.

The carbonization treatment is carried out, for example, by injecting carbon ions into the surface of the film and applying heat treatment (at 300 to 400 ° C. for 30 minutes).

By RIE at the time of forming the contact hole, an altered layer of Ti--C is generated on the surface of the Ti thin film 7, but this altered layer is electrically unstable and is easily oxidized by O ₂ plasma irradiation. , Becomes a reaction product.

However, as in the third embodiment, Ti
By forcibly converting the surface of the thin film 7 into TiC by carbonization, this surface is electrically stabilized and becomes difficult to be oxidized by O ₂ plasma.

By the carbonization treatment, nitrogen atoms and carbon atoms are mixed in titanium on the surface of the TiN thin film 6, but since such a structure is also electrically stable, O ₂
Not easily oxidized by plasma.

Step (FIG. 6): The resist pattern 14 used as a mask is removed by O ₂ plasma ashing treatment. At this time, each contact hole 15-17
Since the bottom of the is carbonized, reaction products are less likely to be generated even by plasma irradiation.

The present invention is not limited to the above embodiment, but may be carried out as follows.

As the sputtering method, other than magnetron sputtering, diode sputtering, high frequency sputtering, quadrupole sputtering or the like may be used.

As a method of sputter etching, Ar is used.
Besides, an inert gas such as He, Ne, or Xe may be used, and a reactive ion beam using a reactive gas (for example, CCl ₄ , SF ₆ ) in addition to the use of these inert gases. Etching (RIBE, also called reactive ion milling) may be used.

The interlayer insulating film may be formed by a method other than the CVD method (PVD method such as sputtering method or vapor deposition method, oxidation method).

The interlayer insulating film may be replaced with another insulating film (various silicate glass, alumina, silicon nitride film, titanium oxide film, etc.).

A laminated structure of Ti / TiN / Ti was used as the second wiring. For example, Ti / (TiN / Ti)
^It may have a structure in which TiN / Ti is repeated like ⁿ (n = integer).

Incidentally, in the second and third embodiments, Ti may be entirely used instead of such a laminated structure.

Although Ti is used as a film having a high selection ratio with respect to TEOS and SOG, molybdenum (Mo), tungsten (W), tungsten nitride (TiW), and doped amorphous silicon (a-Si) are used. May be.

As the nitriding treatment, in addition to N ₂ plasma irradiation, RTP (Rap
id Thermal Process) or thermal annealing may be used.

As the carbonization treatment, the heat treatment after carbon ion implantation may be replaced with RTP.

[0100]

According to the inventions of claims 1 and 18, a highly accurate contact hole can be formed.

According to the second aspect of the invention, the wiring characteristics are good at the bottom of the contact hole, and the contact resistance can be reduced.

In the inventions according to claims 3, 4 and 7, the etching control becomes easy and the manufacturing cost is reduced.
It is possible to improve the yield.

According to the fifth aspect of the invention, the oxide of the first wiring can be reduced, and the wiring characteristics can be improved.

According to the invention described in claim 6, it is possible to provide a semiconductor device having a wiring structure having the same effects as those of claims 1 to 5.

According to the invention described in claims 8 to 13, the etching control becomes easy and the manufacturing cost is reduced.
It is possible to improve the yield.

In the thirteenth and fourteenth aspects of the invention, even if a damage layer is formed at the bottom of the contact hole, the damage layer can be removed by the subsequent sputter etching. The deterioration of contact resistance can be prevented.

According to the invention described in claims 15 to 19, at least the surface of the bottom of the contact hole is changed to a material which is not easily affected by the subsequent treatment such as O ₂ plasma irradiation such as resist ashing. Since various treatments such as nitriding treatment and carbonizing treatment are performed, reaction products are less likely to be generated at the bottom of the contact hole.

Therefore, deterioration of contact resistance due to this reaction product can be prevented.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view showing a manufacturing process of a semiconductor device of an embodiment in which a wiring structure according to an embodiment of the present invention is embodied.

FIG. 2 is a vertical cross-sectional view showing a manufacturing process of a semiconductor device of an embodiment in which a wiring structure according to an embodiment of the present invention is embodied.

FIG. 3 is a vertical cross-sectional view showing a manufacturing process of a semiconductor device of an embodiment in which a wiring structure according to an embodiment of the present invention is embodied.

FIG. 4 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of one embodiment in which the wiring structure in the embodiment of the present invention is embodied.

FIG. 5 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of one embodiment in which the wiring structure of the embodiment of the invention is embodied.

FIG. 6 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of one embodiment in which the wiring structure of the embodiment of the invention is embodied.

FIG. 7 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of one embodiment in which the wiring structure of the embodiment of the invention is embodied.

FIG. 8 is an SEM photograph showing a cross section of the surface of a Ti thin film formed on a substrate, which was etched by RIE and further irradiated with O ₂ plasma.

FIG. 9: RIE is performed on the surface of the TiN thin film formed on the substrate.
₂ is an SEM photograph of a cross section taken after etching by the method of FIG.

FIG. 10 is a diagram showing the results of measuring the film thickness of a reaction product generated on the surface of a Ti film under various processing conditions.

FIG. 11 is a diagram showing a result of XPS analysis of a reaction product formed on a Ti thin film surface by RIE.

FIG. 12 is a diagram showing a result of XPS analysis of a reaction product formed on a surface of a Ti thin film by RIE + O ₂ plasma irradiation.

FIG. 13: TiN and T after RIE + O ₂ plasma irradiation
It is a figure which shows the relationship between a sputtering amount and contact resistance when the surface of i is sputter-etched using argon gas, respectively.

FIG. 14 is a diagram showing the relationship between contact resistance and contact hole size when a Ti thin film is irradiated with RIE + O ₂ plasma and when it is irradiated with a TiN thin film.

FIG. 15 is a vertical cross-sectional view of a semiconductor device in a conventional example.

[Explanation of symbols]

 5 Ti Thin Film 6 TiN Thin Film (Lower Conductive Layer) 7 Ti Thin Film (Upper Conductive Layer) (Third Wiring Material) 8 First Wiring 9 Second Wiring 10 Laminated Wiring (Wiring Structure) 11-13 Interlayer Insulating Film 14 Resist Pattern 15-17 Contact hole

Claims (19)

[Claims] 1. A second wiring having a reflectance lower than that of the first wiring is provided on the first wiring, and the second wiring is a laminated body made of two or more different conductive materials. Characterized wiring structure. 2. The wiring structure according to claim 1, wherein the conductive material of the lower layer is made of a material whose wiring characteristics are not easily deteriorated even by etching. 3. A laminated body of two or more kinds of conductive materials having different second wirings, wherein an etching rate of a predetermined etchant is higher in a conductive material in an upper layer than in a conductive material in a lower layer. The wiring structure according to claim 1 or 2. 4. The first wiring is made of a conductive material containing aluminum as a component, and the second wiring is a laminated body made of two or more kinds of different conductive materials. The uppermost conductive material made of titanium and titanium nitride. The wiring structure according to claim 1, further comprising a lower conductive material made of 5. The wiring structure according to claim 4, wherein a titanium layer is formed between the lower conductive material and the first wiring. 6. The wiring structure according to claim 1, an insulating film covering the wiring structure, and a contact hole formed in the insulating film, the bottom surface of which reaches the conductive material of the lower layer. A semiconductor device comprising: 7. A step of forming the wiring structure according to claim 1 on a substrate, a step of covering the wiring structure with an insulating film, and a resist patterning on the insulating film. And a step of forming a contact hole reaching the conductive material in the lower layer by etching the insulating film by using an etching technique with the resist pattern as a mask, and manufacturing the semiconductor device. Method. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching uses at least two kinds of techniques. 9. A semiconductor device comprising: a step of covering a wiring with an insulating film; and a step of forming a contact hole reaching the wiring in the insulating film by using at least two kinds of etching techniques. Manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the etching uses a dry etching technique and a sputter etching technique together. 11. A process of forming the wiring structure according to claim 1 on a substrate, a process of covering the wiring structure with an insulating film, a lithography technique and a first etching technique. And etching the insulating film to form a contact hole reaching the stacked body, and using a second etching technique, the surface of the stacked body is etched to remove the conductive material in the lower layer of the stacked body. And a step of exposing the semiconductor device. 12. A step of ashing a resist used in lithography with an oxygen-based gas is provided between the step using the first etching technique and the step using the second etching technique. Claim 1 characterized by the above.
1. The method for manufacturing a semiconductor device according to 1. 13. The method of manufacturing a semiconductor device according to claim 11, wherein a dry etching technique is used as the first etching technique, and a sputter etching technique is used as the second etching technique. 14. The method of manufacturing a semiconductor device according to claim 10, wherein a CF-based gas is used as an etchant during the dry etching. 15. A step of forming a wiring structure by providing a conductive third wiring on the first wiring, a step of covering the wiring structure with an insulating film, and a lithographic technique and an etching technique. A step of etching an insulating film to form a contact hole reaching the third wiring material; and a step of transforming at least the surface of the third wiring material into a material that is not easily affected by subsequent treatment such as plasma irradiation. A method of manufacturing a semiconductor device, comprising: 16. A step of forming a wiring structure by providing a conductive third wiring on the first wiring, a step of covering the wiring structure with an insulating film, and a lithographic technique and an etching technique. A step of etching the insulating film to form a contact hole reaching the third wiring material; and a step of transforming at least the surface of the third wiring material into a material that is not easily oxidized by O ₂ plasma irradiation. And a method for manufacturing a semiconductor device. 17. A step of forming a wiring structure by providing a conductive third wiring on the first wiring, a step of covering the wiring structure with an insulating film, and a lithographic technique and an etching technique. Manufacturing a semiconductor device, comprising: a step of etching an insulating film to form a contact hole reaching the third wiring material; and a step of nitriding or carbonizing at least the surface of the third wiring material. Method. 18. The method according to claim 15, wherein the third wiring is made of a material having a reflectance lower than that of the first wiring.
18. The method for manufacturing a semiconductor device according to any one of items 1 to 17. 19. The method according to claim 15, wherein the first wiring is made of a conductive material containing aluminum as a component, and the third wiring is made of a conductive material containing titanium as a component. A method for manufacturing a semiconductor device as described above.