JPH09321045A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase of resistance of Cu wiring and deterioration of reliability. SOLUTION: A first insulating layer 2A is formed on a Si substrate 1. A laminated wiring consisting of barrier films 3A and 3B and a Cu film 4 between them is formed on the first insulating layer 2A. Then, the wiring is exposed to a diluted silane gas 6 while being heated in a low pressure chamber to selectively form a Cu silicide layer 7 only on a part of the wiring on which Cu is exposed. A second insulating layer 2B is formed on the Cu siliside layer 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having copper wiring and a manufacturing method thereof.

[0002]

2. Description of the Related Art With the miniaturization and high integration of LSI, copper (Cu) having low resistance and high electromigration resistance has been developed.
Are being used. A first conventional example using copper wiring is Nobuyoshi Awaya and Nobuyoshi Awaya and Nobuyoshi Awaya.
Journal of Electronic Materials (Journa) by Yoshinobu Arita
l of Electronic Material
s) Vol. 21, No. 10, 1992, pp959
-954). This will be described below with reference to the cross-sectional view shown in FIG.

First, as shown in FIG. 3A, a Si nitride film 12 is formed on a silicon (Si) substrate 11 and has a high barrier property against copper (hereinafter referred to as Cu) and a high Cu oxidation preventing ability.
A barrier film 3A composed of chromium (Cr) and a barrier film 3B composed of Cu film 4 and Cr for the purpose of preventing Cu diffusion and improving the adhesion to the base are formed on the upper layer of A and patterned. To form a wiring composed of three conductive layers.

Next, as shown in FIG. 3B, a Si nitride film 12B is formed on the wiring to improve the oxidation resistance, corrosion resistance and adhesion of the Cu wiring.

On the other hand, Takewaki et al. Show a structure for improving oxidation resistance around a Cu wiring and a manufacturing method thereof (1995 IEICE Electronics Society Conference Proceedings 2, Lecture No. C-418, pp. 115-116). . Hereinafter, this manufacturing method will be described as a second conventional example with reference to the sectional view of FIG.

[0006] First, as shown in FIG.
After a first insulating film 14 composed of a Si oxide film is formed on the substrate 1, a wiring composed of a Cu film 4 is formed thereon. Subsequently, the Si substrate 11 is exposed to the monosilane (SiH ₄ ) gas 6 while heating, so that Cu and Si in the SiH ₄ gas react with each other. As shown in FIG. 4B, a Cu silicide layer ( Cu _x Si _y ) 7 is formed, and the Cu silicide layer 7 prevents oxidation of Cu.

Also, Miyazaki et al. Have proposed a method of preventing oxidation of Cu when forming an interlayer insulating film on Cu wiring (1).
Proc. Of the IEICE Electronics Society Conference, 995, Lecture No. C-419, pp117
-118). This method will be described below as a third conventional example with reference to the sectional view of FIG.

First, as shown in FIG. 5A, the Si substrate 1
First insulating film 1 composed of PSG film formed on 1
4, a barrier film 1 made of tungsten (W)
A barrier film 13B composed of 3A, a Cu film 4 and W is sequentially formed, an insulating film is used as an etching mask (not shown), and silicon tetrachloride (SiCl ₄ ) + nitrogen (N ₂ ) + oxygen (O ₂ ) 250 was used as the etching gas.
The above-mentioned three conductive layers are sequentially etched by a reactive ion etching method at a high temperature of ° C. to form a Cu wiring composed of a W film, a Cu film, and a laminated film of the W film.

Next, as shown in FIG. 5B, tetra-ethoxy-silan is used.
e, hereinafter referred to as TEOS). A plasma TEOS oxide film 15, which is a Si oxide film, is formed on a Cu wiring by a plasma CVD method using + O ₂ mixed gas.

In this high-temperature reactive ion etching step, a silicon oxide film-based side wall protective film is formed on the side wall of the Cu wiring. Further, in the presence of TEOS, oxidation of Cu is very slow. Oxidation does not pose a practical problem.

On the other hand, Okabe et al. Have clarified a method of forming a Si oxide film on the surface of a Cu film in a self-aligned manner without oxidizing Cu (Academic Lecture Meeting of Autumn Applied Physics Society, 1993, 29p-ZE-5). ). Hereinafter, this method will be described as a fourth conventional example with reference to FIG.

First, as shown in FIG. 6A, 1.0 to 5.0% by weight of Si is added to Cu by sputtering using an alloy target on a first insulating film 14 formed on a Si substrate 11. The contained Cu-Si alloy film 4A is formed with a thickness of 500 nm.

Next, as shown in FIG. 6 (b), the Si substrate 11 is subjected to a heat treatment at 500 ° C. for 1 hour in an N ₂ -7 ppm O ₂ atmosphere to diffuse Si in the Cu—Si alloy film 4A outwardly, Reacting with O _{2 on the} surface of the Cu—Si alloy film to oxidize Cu,
The i-oxide film 16 is formed.

[0014]

In the first prior art semiconductor device described above, since the Si nitride film is formed above and below the Cu wiring, all of oxidation of Cu, diffusion of Cu, and corrosion of Cu are suppressed. Can be prevented.

However, since the relative permittivity of the Si nitride film is nearly twice as large as that of the Si oxide film, the capacitance of the interlayer insulating film is significantly increased, and the signal delay due to the increase in capacitance is increased, resulting in deterioration of the performance of the semiconductor device. Bring In particular, in a fine semiconductor device, the ratio of the delay due to the interlayer film capacitance to the delay of the entire circuit increases, so that the influence of the delay becomes serious and the merit of using Cu is lost. is there.

As in the second conventional example, Cu
When the silicide layer is formed, there is an effect of improving the oxidation resistance, corrosion resistance and electromigration resistance of the Cu wiring, and the interlayer capacitance does not increase because it is not necessary to use a Si nitride film for the interlayer insulating film. However, the specific surface area of the high-resistance Cu silicide layer with respect to the surface area of the entire wiring is increased, so that the wiring resistance is increased.

Further, as the wiring becomes finer, the ratio of the surface area to the volume of the wiring becomes higher, so that the rate of increase in the wiring resistance further increases, and the characteristics of the semiconductor device deteriorate. Therefore, there is no merit of adopting Cu having low resistance for the main conductive layer of the wiring. Further, since the reaction between Cu and SiH ₄ is relatively fast, control is not easy. Therefore, it is difficult to control the thickness of the silicide layer, it is difficult to obtain a uniform wiring resistance in a wafer surface or in a lot, and it is difficult to obtain a semiconductor device having stable electric characteristics.

As in the third conventional example, when etching, C
The method of forming a Si oxide film-based protective film on the side wall of the u wiring and then forming the Si oxide film on the Cu wiring by using the TEOS source can prevent Cu oxidation during the formation of the insulating film.
The wiring resistance does not increase. Also, there is no delay due to an increase in interlayer capacitance.

However, the protective film on the side wall of the Cu wiring has a low thermal stability formed under a non-equilibrium state during plasma etching of the conductive film and does not have a high ability to prevent the diffusion of Cu. Since the Si oxide film formed by the source plasma CVD method also does not have a very high barrier property against Cu, diffusion and oxidation of Cu progress due to a plurality of heat treatments performed when multi-layering the wiring, so that the inter-wiring However, there is a possibility that a current leakage failure and an increase in wiring resistance may occur, and it is difficult to obtain a high production yield and long-term reliability.

As in the fourth conventional example, in a method of forming a Si oxide film on the surface of a Cu—Si alloy film in a self-aligned manner, C
By adding Si to u, the electric resistance of Cu becomes 3μΩ
cm, the advantage of Cu wiring is lost. Further, since a high temperature of 500 ° C. and a long time of one hour are required to form a Si oxide film, there is a disadvantage that manufacturing costs increase.

An object of the present invention is to minimize the increase in the electrical resistance of a Cu wiring while minimizing the long-term reliability of Cu wiring such as oxidation resistance, corrosion resistance, electromigration resistance, and stress migration resistance, and manufacturing yield. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can improve the performance.

[0022]

A semiconductor device according to a first invention comprises a first insulating film provided on a semiconductor substrate and the first insulating film.
A wiring formed of a first conductive film and a second conductive film sequentially provided on the insulating film and a copper silicon compound layer provided on a side surface of the copper film, and a wiring provided on the first insulating film and the wiring. It is characterized in that it includes a formed second insulating film.

A semiconductor device according to a second aspect of the present invention is a semiconductor device comprising: a first insulating film provided on a semiconductor substrate; a wiring groove formed in the first insulating film; a copper film provided in the wiring groove; A wiring formed of a first conductive film provided on the bottom and side walls of the copper film and a copper silicon compound layer provided on the surface of the copper film, and a first insulating film and a wiring provided on the wiring. It is characterized by including two insulating films.

In the method of manufacturing a semiconductor device of the third invention, a step of forming a first insulating film on a semiconductor substrate, and a first conductive film, a copper film and a second conductive film are sequentially formed on the first insulating film. A step of forming, a step of patterning the second conductive film, the copper film and the first conductive film to form a wiring, and a step of forming an exposed copper film surface of a sidewall portion of the wiring into a copper silicon compound,
And a step of forming a second insulating film on the first insulating film and the wiring.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a wiring groove in the first insulating film, and an entire surface including the wiring groove. A step of sequentially forming a first conductive film and a copper film to fill the wiring groove, and a step of removing the first conductive film and the copper film outside the wiring groove to form the first conductive film and the copper film The method comprises: forming a wiring; forming a copper silicon compound layer on the exposed copper film surface above the wiring; and forming a second insulating film on the entire surface including the copper silicon compound layer surface. It is what

[0026]

According to the present invention, the periphery of the wiring is covered with a barrier film and a Cu silicide layer which are effective for preventing Cu oxidation, preventing Cu diffusion, and improving the electromigration resistance and stress migration resistance of Cu. Cu wiring can be formed with high controllability, high uniformity, and high reproducibility.

Therefore, even if an insulating film such as a Si oxide film having a lower non-dielectric constant than the Si nitride film but having the possibility of oxidizing Cu is formed on the Cu wiring, Cu
Is not oxidized, and the long-term reliability of the Cu wiring is improved.
Further, even when heat treatment is performed a plurality of times for multilayering the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated, so that a semiconductor device having high performance and high long-term reliability can be manufactured with high yield.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a first insulating film 2A made of a Si oxide film is formed on a Si substrate 1 by a thermal oxidation method or by using SiH ₄ and nitrous oxide (N ₂ O) or TEO.
About 500 nm by the plasma CVD method using S and O ₂
Formed to a thickness of

The first insulating film is not limited to the Si oxide film, but other than this, a PSG film or a BPSG film containing phosphorus (P) or boron (B) in the Si oxide film, a polyimide film, or the like. It may be an organic film. Also, the forming method is not limited to the plasma CVD method. Subsequently, a barrier film 3A composed of a titanium nitride film (hereinafter referred to as a TiN film) is formed by a reactive sputtering method using a titanium target at a power of 2.5 to 5.0 kW and a pressure of 2 to 2.
It is formed with a thickness of 25 to 100 nm under the condition of 10 mTorr.

Next, a Cu film 4 is formed on the barrier film 3A by a sputtering method under the conditions of a film forming power of 2.0 to 5.0 kW and a film forming pressure of 2 to 10 mTorr in a thickness of 250 to 500 nm.
Formed with a thickness of Next, a barrier film 3B made of a TiN film is formed on the Cu film 4 with a thickness of 25 to 100 nm under the same conditions as the barrier film 3A.

The barrier films 3A and 3B are not limited to TiN films.
In addition, titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (T
a), tungsten (W), silicides, borides, nitrides, carbides thereof, and alloys containing these can be used.

This barrier film is made of C, which is the main conductive layer of the wiring.
It is formed for the purpose of preventing oxidation of u, diffusion of Cu into the insulating film, and ensuring adhesion with the underlying first insulating film.

Next, a thickness of 30 nm is formed on the barrier film 3B by a plasma CVD method using TEOS + O ₂ as a source.
An oxide film having a thickness of 0 to 500 nm is formed, and is patterned by a reactive ion etching method using a photoresist as a mask to form an etching mask 5 at the time of wiring processing.

Next, as shown in FIG.
l ₄ , chlorine (Cl ₂ ), ammonia (HN ₃ ) and N ₂
Temperature of 280 by a reactive ion etching method using
° C, pressure = 2 Pa, SiCl ₄ = 20 sccm, Cl _{2
= 20sccm, HN 3 = 10~30sccm,} N 2 =
80 sccm, N ₂ = 80 sccm, RF power = 20
Under the condition of 0 W, the barrier film 3B, the Cu film 4 and the barrier film 3
A is sequentially etched to form a wiring. Subsequently, the mask 5 remaining on the barrier film 3B is removed by a reactive ion etching method using a carbon-fluorine-based gas.

Next, as shown in FIG.
Is introduced into a vacuum chamber maintained at a constant temperature of 300 ° C. to 400 ° C., and SiH ₄ gas or Si diluted with an inert gas such as argon (Ar) or N ₂ at a pressure of 50 to 500 Pa.
The H ₄ gas 6 is introduced into the vacuum chamber, and the Si substrate 1 is exposed to the atmosphere of the SiH ₄ gas 6. Then, the exposed Cu on the side wall of the wiring
The film reacts with the SiH ₄ gas to form a C film having a thickness of 10 to 20 nm.
u silicide layer 7 (Cu _x Si _y compound, x, y are integers) to form a wiring side wall.

The composition and thickness of the Cu silicide layer 7 formed on the side wall of the wiring are determined by the pressure, temperature, exposure time, concentration of SiH ₄ gas, partial pressure and the like.
A Cu silicide layer having a thickness of 5 to 20 nm can be formed by a minute treatment. In addition to monosilane, disilane (Si ₂ H ₆ ) having a Si—H bond, difluorsilane (SiH ₂ F ₂ ) also having an F bond, or the like can be used. Cu using diluted SiH ₄ gas under reduced pressure atmosphere
When silicidation is used, the reaction rate of silicidation can be reduced. Therefore, a thin Cu silicide film can be formed with high uniformity and controllability, and the electrical characteristics of the Cu wiring become stable.

In this step, if Cu on the wiring side wall is oxidized or Si oxide film-based deposits are present on the wiring side wall, it is difficult for Cu to react with the SiH ₄ gas. Therefore, when Cu is oxidized, SiH ₄
If a hydrogen (H ₂ ) gas is introduced before the introduction and heated to about 400 ° C., the Cu oxide can be reduced to Cu, and the subsequent silicidation reaction can be promoted. This pretreatment may be performed in a vacuum chamber for introducing SiH ₄ gas, or may be performed in another vacuum chamber and then transferred to a vacuum chamber for introducing SiH ₄ gas without breaking vacuum.

If Si oxide film-based deposits are present on the wiring side walls, hydrofluoric acid (HF) gas is introduced and exposed in a separate vacuum chamber before introducing SiH ₄ as pretreatment. Can be removed, and the subsequent silicidation reaction can be promoted. At this time, Cu is not etched, but the barrier film may be etched. Therefore, it is necessary to determine pretreatment conditions in consideration of the etching rate of the barrier film and the deposit.

The conveying Therefore pretreatment using highly corrosive HF gas, performed in another vacuum chamber and vacuum chamber to introduce SiH ₄ gas, a vacuum chamber for introducing the SiH ₄ gas without subsequent breaking the vacuum I do. When a thin Cu silicide layer is formed on the side wall of the wiring, the oxidation resistance of the wiring is greatly improved, and the thickness of the Cu silicide layer is sufficiently thin, so that the wiring resistance hardly increases.

Subsequently, as shown in FIG. 1D, the second insulating film 2B made of a silicon oxide film is formed on the wiring by a plasma CVD method using TEOS + O ₂ as a source without breaking the vacuum to 500 to 500 μm. Deposit with a thickness of 1000 nm. The deposition of the insulating film may be performed in the same vacuum chamber as the vacuum chamber in which the Cu silicide layer is formed, or after being transferred to another vacuum chamber. As shown in the conventional example, in the plasma CVD using TEOS as a source, Cu is slowly oxidized and the Cu surface is silicified, so that the side wall of the wiring is hardly oxidized when the second insulating film is deposited.

When the surface protection by silicidation of the wiring side wall and the deposition of the insulating film are performed in a continuous process, the above advantages can be obtained without increasing the number of steps. However, continuous vacuum processing of silicidation of Cu and deposition of an insulating film cannot be performed due to a problem in the configuration of the apparatus, or continuous vacuum processing is performed by a plasma CVD method using SiH ₄ + N ₂ O, which easily oxidizes Cu. In this case, the O ₂ or N ₂ O component adsorbed on the wiring surface when the Si substrate is exposed to the air tends to cause oxidation of the Cu silicide layer during the deposition of the insulating film. In that case, it is necessary to optimize conditions such as lowering the deposition temperature of the insulating film, but this is not necessarily impossible unless continuous vacuum processing is used.

The second insulating film 2B is not necessarily made of TEOS +
It is not necessary to use a Si oxide film formed by the O ₂ plasma CVD method, and the plasma C using SiH ₄ + N ₂ O is used.
Si oxide film formed by VD method, PS formed by plasma CVD method using a source in which phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) is added to TEOS + O _2.
It may be a G film or a BPSG film. Further, an organic material such as polyimide having a small relative dielectric constant may be formed by a coating method, and this method is effective for reducing the interlayer capacitance.

In the semiconductor device manufactured in the first embodiment described above, the upper and lower sides and side walls of the Cu wiring prevent Cu oxidation,
The barrier films 3A and 3B and the Cu silicide layer 7 are effective for preventing the diffusion of u and improving the electromigration resistance and the stress migration resistance of Cu. Therefore, even when an insulating film such as a Si oxide film, which has a lower relative dielectric constant than the Si nitride film on the Cu wiring but may oxidize Cu during film formation, is not oxidized, Cu is not oxidized. The long-term reliability of wiring is improved.

In the manufacturing process, even if heat treatment is performed a plurality of times for multilayering the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated, so that a semiconductor device having high performance and high long-term reliability is provided. Can be manufactured with high controllability, uniformity and reproducibility and high yield.

The semiconductor device described above and the method of manufacturing the same
The present invention can be applied irrespective of the type of the semiconductor device such as the OS and the bipolar.

FIGS. 2A to 2D are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining a second embodiment of the present invention.

First, as shown in FIG.
A first insulating film 2A composed of an Si oxide film having a thickness of 500 to 1500 nm is formed thereon by plasma CVD which is a known method.
Then, the first insulating film 2A is etched by a reactive ion etching method using a photoresist film as a mask to form a wiring groove 8 having a depth of 300 to 800 nm. Next, a barrier film 3 composed of a TiN film is formed on the entire surface including the wiring groove 8 by a reactive sputtering method using a titanium target at a power of 2.5 to 5.0 kW and a pressure of 2 to 2.5 kW.
It is formed with a thickness of 25 to 100 nm under the condition of 10 mTorr.

Next, as shown in FIG.
Cu (HFA) (TMVS) (Copper He
xa Fluor Athethylacetona
teTri-Methyl Vinyl Silan
_{e, Cu (C 5 HF 6} O 2) (C 5 H 12 Si)) thick by Cu-CVD method using an organic source as a raw material 5
A Cu film 4 having a thickness of 100 to 1000 nm is formed so that the wiring groove 8 is filled with the barrier film 3 and the Cu film 4. Cu-C
The VD method uses a raw material source of 20 to 50 sccm and a carrier H _2.
When the gas is 50 to 200 sccm, the temperature is 150 to 250 ° C., and the pressure is 5.0 to 20.0 Pa, a Cu film having a smooth and high step coverage can be formed.

Next, a chemical mechanical polishing method (Chemical Mechanical) using a slurry containing alumina (Al ₂ O ₃ ) fine powder and hydrogen peroxide (H ₂ O ₂ ) as main components.
The Cu film 4 and the barrier film 3 exposed in portions other than the wiring trenches are polished by an alPolishing (hereinafter, CMP method).
After removal, a trench-filled Cu wiring composed of the barrier film 3 and the Cu film 4 is formed.

Next, as shown in FIG.
SiH ₄ gas is introduced into a vacuum chamber kept at a constant temperature of 00 to 400 ° C., SiH ₄ gas at a pressure of 50 to 500 Pa, or SiH ₄ gas 6 diluted with N ₂ or an inert gas such as Ar is introduced into the vacuum chamber, and a Si substrate 1 is exposed to a SiH ₄ gas 6 atmosphere. Then, the exposed Cu film 4 above the wiring is reacted with the SiH ₄ gas to form a Cu silicide layer 7 having a thickness of 10 to 20 nm.
It is formed only above the wiring. C formed on top of wiring
The composition and thickness of the u-silicide layer 7 are determined by the pressure, temperature, exposure time, temperature and partial pressure of the SiH ₄ gas, and can be formed by processing for about 1 minute.

For forming the silicide layer 7, in addition to SiH ₄ , disilane (Si) having a Si—H bond is also used.
₆ H ₆ ) and difluorsilane (SiH
₂ F ₂₎ or the like may be used. When Cu is silicided using a SiH ₄ gas diluted under a reduced pressure atmosphere,
The reaction rate of silicidation can be reduced. Therefore, a thin Cu silicide layer can be formed with high uniformity and controllability. In this step, C on the upper portion of the Cu wiring
If u is oxidized, it becomes difficult to react with SiH ₄ gas. Particularly in the CMP process, H _{2 having} strong oxidizing power is contained in the slurry.
Since O ₂ is contained, it is highly possible that the Cu surface on the wiring is oxidized. In that case, SiH
_{(4) If} hydrogen gas is introduced before the introduction and heated to about 400 ° C., Cu oxide can be reduced to Cu and the subsequent silicidation reaction can be promoted. This pretreatment may be performed in a vacuum chamber for introducing SiH ₄ gas, or may be performed in another vacuum chamber and then transferred to a vacuum chamber for introducing SiH ₄ gas without breaking vacuum. When a thin Cu silicide layer is formed on the upper part of the Cu wiring, the oxidation resistance of the exposed Cu portion of the wiring is greatly improved. However, since the Cu silicide layer is sufficiently thin, the wiring resistance hardly increases.

Next, as shown in FIG. 2D, on the Cu wiring,
The TEOS + O ₂ composed of Si oxide film by a plasma CVD method using a source second insulating film 2B 500 to 1
It is formed with a thickness of 000 nm. The type and deposition conditions of the second insulating film applicable in the second embodiment are the same as those in the first embodiment, and the PSG is not limited to the Si oxide film.
A film, a BPSG film, a polyimide, or the like is also applicable.

In the semiconductor device manufactured by the above method, the bottom and side walls of the trench-embedded Cu wiring are barrier films, and the wiring upper portion is C.
coated with u-silicide. Therefore, even when an insulating film such as a Si oxide film that may oxidize Cu is formed during film formation, Cu is not oxidized, and the long-term reliability of the Cu wiring is improved.

In the manufacturing process, even if heat treatment is performed a plurality of times in order to multilayer the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated. It can be manufactured with high controllability, uniformity and reproducibility and high yield.

The above-described semiconductor device and its manufacturing method can be applied irrespective of the type of semiconductor device, such as a MOS or bipolar device, as in the case of the first embodiment.

[0057]

As described above, according to the semiconductor device and the manufacturing method of the present invention, in the periphery of the wiring, the oxidation of Cu is prevented,
Of Cu wiring having a structure covered with a barrier film and a Cu silicide layer, which is effective in preventing diffusion of Cu and improving electromigration resistance and stress migration resistance of Cu, is highly controlled, highly uniform, and highly reproducible. Can be formed with.

For this reason, even when an insulating film such as a Si oxide film having a lower dielectric constant than the Si nitride film but having a possibility of oxidizing Cu is formed on the Cu wiring, the Cu film may be formed.
Is not oxidized, and the long-term reliability of the Cu wiring is improved.
Furthermore, even when heat treatment is performed a plurality of times for multilayering the Cu wiring, the characteristics of the wiring and the insulating film are not deteriorated, so that a semiconductor device having high performance and high long-term reliability can be manufactured at a high yield. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor chip for explaining a first conventional example.

FIG. 4 is a sectional view of a semiconductor chip for explaining a second conventional example.

FIG. 5 is a sectional view of a semiconductor chip for explaining a third conventional example.

FIG. 6 is a sectional view of a semiconductor chip for explaining a fourth conventional example.

[Explanation of symbols]

 1,11 Si substrate 2A First insulating film 2B Second insulating film 3A, 3B Barrier film 4 Cu film 4A Cu-Si alloy film 5 Mask 6 Silane gas 7 Cu silicide layer 8 Groove 12A, 12B Si nitride film 13A, 13B Barrier film 14 First insulating film 15 Plasma TEOS oxide film 16 Si oxide film

Claims (10)

[Claims] 1. A first insulating film provided on a semiconductor substrate, a first conductive film and a second conductive film sequentially provided on the first insulating film, and copper silicon provided on side surfaces of the copper film. A semiconductor device comprising: a wiring composed of a compound layer; and a second insulating film provided on the first insulating film and the wiring. 2. A first insulating film provided on a semiconductor substrate, a wiring groove formed in the first insulating film, a copper film provided in the wiring groove, and a bottom portion and a sidewall portion of the copper film. A wiring composed of a first conductive film provided on the surface and a copper silicon compound layer provided on the surface of the copper film, and a second insulating film provided on the first insulating film and the wiring. A semiconductor device characterized by: 3. A step of forming a first insulating film on a semiconductor substrate, a step of sequentially forming a first conductive film, a copper film and a second conductive film on the first insulating film, and the second conductive film. And a step of patterning the copper film and the first conductive film to form a wiring, a step of forming a copper silicon compound on the exposed copper film surface of the side wall portion of the wiring, and a step of forming a wiring on the first insulating film and the wiring. And a step of forming a second insulating film. 4. A step of forming a first insulating film on a semiconductor substrate, a step of forming a wiring groove in the first insulating film, and a step of sequentially forming a first conductive film and a copper film over the entire surface including the wiring groove. The step of filling the wiring groove, the step of removing the first conductive film and the copper film outside the wiring groove to form a wiring composed of the first conductive film and the copper film, and the wiring upper portion. And a step of forming a second insulating film over the entire surface including the surface of the copper silicon compound layer, and a method of manufacturing a semiconductor device. 5. The first conductive film comprises titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr),
Niobium (Nb), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W),
A single layer film composed of these silicides, borides, nitrides, carbides and alloys containing them.
Alternatively, the semiconductor device according to claim 2. 6. The semiconductor device according to claim 1, wherein the first conductive film is a two-layer film composed of Ti and a nitrogen compound of Ti or a boron compound of Ti and Ti. 7. The second conductive film comprises titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr),
Niobium (Nb), molybdenum (Mo), hafnium (H
The semiconductor device according to claim 1, wherein the semiconductor device is a single-layer film composed of f), tantalum (Ta), tungsten (W), and their silicides, borides, nitrides, carbides and alloys containing them. 8. The semiconductor device according to claim 1, wherein the second conductive film is a two-layer film composed of Ti and a nitrogen compound of Ti or a boron compound of Ti and Ti. 9. The method of manufacturing a semiconductor device according to claim 3, wherein the copper silicon compound is formed by a reaction of copper and a gas containing silicon. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the gas containing silicon is monosilane or disilane.