JPH08264534A - Formation of interconnection - Google Patents

Abstract

PURPOSE: To obtain a method for forming a flat interconnection embedded in an insulation layer by polishing while suppressing contamination with metal. CONSTITUTION: SOG is deposited, as an insulation layer 3, on a substrate 1 having irregularities and a metal layer 4 is deposited thereon while filling recesses 5a, 5b formed in the surface of the insulation layer 3. The metal layer 4 is then removed selectively by polishing using the insulation layer 3 as a stopper thus forming an interconnection buried in the recesses 5a, 5b. Finally, the insulation layer 3 is polished selectively thus planarizing the upper surface thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a buried wiring formed by polishing, and more particularly to a method of forming a buried wiring of a semiconductor device.

To form a buried wiring, a groove-shaped, hole-shaped, or plate-shaped depression is formed in an insulating layer deposited on a substrate, and a metal layer filling the depression is deposited on the entire surface of the substrate and then polished. As a result, a CMP (Chemical Mechanical Polishing) method is employed in which the metal embedded in the depression is left as a wiring and the metal deposited on the upper surface of the insulating layer other than that is removed to form a wiring.

The surface of the substrate on which the embedded wiring is formed needs to be flatly polished in order to form a multi-layered wiring thereon. Further, in order to avoid the deterioration of the quality of the semiconductor device due to the contamination, it is desirable that the metal contamination on the surface after polishing is small.

Therefore, there is a need for a method of forming a buried wiring with less metal contamination and a method of forming a buried wiring with a method of flattening the surface and less metal contamination.

[0005]

2. Description of the Related Art A conventional method for forming a buried wiring embedded in an insulating layer with a flat surface is a polishing agent that selectively polishes a wiring material by using the insulating layer as a polishing stopper (hereinafter referred to as " It was made by polishing with a metal abrasive. Hereinafter, a conventional method for forming a buried wiring will be described along with a conventional example.

FIG. 5 is a cross-sectional process diagram of a conventional first embodiment, showing a process of forming wirings connected to MOS transistors. Referring to FIG. 5A, first, a field oxide film 2 that defines an element formation region is formed on the surface of the semiconductor substrate 1 by using LOCOS. Next, the gate electrode 7 and the source / drain regions are formed in the element forming region by a known method, and the insulating layer 3 made of SiO ₂ is deposited on the entire surface of the substrate 1 by the CVD method.

Next, referring to FIG. 5B, the insulating layer 3
Polish the top surface flat. Next, by using photolithography, a via hole 5a that opens on the upper surface of the gate electrode 7 and a contact hole 5b that opens on the source or drain region, respectively, are formed to form the recess 5 that defines the wiring. Next, the metal layer 4 that fills the depression 5 is deposited on the substrate 1 by using the CVD method.

Next, referring to FIG. 5C, the metal layer 4
Is polished with a metal polishing agent to remove the metal layer 4 deposited on the upper surface of the insulating layer 3. At this time, the insulating layer 3 functions as a polishing stopper, and as a result, the metal embedded in the recess 5 is left as it is and the embedded wiring 8, for example, the via 8a,
Contact wiring 8b is formed.

However, in the metal layer 4 embedded in the recess 5, referring to FIG. 5B, a region 6 having a different metal composition or structure extending inward from the surface center of the recess (hereinafter referred to as a "nest") is formed. .) Occurs. The cavities 6 are easily polished and corroded by the metal polishing agent, and as a result, the wiring 8 formed by the above method has a recess on the surface thereof as shown in FIG. 5C. Therefore, the reliability of the wiring 8 deteriorates.

Further, when a metal polishing agent for selectively polishing metal is used, the surface of the insulating film after the metal layer is removed is contaminated with the metal. Such contamination significantly deteriorates the reliability of the semiconductor device.

A second conventional method of forming a buried wiring in an insulating film on a substrate using polishing is polishing in which a metal as a material of the buried wiring and an insulating layer are simultaneously polished, that is, at the same polishing rate. It is a method using an agent. Next, Japanese Patent Fair 6-8
This method will be described based on the contents disclosed in 2660.

FIG. 6 is a sectional process view of a conventional second embodiment, which shows a process of forming wiring on a MOS transistor. Referring to FIG. 6A, a MOS transistor having a gate electrode 7 is formed in the transistor formation region defined by the field oxide film 2 on the substrate 1. Then, an insulating film 3 having a uniform thickness is deposited on the entire surface of the substrate 1, and a via hole 5a and a contact hole 5b which are opened in the upper surface of the gate electrode 7 and the source or drain region are formed in the insulating film 3. Then, the via hole and the contact hole are buried, and the metal layer 4 is deposited on the entire surface of the substrate.

Then, the insulating film 3 and the metal layer 4 are polished under the same polishing rate, and the metal layer 4 filling the via holes 5a and the contact holes 5b is left, and the other metal layers 4 are removed. As a result, referring to FIG. 6B, a via 8a connected to the gate electrode 7 and a contact wiring 8b connected to the source and drain are formed.

Since this polishing polishes the insulating film 3 and the metal layer 4 at the same speed, the polished surface should be polished flat regardless of the shape before polishing. However, the polishing rate is
Temperature, polishing pressure, condition of polishing cloth, composition of polishing agent or P
It is not easy to polish the insulating layer 3 and the metal layer 4 at the same speed, because they change slightly depending on the conditions such as H. Also,
An abrasive having a considerable polishing rate for the metal layer 4 generally easily contaminates the polished surface of the insulating film 3 with metal. Furthermore, the cavities 6 are likely to be polished or corroded to form depressions on the surface of the wiring 8.

Another problem in using the conventional method of selectively polishing the metal layer occurs when the wiring density is rough. FIG. 7 is a process diagram of the end surface of the third example of the related art, showing the cross-sectional shape of the wiring when the wiring density varies.

With reference to FIG. 7A, a silicon nitride thin film is deposited as an etch stopper 10 on the substrate 1, and a silicon oxide film is flatly deposited thereon as an insulating layer 3 by the CVD method. Then, by photo-etching, the recess 5 defining the wiring 8 is opened in the insulating layer 3 by using the etch stopper 10 as a stopper for etching. Then,
A metal layer 4 that fills the depression 5 is deposited on the entire surface of the substrate 1.
Then, the metal layer 4 is polished flat with a metal abrasive,
Referring to FIG. 7B, the metal layer 4 on the insulating layer 3 is removed to form the buried wiring 8.

In this method, the oxide film 2 which functions as a polishing stopper is polished and thinned in the dense wiring region 11 where the wiring 8 is densely arranged, while the rough wiring in which the wiring 8 is roughly arranged. The region 12 is not so much polished and remains thick. As a result, a concave portion 11a is formed on the polished surface of the dense wiring region 11.
Usually, in multi-layer wiring of a semiconductor device, dense wiring regions are often arranged so as to overlap each other. In such a case, referring to FIG. 7C, since the surface of the dense wiring region 11 formed in the upper insulating layer 31 with the interlayer insulating film 13 interposed therebetween overlaps with the lower concave portion, a deep concave portion 11a is formed. To do. Therefore, it becomes difficult to form the multilayer wiring.

[0018]

As described above, in the conventional method of forming a buried wiring in which a metal layer is removed by using a metal abrasive that selectively polishes the metal layer, the holes in the metal layer are polished or Since it is corroded to form a recess on the surface of the buried wiring, there are problems that it is difficult to flatten and the reliability of the wiring is poor. There is also a problem that the polished surface is contaminated with metal. In addition, there is a problem that the thickness of the wiring and the insulating layer in the region where the wiring density is high becomes thin and it is difficult to flatten the surface.

In the present invention, the insulating layer is formed of spin-coated glass (hereinafter referred to as "SOG"), the metal layer on the insulating layer is removed by using a metal abrasive, and then the insulating layer is selectively polished. It is intended to provide a method for forming a buried wiring which is flat and has a flat polished surface with less metal contamination. Further, by inserting a finishing polishing process for the insulating layer after removing the metal layer, metal contamination is reduced. further,
By providing a dummy embedded wiring in the area where the wiring density is low, it is possible to prevent the polishing amount from varying due to the density of the wiring.
A method for forming a flat wiring is provided.

[0020]

FIG. 1 is a sectional process drawing of a first embodiment of the present invention, which shows a process of forming a buried wiring on a substrate on which a field oxide film is formed.

FIG. 2 is a sectional process drawing of the second embodiment of the present invention, showing a wiring forming process of a semiconductor device when the wiring density is rough. The first configuration of the present invention for solving the above-mentioned problems is, with reference to FIG. 1, a step of forming a recess 5 defining a wiring 8 in an insulating layer 3 provided on a substrate 1, A step of depositing the metal layer 4 by embedding the recess 5 on the layer 3; and a part of the metal layer 4 embedded in the recess 5 as the wiring 8 and the metal layer deposited on the insulating layer 3. In the wiring forming method, the insulating layer 3 includes a spin-coated glass (SOG) layer, and the polishing step uses the insulating layer 3 as a stopper to selectively select the metal layer 4. And a metal polishing step of exposing the upper surface of the insulating layer 3 to expose the upper surface of the insulating layer 3 and a flattening polishing step of selectively polishing the insulating layer 3 to flatten the upper surface of the insulating layer 3. In the second configuration, the wiring 8 is formed on the insulating layer 3 provided on the substrate 1. To form the recess 5 and to deposit the recess 5 on the insulating layer 3 to deposit the metal layer 4, and to leave the portion of the metal layer 4 embedded in the recess 5 as the wiring 8. In the wiring forming method, which includes a polishing step of removing the metal layer 4 deposited on the insulating layer 3, the polishing step selectively removes the metal layer 4 using the insulating layer 3 as a stopper, It is characterized in that it has a metal polishing step of exposing the upper surface of the insulating layer 3 and then a final polishing step of selectively polishing the insulating layer 3, and the third configuration is shown in FIG. And then board 1
Forming a recess 5 for defining a wiring 8 in the insulating layer 3 provided thereon; depositing the recess 5 on the insulating layer 3 and depositing a metal layer 4; and forming the recess 5 in the metal layer 4. A wiring step of removing the metal layer 4 deposited on the insulating layer 3 while leaving the portion buried in the wiring 8 as the wiring 8; A dummy wiring 9 formed simultaneously with the wiring 8 by a polishing process for removing the metal layer 4 is provided in a region where the metal layer 4 is roughly arranged, and a fourth configuration is In the wiring forming method having the first to third configurations, the insulating layer 3 is made of silicon oxide, and the metal layer 4 is made of tungsten.

[0022]

In the first structure of the present invention, as shown in FIGS.
First, the metal layer 4 deposited on the insulating layer 3 is removed by polishing with an abrasive that selectively removes the metal layer 4 (hereinafter referred to as “metal layer removing step”), and the insulating layer The metal layer 4 embedded in the recess 5 of 3 is left as a wiring. As a result of the selective removal of the metal layer 4 by this polishing, the surface of the insulating layer 3 exposed on the polished surface retains the surface shape of the insulating layer 3 at the time of deposition.

As is well known, such selective polishing is performed by using, for example, a polishing agent having a polishing rate of the metal layer 4 higher than that of the insulating layer 3, that is, polishing using the above-mentioned metal polishing agent. You can do it. In the present specification, the “wiring” is a metal wiring, and includes a linear conductive wire for connecting elements, a contact hole, and a plate-shaped wire. The "dummy wiring" is made of the same material as the "wiring" and has the same shape as the "wiring" such as a wire, a hole, or a plate, and is not electrically connected to any other.

In the first configuration, the insulating layer 3 is SOG or S.
It is composed of layers including an OG layer. Therefore, as shown in FIG.
Referring to (b), the unevenness on the surface of the substrate 1 is relaxed, and CV
Compared with the oxide film deposited by the D method, the surface of the insulating layer 3 is made extremely flat although slight unevenness remains. In this configuration, subsequently, a planarizing polishing for polishing the insulating layer 3 is performed using an abrasive for selectively polishing the insulating layer 3 (hereinafter referred to as “insulating layer polishing agent”). By polishing the insulating layer 3,
The slight unevenness on the surface of the insulating layer 3 which is flattened by SOG is removed, and the surface is more completely flattened.

In this structure, immediately after the metal layer removing step, a recess is formed on the surface of the metal layer 4 embedded in the recess 5 due to the cavities 6, and this recess is removed by the subsequent flattening polishing. . In the flattening polishing using the insulating layer polishing agent, the polishing and corrosion of the cavities 6 are almost negligible.
Therefore, in this configuration, the insulating layer 3 and the upper surface of the wiring 8 are in the same plane, and an extremely flat polished surface without the depression of the upper surface of the wiring 8 is realized.

In the second structure of the present invention, after the metal layer removing step, finish polishing using an insulating layer polishing agent is performed. In addition,
Final polishing is polishing performed in the final step of polishing,
This refers to short-time polishing performed under a light polishing pressure or by changing the polishing agent or changing the polishing pressure and the polishing agent as compared with normal polishing. The change in the shape of the polishing surface and the increase in the polishing amount in such final polishing are usually negligible. The inventor of the present invention has revealed that finish polishing reduces metal contamination on the polished surface. Below, this experiment and its results are explained.

In this experiment, referring to FIG. 2, the wiring 8 and the dummy wiring were formed on the substrate 1, and the surface immediately after polishing was cleaned with a scrubber and then with a 0.5% hydrofluoric acid aqueous solution. Next, the surface layers of the insulating layer 3, the wiring 8 and the dummy wiring 9 deposited on the substrate 1 are exposed to fluorinated nitric acid vapor and dissolved,
The solution was treated with IPC-MS (Inductively Coupled Plasma).
Mass Spectrometry).

After the metal layer removing step with the metal polishing agent,
When finish polishing is performed for 0.5 minutes using an insulating layer polishing agent, Na is 2.2 × 10 ¹⁰ atoms / cm ² , and K is 1.6 × 10 ¹⁰
atoms / cm ² or less, Ca 1.2 × 10 ¹⁰ atoms / cm ² , Al
Is 25 × 10 ¹⁰ atoms / cm ² and Fe is 1.1 × 10 ¹⁰ atoms / cm ^2.
It was cm ² . On the other hand, immediately after the metal layer removing step using the metal polishing agent, Na was 2.1 × 10 ¹⁰ atoms / cm ² and K was 1.
6 × 10 ¹⁰ atoms / cm ² or less, Ca 2.8 × 10 ¹⁰ atoms / cm 2
² , Al 1020 × 10 ¹⁰ atoms / cm ² and Fe 11 ×
It was 10 ¹⁰ atoms / cm ² . This means that Al and Fe contaminations by finish polishing are about 1/20 and 1/10, respectively.
It has been revealed that it has decreased to. The polishing pressure for finish polishing is preferably a light load, but a pressure with which the polishing cloth uniformly contacts the entire surface of the substrate 1 is required.

Further, an oxide film serving as an insulating layer is formed on the substrate by C
A sample was prepared by depositing by a VD method, depositing a titanium nitride layer having a thickness of 50 nm on the insulating layer, and then depositing a tungsten layer having a thickness of 400 nm as a metal layer. The metal layer and the titanium nitride layer were removed by the same process as the metal layer removing process of the first experiment. After that, a sample which was further subjected to final polishing for 0.5 minutes and a sample which was overpolished by continuing the metal layer removing step for 0.5 minutes were prepared. After the surfaces of these two samples were washed with 0.5% hydrofluoric acid aqueous solution, the diameter of 0.3 μm present on the polished surface of each sample
The number of dusts above was measured.

The number of dust particles on the polishing surface after the final polishing was 12 on the wafer having a diameter of 6 inches, and the number of dust particles on the polishing surface after the overpolishing was the metal layer removing step was 1302. That is, the number of dust is 1/100 of the conventional
Has been reduced to.

As described above, in the second configuration of the present invention,
Since the final polishing is performed using the insulating layer polishing agent after the metal layer removing step, the number of dust particles on the polishing surface is reduced. Also, there is little metal contamination on the polished surface.

In the third structure of the present invention, referring to FIG. 2, dummy wiring 9 is formed separately from wiring 8 in rough wiring region 12 on substrate 1. This dummy wiring is used in the rough wiring area 12
In the dense wiring region 11, the wirings 8 and the dummy wirings 9 are formed so that the occupied areas are substantially equal. Therefore, by simultaneously forming the wiring 8 and the dummy wiring 9 in the metal layer removing step, it is possible to avoid thinning of the insulating film 3 and the wiring 8 in the dense wiring region 11.

The dummy wiring 9 and the wiring 8 may be formed in the same metal removing step, and the preceding step, for example, the step of forming a dent, need not be the same. Moreover, the shape, for example, the planar shape or the cross-sectional shape may be different. Furthermore, in the present invention, the recess 5 does not necessarily have to penetrate the insulating layer 3, and the bottom surface of the recess 5 may be inside the insulating layer 3.

[0034]

EXAMPLES The present invention will be described in detail below with reference to examples. The first embodiment of the present invention relates to the formation of transistor vias and contact wirings in the manufacture of semiconductor devices.

Referring to FIG. 1, referring to FIG.
A field oxide film 2 of LOCOS was formed on a partial region of the surface of the silicon substrate 1, and then a transistor having a gate electrode 7 was formed. After that, a silicon oxide film formed of SOG was deposited on the entire surface to form an insulating layer 3.

Next, by using reactive ion etching, the insulating layer 3 on the gate electrode 7 and the drain region is formed,
A via hole 5a and a contact hole 5b were opened.
The via hole 5a and the contact hole 5b are a kind of the recess 5 provided in the insulating layer 3.

Next, tungsten was deposited on the entire surface by the CVD method to form the metal layer 4. This metal layer 4 has a nest 6 at the center of each hole 5a, 5b. Then,
Referring to FIG. 1B, the metal layer 4 is removed using a metal layer polishing agent.

As the metal polishing agent, a trade name XGB5518 in which abrasive grains containing α-alumina as a main component and an additive containing potassium phthalate as a main component are added, and hydrogen peroxide solution are mixed at a ratio of 1: 1.
A non-woven fabric, trade name SUBA400, was used as the polishing cloth. When the polishing pressure is 350 g / cm ² , the polishing rate ratio between the insulating layer 3 and the metal layer 4 is 1: 2.
0, the polishing rate of the metal layer 4 was about 100 nm / min, and the metal layer 4 having a thickness of 400 nm deposited on the upper surface of the insulating layer 3 was substantially removed by polishing for 4 minutes. At this time, a recess due to the nest 6 was formed on the surface of the metal layer remaining in the via hole 5a and the contact hole 5b.

Then, referring to FIG. 1C, the surface of the insulating layer 3 was flattened by flattening polishing using an insulating layer polishing agent. In the flattening polishing process, the product name SC112, which is an abrasive containing fumed silica as the main component, and an additive containing potassium hydroxide as the main component, is used. Polishing was performed for 0.5 minutes at a polishing pressure of 300 g / cm ² using IC1000.

In this example, a flat buried wiring can be easily formed. In addition, a clean surface with little metal contamination on the surface can be easily realized. The second embodiment of the present invention relates to a wiring formed on a semiconductor substrate.

Referring to FIG. 2A, an etch stopper 10 made of a silicon nitride thin film is deposited on the semiconductor substrate 1, and a silicon oxide film is deposited on the etch stopper 10 to form an insulating layer 3. Next, a groove 5c that defines the wiring 8 and a groove 5d that defines the dummy wiring 9 are formed in the insulating layer 3.

The wirings 8 are arranged at a high density in the dense wiring area 11 and at a low density in the rough wiring area 12. The dummy wirings 9 are provided in the rough wiring region so that the wiring densities on the entire surface of the substrate are equal. After that, a metal layer removing process and a flattening polishing process are performed under the same conditions as in the first embodiment, and then, as shown in FIG.
With reference to FIG. In this embodiment, the surface of the insulating layer is polished flat even if the wiring has a coarse and dense distribution.

FIG. 3 is a perspective view of a second embodiment of the present invention,
This shows a part of the grooves 5c and 5d formed in the insulating layer 3. With reference to FIG. 3A, the grooves 5c that define the wirings 8 are arranged in parallel lines, and the grooves 5d that define the dummy wirings 9 extending in parallel to the wirings 9 are formed on substantially the entire surface of the rough wiring region 12. Is provided. Further, referring to FIG. 3B, the rough wiring area 1
It is also possible to provide a groove 5d defining the hole-shaped dummy wiring 9 on substantially the entire surface of 2. The use of the hole-shaped dummy wiring 9 is excellent in that, when the dummy wiring 9 comes into contact with the adjacent wiring 8 or the wirings arranged above and below, there is less risk of electrical short circuit with other wiring. Further, the wiring density can be increased with the linear dummy wiring.

FIG. 4 is a sectional process drawing of the third embodiment of the present invention, showing a section of a semiconductor device having multi-layer wiring.
Referring to FIG. 4A, a field oxide film 2 defining a MOS transistor formation region is formed on the surface of the silicon substrate. Then, a gate electrode having a side wall 7 is formed in the transistor formation region, and source and drain regions are formed by ion implantation. Then, after SOG is formed on the entire surface of the substrate, the wiring 8 embedded in the insulating layer 3 made of SOG having a flat upper surface, for example, the gate electrode 7 is connected by the same method as in the first embodiment of the present invention. Via 8a,
Contact wiring 8b for ohmic connection to the drain region
Also, a wiring 8c connecting the gate electrode 7 and the source region is formed. The wiring 8 is tungsten deposited by the CVD method.

Next, referring to FIG. 4B, a silicon nitride etch stopper 10 and a second insulating layer 3 made of a silicon oxide film are sequentially deposited on the entire surface of the substrate. Next, the wiring 8 and the dummy wiring 9 are formed on the insulating layer 3 by reactive ion etching using the etch stopper 10 as a stopper.
To form a depression that defines Further, the etch stopper 10 exposed at the bottom of the depression is removed by etching, and the surface of the lower insulating layer 3 and the via 8a, contact wiring 8b, and wiring 8c are exposed at the bottom of the depression.

Then, after depositing tungsten as a metal layer by the CVD method, the metal layer is removed by polishing, and finally, touch polishing for polishing with a minimum load is carried out for 10 seconds to complete polishing. This polishing step was performed under the same conditions as in the second embodiment of the present invention. As a result, the second layer wiring 8 and the dummy wiring 9 are formed.

Next, referring to FIG. 4C, an etch stopper 10 and an interlayer insulating film 13 are sequentially deposited on the entire surface of the substrate, and a via 8a for connecting to the second layer wiring 8 is used as a third layer wiring. Form. The via a is formed by the same method as the second layer wiring.

Next, a fourth layer wiring is formed on the interlayer insulating film 13 in the same manner as the second layer wiring. Further, a semiconductor device having a multi-layer wiring is manufactured through a normal semiconductor device manufacturing process.

[0049]

According to the present invention, it is possible to provide a wiring forming method for easily forming a buried wiring which is flat and has less metal contamination even if the surface of the substrate is uneven by polishing. Further, it is possible to provide a wiring forming method in which the metal contamination and the dust on the surface of the insulating layer on which the embedded wiring is formed by polishing with the metal polishing agent is reduced. Further, it is possible to provide a wiring forming method for forming a wiring having a flat surface regardless of the density of the wiring. Therefore, it greatly contributes to the performance improvement of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional process drawing of a first embodiment of the present invention.

FIG. 2 is a sectional process drawing of a second embodiment of the present invention.

FIG. 3 is a perspective view of a second embodiment of the present invention.

FIG. 4 is a sectional process drawing of a third embodiment of the present invention.

FIG. 5 is a sectional process diagram of a conventional first embodiment.

FIG. 6 is a sectional process diagram of a conventional second embodiment.

FIG. 7 is a sectional process diagram of a conventional third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Field oxide film 3,31 Insulating layer 4 Metal layer 5, 5a to 5d Recess 6 Nest 7 Gate electrode 8, 8a, 8b, 8c Wiring 9 Recess 10 Etch stopper 11 Dense wiring area 12 Rough wiring area 13 Interlayer insulation film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukihiro Sato 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kenichi Inoue, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Akitaka Erasawa, 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited (72) Inventor Yoshiyuki Okura, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited (72) Inventor, Akio Ito Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Fukuoka Prefecture Fujitsu Limited (72) Watanabe Nakamura 1015 Ueodaanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Kanagawa Prefecture (72) Inventor Akira Oishi 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Address within Fujitsu Limited

Claims (4)

[Claims] 1. A step of forming a recess for defining a wiring in an insulating layer provided on a substrate, a step of filling the recess on the insulating layer and depositing a metal layer, and a step of filling the recess of the metal layer. And a polishing step of removing the metal layer deposited on the insulating layer while leaving the exposed portion as the wiring, the insulating layer including a spin-coated glass (SOG) layer, and the polishing step. The step is a metal polishing step of selectively removing the metal layer by using the insulating layer as a stopper to expose the upper surface of the insulating layer, and then selectively polishing the insulating layer to remove the upper surface of the insulating layer. And a flattening / polishing step of flattening. 2. A step of forming a recess for defining a wiring in an insulating layer provided on a substrate, a step of filling the recess on the insulating layer and depositing a metal layer, and a step of filling the recess in the metal layer. A polishing step of removing the metal layer deposited on the insulating layer while leaving the exposed portion as the wiring, and the polishing step selectively uses the metal layer as a stopper in the polishing step. A method of forming a wiring, comprising: a metal polishing step of removing the insulating layer to expose the upper surface of the insulating layer; and a final polishing step of selectively polishing the insulating layer. 3. A step of forming a recess that defines a wiring in an insulating layer provided on a substrate, a step of depositing a metal layer that fills the recess on the insulating layer, and a step of depositing a metal layer in the recess of the metal layer. A wiring forming method comprising a polishing step of removing the metal layer deposited on the insulating layer while leaving the embedded portion as the wiring, wherein the wiring is roughly arranged in the region on the insulating layer. A dummy wiring formed simultaneously with the wiring by a polishing process for removing the metal layer in the formed region. 4. The wiring forming method according to claim 1, 2 or 3, wherein the insulating layer is made of silicon oxide and the metal layer is made of tungsten.