JPH08263449A - System for parallel communication between arithmetic processors - Google Patents

Abstract

PURPOSE: To suppress the waiting time of data exhcnage at a minimum by preparing the sets of arithmetic processors, which enable simultaneous communication, corresponding to the numerical values of respective digits when a positive integer smaller than the number of arithmetic processors is expressed by a binary number system. CONSTITUTION: In the items of columns in the figure, identification numbers N of arithmetic processors 2-0, 2-1...2-7 are defined as 0, 1...7 and displayed in parentheses as the binary numbers of three digits. In the respective items of rows, values (from 1 to 8) smaller than the total number '8' of arithmetic processors are allocated as any arbitrary number (m) and displayed in parentheses as the binary numbers of three digits similarly to the identification numbers. When the arbitrary number (m) is chosen to be '3', in this case, a binary numerical value M is generated for each arithmetic processor by inverting the numerical values of first and second digits among the respective binary displayed identification numbers N of arithmetic processors corresponding to the row of m=3, it is possible to generate sets of arithmetic processors that can be executed simultaneously by taking the value of M as the identification number of arithmetic processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit for calculating matrix data when a large-scale matrix calculation in designing a large-scale facility such as a nuclear facility is required at a considerable frequency. Of parallel communication system.

[0002]

2. Description of the Related Art As described above, in designing large-scale facilities such as nuclear facilities, large-scale matrix calculations such as radiation behavior calculation for shielding design and core performance prediction analysis for core design are required. It is required quite often, and therefore it is required to increase the efficiency of the matrix calculation.

Recently, in order to improve the efficiency of matrix calculation,
By using a large number of arithmetic processing units each having a communication means and a storage unit and performing a matrix calculation on a large number of arithmetic processing units in parallel, it is possible to obtain a high level which cannot be obtained by a computer having only one arithmetic processing unit. It has been devised to perform speed calculations.

For example, in the case of core design, the core of a nuclear reactor is divided into several segments composed of a plurality of fuel assemblies, and each segment is associated with one arithmetic processing unit to calculate the output and the thermal-hydraulics. And are calculated in parallel in each arithmetic processing unit. When analyzing various data between segments, for example, neutron flux inflow and outflow and pressure balance of coolant between channels, data of neutron flux at segment boundaries and pressure loss of each channel are transferred between processing units by communication means. Interact with each other to perform spatially continuous analysis.

In addition, for example, in the case of a shield design, the entire system including the reactor core, coolant, shield, etc. is divided into several small areas, and each small area is associated with one arithmetic processing unit. Then, the radiation distribution calculation is performed in parallel by each arithmetic processing unit. When analyzing the inflow and outflow of the neutron flux between the small regions, spatially continuous analysis is performed by exchanging data of the neutron flux at the boundary of the small region between the arithmetic processing devices by the communication means.

FIG. 4 is a block diagram showing an example of the configuration of an apparatus including an arithmetic processing unit for performing such processing.

As shown, one host computer 1
H and eight arithmetic processing units 2-0 to 2-7. The host computer 1H has a host storage device 3H and host communication means 4H, and each of the arithmetic processing devices 2-0 to 2-7 has individual storage devices 5-0 to 5-7 and individual communication means 6-.
0-6-7 are provided, and the host communication means 4H and the individual storage devices 6-0-6-7 are connected to each other.

The matrix data read into the host computer 1H is divided into the respective arithmetic processing units 2-0 to 2-7,
It is transmitted to each arithmetic processing unit 2-0 to 2-7 via the communication unit 4H and each individual communication unit 4-0 to 4-7. The arithmetic processing devices 2-0 to 2-7 calculate the input divided matrix elements, transmit the arithmetic result to another arithmetic processing device as necessary, and perform arithmetic in another arithmetic processing device. Receive the results. Each of the individual storage devices 5-0 to 5-7 stores the operation result of its own operation processing device, and also receives and stores the operation result of another operation processing device via the individual communication means.

[0009]

However, even if a plurality of arithmetic processing units are used to perform the computations in parallel, the computations are not performed independently of each other without performing communication between the arithmetic processing units. It is rare to be able to proceed, and normally the calculation is performed while communicating between the processing units. For example,
Consider a case where the matrix A of 4 rows and 4 columns is multiplied by four arithmetic processing units to obtain the matrix C of 4 rows and 4 columns. A,
The elements of B and C are represented as a _ij , b _ij , and c _ij , respectively, as follows.

[0010]

[Equation 1] In one of the four processing units,

[0011]

[Equation 2] The calculation is performed as follows.

As is clear from this example, for each matrix element (element a _ij or element b _ij ) used in the calculation, element data for the entire row or column is required. The element c _ij obtained as a result of the calculation can obtain data only partially in each calculation processing device. This means that, for example, when it is necessary to multiply the matrix C and the matrix A in the next step, the data will be insufficient with only the elements obtained by the calculation. Therefore, A × B =
After carrying out the calculation of C, the rest of the matrix C in the above equation must be filled with at least the data of the first and second rows and the data of the first and second columns. I won't.

The generalization of these problems is as follows. There is a matrix X (nk), which is divided into n arithmetic processing units. For example, in the arithmetic processing unit with the identification number 1, X (nk)
(1), X (2), ... X (k) are X (k + 1), X (k + 2), ... X (2k) in the arithmetic processing unit with the identification number 2.
Suppose you have the calculation result of. By performing communication between the n arithmetic processing devices from this state, an operation may be required to create a situation in which the n arithmetic processing devices have the calculation result of the matrix X (nk).

At this time, it is a condition on the communication means that the communication is one-to-one communication. For example, when transferring data from the arithmetic processing device 1 to the arithmetic processing device 2, the arithmetic processing device 2
Must be in a position to receive data from the arithmetic processing unit 1. At this time, the arithmetic processing unit 2 will try to transfer data to another processing, for example, the arithmetic processing unit 3 or receive data from the arithmetic processing unit 4. If so, communication will fail and calculation will be interrupted. In order for communication to be performed smoothly, it is necessary to predetermine the order of communication so that there is no confusion between the transmitting side and the receiving side.

Taking the case of using four arithmetic processing units as an example, the following three methods (1) to (3) can be easily considered. (1) Method of sequentially performing transmission and reception one by one (a) The calculation result of the arithmetic processing device 1 is transmitted to the arithmetic processing device 2 (hereinafter, described as the arithmetic processing device 1 → the arithmetic processing device 2). (B) Arithmetic processing unit 1 → Arithmetic processing unit 3 (c) Arithmetic processing unit 1 → Arithmetic processing unit 4 (d) Arithmetic processing unit 2 → Arithmetic processing unit 1 (e) Arithmetic processing unit 2 → Arithmetic processing unit 3 (f ) Arithmetic processing unit 2 → Arithmetic processing unit 4 (g) Arithmetic processing unit 3 → Arithmetic processing unit 1 (h) Arithmetic processing unit 3 → Arithmetic processing unit 2 (i) Arithmetic processing unit 3 → Arithmetic processing unit 4 (j) Arithmetic Processing device 4 → arithmetic processing device 1 (k) arithmetic processing device 4 → arithmetic processing device 2 (l) arithmetic processing device 4 → arithmetic processing device 3 is sequentially executed.

Here, (a), (b), (c), ... Show the order of processing steps, that is, the time series. This method consists of 12 steps. This method takes time,
Communication disruptions are a sure way to be avoided. (2) A method of collecting data in a predetermined representative arithmetic processing device and then distributing the data to each arithmetic processing device. (I) Collect data in the representative arithmetic processing unit 1. (A) Arithmetic processing unit 2 → Arithmetic processing unit 1 (b) Arithmetic processing unit 3 → Arithmetic processing unit 1 (c) Arithmetic processing unit 4 → Arithmetic processing unit 1 When the above is sequentially executed, all the data is stored in the representative arithmetic processing unit 1. Get together. (Ii) All data is distributed from the representative arithmetic processing unit 1. (D) Arithmetic processing unit 1 → Arithmetic processing unit 2 (e) Arithmetic processing unit 1 → Arithmetic processing unit 3 (f) Arithmetic processing unit 1 → Arithmetic processing unit 4 is sequentially executed, and the entire matrix is arithmetic processing unit 2 and arithmetic processing. The data is transmitted to the processing device 3 and the arithmetic processing device 4.

The method (2) has a smaller number of steps than the method (1), but the amount of data transmitted in steps (d) to (f) is large (4 in steps (a) to (c)). Therefore, the communication time may be longer than (1).

The method (1) and the method (2) are common in that data transmission / reception is not parallelized. In the actual calculation, the size of the matrix is much larger than that in the above example, and it must be assumed that the number of divisions of the matrix element will be tens or hundreds. Therefore, as long as the above method is followed, a large amount of time is consumed for communication in a large-scale calculation. (3) Parallel processing method by communication. (A) The arithmetic processing device 1 → the arithmetic processing device 2 and the arithmetic processing device 3 → the arithmetic processing device 4 are simultaneously executed. (B) The arithmetic processing device 1 → the arithmetic processing device 3 and the arithmetic processing device 2 → the arithmetic processing device 4 are simultaneously executed. (C) The arithmetic processing unit 1 → the arithmetic processing unit 4 and the arithmetic processing unit 2 → the arithmetic processing unit 3 are simultaneously executed. (D) The arithmetic processing unit 2 → the arithmetic processing unit 1 and the arithmetic processing unit 4 → the arithmetic processing unit 3 are simultaneously executed. (E) The arithmetic processing device 3 → the arithmetic processing device 1 and the arithmetic processing device 4 → the arithmetic processing device 2 are simultaneously executed. (F) The arithmetic processing unit 4 → the arithmetic processing unit 1 and the arithmetic processing unit 3 → the arithmetic processing unit 2 are simultaneously executed.

In this way, all data is distributed to the four arithmetic processing units without duplication or collision of communication. The time required for communication is, for example, half that of the above method (1). However, the above method cannot be put into practical use unless the communication order in each arithmetic unit is generalized for all division numbers.

Therefore, the present invention has been made in consideration of the above-mentioned drawbacks, and the arithmetic processing for parallel arithmetic operation of matrix data which can achieve high speed by minimizing the waiting time at the time of transmitting and receiving data. It is intended to provide a communication method between devices.

[0021]

A parallel communication system between arithmetic processing units according to claim 1 is assigned one-to-one to a divided data group, operates the assigned data group, and uniquely 2 ^n, where n is a positive integer
And a communication means which is provided for each arithmetic processing device and which mutually transmits and receives the arithmetic result of its own arithmetic processing device and the arithmetic result of each other arithmetic processing device. , By the numerical value of each digit when an arbitrary positive integer m smaller than the number of arithmetic processing units (= 2 ⁿ ) is represented by a binary system,
A step of converting the identification number of each arithmetic processing unit, and an arithmetic process capable of treating the number of each arithmetic processing unit created by the converting step as the identification number of the arithmetic processing unit and simultaneously communicating the arithmetic result. Generating a set of devices.

According to a parallel communication system between arithmetic processing units according to a second aspect, the conversion step according to the first aspect relates to the numerical value of each digit of the identification number of each arithmetic processing unit when expressed in a binary system. , In the numerical value that represents the positive integer m in the binary system by inverting the numerical value of the digit of the identification number corresponding to the digit in which 1 is set in the binary system. It is characterized in that it has a step of keeping the numerical value of the digit of the identification number corresponding to the digit in which 0 stands as it is without inverting it.

In the parallel communication system between arithmetic processing units according to claim 3, the conversion step according to claim 1 relates to the numerical value of each digit of the identification number of each arithmetic processing device when expressed in binary. , In the numerical value that represents the positive integer m in the binary system by inverting the numerical value of the digit of the identification number that corresponds to the digit in which 0 stands in the numerical system that represents the positive integer m in the binary system. It is characterized in that it has a step of leaving the numerical value of the digit of the identification number corresponding to the digit in which 1 is standing as it is without inverting it.

A parallel communication system between arithmetic processing units according to claim 4 is characterized in that the positive integer m according to any one of claims 1 to 3 is changed to 1, 2, ..., 2 ⁿ -1. And

A parallel communication system between arithmetic processing units according to a fifth aspect is assigned to a divided data group, operates the assigned data group, and has a unique identification number,
Number of vehicles less than the number of divisions (= 2 ⁿ + k <2 ^{(n + 1)} , k
Is a natural number, and n is a positive integer), and a communication unit provided for each arithmetic processing unit and for transmitting and receiving mutually the arithmetic result of its own arithmetic processing unit and the arithmetic result of each other arithmetic processing unit. And the number of arithmetic processing units (=
2 ⁿ + k) An arbitrary positive integer m smaller than 2 ⁿ + k) is represented by a binary number, and a step of converting the identification number of each arithmetic processing unit and each operation created by the converting step The number of each processing device is treated as an identification number of the arithmetic processing device, and at the same time, the step of generating a set of arithmetic processing devices capable of communicating the operation result and the set generated by the step of generating the set , If the identification number includes more than the number of arithmetic processing devices (= 2 ⁿ + k), communication of the arithmetic result of the arithmetic processing devices of the set is performed, and the identification number indicates the number of arithmetic processing devices (= 2 ⁿ + k)
And waiting until the communication of all the sets of arithmetic processing units that do not exceed the above is completed.

In the parallel communication system between arithmetic processing units according to claim 6, the conversion step according to claim 5 relates to the numerical value of each digit of the identification number of each arithmetic processing unit when expressed in binary. , In the numerical value that represents the positive integer m in the binary system by inverting the numerical value of the digit of the identification number corresponding to the digit in which 1 is set in the binary system. It is characterized in that it has a step of keeping the numerical value of the digit of the identification number corresponding to the digit in which 0 stands as it is without inverting it.

According to a parallel communication system between arithmetic processing units according to a seventh aspect, in the converting step according to the fifth aspect, the numerical value of each digit of the identification number of each arithmetic processing unit when expressed in binary system. , In the numerical value that represents the positive integer m in the binary system by inverting the numerical value of the digit of the identification number that corresponds to the digit in which 0 stands in the numerical system that represents the positive integer m in the binary system. It is characterized in that it has a step of leaving the numerical value of the digit of the identification number corresponding to the digit in which 1 is standing as it is without inverting it.

A parallel communication system between arithmetic processing units according to claim 8 is characterized in that the positive integer m according to any one of claims 5 to 7 changes from 1 to 2 ^{(n + 1)} -1. .

According to a ninth aspect of the present invention, there is provided a parallel communication system between arithmetic processing devices, wherein a sequence for transmitting and receiving arithmetic results between two arithmetic processing devices according to any one of the first to eighth aspects is first identified by an identification number. It is characterized in that the small arithmetic processing unit sends the arithmetic result to the large arithmetic processing unit, and the arithmetic processing unit having the next largest identification number transmits the arithmetic result to the small arithmetic processing unit.

According to a parallel communication system between arithmetic processing units according to a tenth aspect, a sequence of transmitting and receiving an arithmetic result between two arithmetic processing units according to any one of the first to eighth aspects is first identified by an identification number. It is characterized in that the large arithmetic processing unit sends the arithmetic result to the small arithmetic processing unit, and then the arithmetic processing unit having the small identification number sends the arithmetic result to the large arithmetic processing unit.

[0031]

According to the parallel communication system between arithmetic processing units according to the first aspect of the present invention, an arbitrary positive integer m smaller than the number of arithmetic processing units is represented by a binary number at the same time. A set of arithmetic processing units that can communicate is created.

As a result, it is possible to minimize the waiting time during the data transmission / reception of the arithmetic processing unit.

According to a parallel communication system between arithmetic processing units according to a second aspect of the present invention, the numerical value of each digit of the identification number of each arithmetic processing unit when expressed in the binary system is a positive value according to the first aspect. By inverting the numerical value of the digit of the identification number corresponding to the digit in which 1 is set among the numerical values in which the integer m of is expressed in a binary system, a set of arithmetic processing units capable of simultaneous communication is created.

As a result, it is possible to minimize the waiting time during the data transmission / reception of the arithmetic processing unit.

According to a parallel communication system between arithmetic processing units according to a third aspect of the present invention, the numerical value of each digit of the identification number of each arithmetic processing unit when expressed in a binary system is a positive value according to the first aspect. By inverting the numerical value of the digit of the identification number corresponding to the digit in which 0 is set in the numerical value in which the integer m of is expressed in a binary system, a set of arithmetic processing units capable of simultaneous communication is created.

As a result, it is possible to minimize the waiting time when the arithmetic processing unit transmits and receives data.

In the parallel communication system between arithmetic processing units according to claim 4 of the present invention, the positive integer m according to any one of claims 1 to 3 is replaced by 1, 2, ... ) To create a set of all processing units that can communicate simultaneously.

As a result, it becomes possible to minimize the waiting time during the data transmission / reception of all arithmetic processing devices.

A parallel communication system between arithmetic processing units according to a fifth aspect of the present invention is to create a set of arithmetic processing units capable of simultaneous communication when the total number of arithmetic processing units is smaller than the number of data divisions. is there.

As a result, even when the total number of arithmetic processing units is smaller than the number of data divisions, it is possible to minimize the waiting time when the arithmetic processing units transmit and receive data.

According to a sixth aspect of the present invention, there is provided a parallel communication system between arithmetic processing units, wherein when the total number of arithmetic processing units is less than the number of data divisions, each arithmetic processing unit is represented in binary. For each numerical value of the identification number, by inverting the numerical value of the digit of the identification number corresponding to the digit in which 1 is set in the numerical value in which the positive integer m according to claim 5 is represented in the binary system. ,
This is to create a set of arithmetic processing units that can communicate simultaneously.

As a result, even when the total number of arithmetic processing units is smaller than the number of data divisions, it is possible to minimize the waiting time when the arithmetic processing units transmit and receive data.

According to a seventh aspect of the present invention, there is provided a parallel communication system between arithmetic processing units, wherein when the total number of arithmetic processing units is smaller than the number of divisions of data, each arithmetic processing unit is represented in a binary system. For each numerical value of the identification number, by inverting the numerical value of the digit of the identification number corresponding to the digit in which 0 is set among the numerical values representing the positive integer m according to claim 5 in the binary system. ,
This is to create a set of arithmetic processing units that can communicate simultaneously.

As a result, even when the total number of arithmetic processing units is smaller than the number of data divisions, it is possible to minimize the waiting time when the arithmetic processing units transmit and receive data.

In the parallel communication system between arithmetic processing units according to claim 8 of the present invention, the positive integer m according to any one of claims 5 to 7 is used as 1, 2, ... ) To create a set of all processing units that can communicate simultaneously.

As a result, even when the total number of arithmetic processing units is smaller than the number of data divisions, it is possible to minimize the waiting time during data transmission / reception of all arithmetic processing units.

According to a ninth aspect of the present invention, there is provided a parallel communication system between arithmetic processing units, wherein a group of arithmetic processing units is created by the method according to any one of the first to eighth aspects. The sequence of transmitting and receiving the calculation result between the processing devices is such that the calculation result having a larger identification number is sent to the calculation processing device having a smaller identification number, and then the calculation result having a smaller identification number is sent to the calculation processing device having a larger identification number. To do.

This makes it possible to formulate the sequence of transmitting and receiving the calculation result between the calculation processing devices.

A parallel communication system between arithmetic processing units according to a tenth aspect of the present invention is a set of arithmetic operations after a group is formed between the arithmetic processing units according to any one of the first to eighth aspects. A sequence in which the processing results are transmitted and received between the processing devices is such that the processing results are sent from a processing device with a small identification number to a processing device with a large identification number, and then the processing results are sent from a processing device with a large identification number to a small processing device. To do.

This makes it possible to formulate the sequence of transmitting and receiving the calculation result between the arithmetic processing units.

[0051]

EXAMPLES Examples of the present invention will be described below. A first by a parallel communication system between arithmetic processing units according to claim 1.
An embodiment will be described based on the chart of FIG. 1 and the block diagram of FIG. 4 described above.

In the chart shown in FIG. 1, the identification numbers N of the arithmetic processing units 2a to 2h are 0, 1, ... 7 in the column items, and these are displayed in parentheses as three-digit binary numbers. (Identification number N is 000,001,010,011,1 respectively)
00, 101, 110, 111). A value (1 to 7) smaller than the total number of arithmetic processing units 8 is assigned to each item of the line as an arbitrary number m, and like the above-mentioned identification number, a binary 3-digit number is used in parentheses. It is displayed as a number.

Here, the following operation is performed by taking the case where the arbitrary number m is set to the value 3 as an example (see the row of m = 3 in FIG. 1).

When the value 3 is represented in binary, it is 011. Value 0
In 11, the digit of “0” is the third digit, and the digit of “1” is the first digit and the second digit. Therefore, of the identification numbers N of the binary number display of the arithmetic processing unit corresponding to the row of m = 3, the numerical value of the third digit is left as it is and the numerical value of the second digit and the numerical value of the first digit are inverted (if 1 is 1). Set it to 0 and set it to 1 if it is 0, or invert the value of the third digit (set it to 0 if it is 1 and set it to 0).
If so, the value is set to 1). The second digit and the first digit are left unchanged. FIG. 1 shows the former operation.

By this operation, 2 units are set for each arithmetic processing unit.
A numerical value M of a base number is generated, and by using the value as the identification number of the arithmetic processing device, a set of arithmetic processing devices that can be executed simultaneously can be generated.

As a result, it is possible to minimize the waiting time during the data transmission / reception of the arithmetic processing unit.

The second embodiment of the parallel communication system between arithmetic processing units according to claim 2 is to perform the former operation in the first embodiment.

That is, for example, among the identification numbers N of the binary numbers of the arithmetic processing unit corresponding to the row of m = 3, the numerical value of the third digit is left unchanged and the numerical values of the second digit and the first digit are inverted. (1 is set to 0, and 0 is set to 1). For example, in the first column of FIG. 1 (identification number N in the first arithmetic processing unit
= 0, 000 expressed in binary number and the third line (m =
In 3), the numerical value M = 011. Thus, for the row of m = 3, the result of operating the identification number N of each arithmetic processing unit is (011,010,001,111,11,11)
0,101,100), and these are expressed in decimal notation as (3,2,1,0,7,6,5,4). The numerical value M = (3,2,1,0,7,6,5,4) indicates the identification number of the arithmetic processing device, and the arithmetic processing device in the column to which these values belong is the communication partner. Will be the identification number.
That is, for example, the arithmetic processing device with the identification number 0 in the first column communicates with the arithmetic processing device with the identification number 3 belonging to this column. Thus, for an arbitrary number m = 3, 4
A set between a pair of arithmetic processing units (the arithmetic processing unit with identification number 0,
(Arithmetic processing device of identification number 3), (arithmetic processing device of identification number 1, arithmetic processing device of identification number 2), (arithmetic processing device of identification number 4, arithmetic processing device of identification number 7), An arithmetic processing unit, an arithmetic processing unit with an identification number of 6) can be obtained. After that, based on this set, four pairs of transmission / reception corresponding to m = 3 can be performed in parallel.

As a result, it is possible to minimize the waiting time during the data transmission / reception of the arithmetic processing unit.

The third embodiment of the parallel communication system between arithmetic processing units according to claim 3 is to perform the latter operation of the first embodiment.

That is, in the second embodiment described above, when the arbitrary number m is represented by a binary number, the digit of "0" of m is left unchanged and the digit of "1" is inverted. The operation of the example is such that the digit of "1" is left as it is and the digit of "0" is inverted. For example, the operation of m = 3 (= 011)
Among the identification numbers displayed in binary notation of the processor,
The operation is performed by reversing the digit of “0”, that is, the third digit (0 if 1, 0 if 0) and leaving the first and second digits as they are. Then, an arbitrary number m = 3
On the other hand, a set of four pairs of arithmetic processing devices (arithmetic processing device with identification number 0, arithmetic processing device with identification number 4), (arithmetic processing device with identification number 1 and arithmetic processing device with identification number 5), ( An arithmetic processing device with identification number 2 and an arithmetic processing device with identification number 6) and an arithmetic processing device with identification number 3 and an arithmetic processing device with identification number 7 can be provided. After that, based on this set, four pairs of transmission / reception corresponding to m = 3 are performed in parallel.

As a result, it is possible to minimize the waiting time during the data transmission / reception of the arithmetic processing unit.

A fourth embodiment of the parallel communication system between arithmetic processing units according to claim 4 will be described below with reference to the chart of FIG.

As shown in the figure, the value of an arbitrary number m is changed from 1 to 7 (the total number of arithmetic processing devices -1, in this case, the total number of arithmetic processing devices is 8), and each value is changed. Each time, the operation described in the first to third embodiments is performed to generate a combination of sets among all arithmetic processing units capable of simultaneous communication.

As a result, it is possible to easily perform an exhaustive one-to-one correspondence without overlap between the respective arithmetic processing devices for all conditions, and to perform communication between a large number of arithmetic processing devices without delay. To be done. That is, by transmitting and receiving data in parallel in parallel, the delay in communication can be reduced and the calculation speed can be increased.

A fifth embodiment of the parallel communication system between arithmetic processing units according to claim 5 will be described with reference to FIG. FIG. 2 is a table for explaining the operation of determining the communication partner of each arithmetic processing device for every arbitrary number m, as in the case of FIG. 1 described above.

In the first to fourth embodiments, the number of arithmetic processing units is assumed to be a power of 2, but the fifth embodiment
The embodiment can be applied to a case where the number of arithmetic processing devices is not a power of 2 as a more general condition, that is, a case where the number of arithmetic processing devices is represented by 2 ⁿ + k (<2 ^{(n + 1 )} ). It is the one.

Here, description will be given assuming that the number of arithmetic processing devices is 6 (= 2 ² +2 <2 ^{(2 + 1)} ) as shown in FIG. When the identification numbers (0 to 5) of the arithmetic processing unit are displayed in binary, they are (000, 001, 010, 011, 1).
00, 101). On the other hand, for example, as in the second embodiment, the operation of the number m = 3 (the number of the third digit is left unchanged,
When the first digit and the second digit are reversed), the number M assigned to each arithmetic processing unit becomes (011,0).
10, 001,000, 111, 110). 10
It is (3,2,1,0,7,6) when expressed in the base system.
Thus, two sets of arithmetic processing units (arithmetic processing device with identification number 0 and arithmetic processing device with identification number 3) and (arithmetic processing device with identification number 1 and arithmetic processing device with identification number 2) are generated.
However, for the arithmetic processing devices with the identification numbers 4 and 5, there is no arithmetic processing device corresponding to the identification numbers 6 and 7, so a set of arithmetic processing devices cannot be generated (FIG. 2).
Mark "X" part). Therefore, the calculation corresponding to (arithmetic processing device with identification number 4 and arithmetic processing device with identification number 7) and (arithmetic processing device with identification number 5 and arithmetic processing device with identification number 6) is (arithmetic processing device with identification number 0). , The arithmetic processing unit with the identification number 3), (the arithmetic processing unit with the identification number 1, the arithmetic processing unit with the identification number 2) It will be performed between these arithmetic processing units.

As described above, even when the total number of arithmetic processing devices is less than the number of data divisions, it is possible to minimize the waiting time when the arithmetic processing devices transmit and receive data.

A sixth embodiment of the parallel communication system between arithmetic processing units according to claim 6 will be described with reference to the chart of FIG.

Similar to the fifth embodiment, the sixth embodiment has a general condition that the number of arithmetic processing devices is not a power of 2, that is, the number of arithmetic processing devices is 2 ⁿ + k (<2.
^{(N + 1)} ), so that it can be applied. In the sixth embodiment, similarly to the second embodiment, a set of arithmetic processing units is generated as follows.

For example, an arbitrary number m = 3 is 011 when expressed in a binary system. In the value 011, the digit of "0" is the third digit, and the digit of "1" is the first digit and the second digit. Where m =
Of the respective identification numbers N of the binary display of the arithmetic processing unit corresponding to the row of 3, the numerical value of the third digit is left as it is and the numerical value of the second digit and the first digit are inverted (if 1 is 0, If the value is 0, the value is set to 1), or the numerical value of the third digit is inverted (if the value is 1, the value is 0; if the value is 0, the value is 1). For example, among the identification numbers N of the binary display of the arithmetic processing unit corresponding to the row of m = 3, the numerical value of the third digit is left as it is and the numerical value of the second digit and the numerical value of the first digit are inverted (if 1 is 1 0 and 1 if 0).

As a result, even when the total number of arithmetic processing devices is smaller than the number of data divisions, it is possible to minimize the waiting time when the arithmetic processing devices transmit and receive data.

The seventh embodiment of the parallel communication system between the arithmetic processing devices according to the seventh aspect is similar to the fifth embodiment in that the general condition is that the number of arithmetic processing devices is not a power of 2, that is, the arithmetic operation is performed. The number of processing devices is 2 ⁿ + k (<2
^{(N + 1)} ), so that it can be applied.

In the seventh embodiment, similarly to the third embodiment, a set of arithmetic processing units is generated as follows.

When an arbitrary number m = 3 is represented by a binary number, the number m
The digit "0" is left as it is and the digit "1" is inverted, whereas the digit "1" is left as it is and the digit "0" is inverted. For example, the operation of m = 3 (= 011) is performed by using the binary identification number of the arithmetic processing device
The operation is performed by reversing the digit of “0”, that is, the third digit (0 if 1, 0 if 0) and leaving the first and second digits as they are. For example, an operation of several m = 3 (the number of the third digit is left as it is and the positions of the first digit and the second digit are reversed) is performed. 2 of the arithmetic processing units corresponding to the row of m = 3
The numerical value of the third digit of each identification number N displayed in the base number is left as it is and the numerical value of the second digit and the numerical value of the first digit are inverted (1 is 0, 0 is 1).

As a result, even when the total number of arithmetic processing devices is smaller than the number of data divisions, it is possible to minimize the waiting time during data transmission / reception of the arithmetic processing devices.

An eighth embodiment of the parallel communication system between arithmetic processing units according to claim 8 will be described with reference to FIG.

In FIG. 2, the method adopted in the fourth embodiment is used as an operation method for giving the identification number of the communication partner of each arithmetic processing unit. As shown in FIG. 2, several meters
The value of is changed from 1 to 7 and the correspondence described in the fourth embodiment is performed for each stage to generate a set of the arithmetic processing device to be executed and the arithmetic processing (device) to be waited for.

As a result, even if the total number of arithmetic processing units is less than the number of data divisions, an exhaustive one-to-one correspondence between the arithmetic processing units without duplication can be performed easily for all conditions. It can be performed, and communication between a large number of arithmetic processing units can be performed without delay. That is, by transmitting and receiving data in parallel in parallel, the delay in communication can be reduced and the calculation speed can be increased.

A ninth embodiment of the parallel communication system between arithmetic processing units according to claim 9 will be described.

Communication between the arithmetic processing devices normally takes the form of transmission and reception of data. Therefore, if data is transmitted from the arithmetic processing device 1 to the arithmetic processing device 2, for example, the arithmetic processing device 2 will be reversed in a series of communication processes. Data is transmitted to the arithmetic processing unit 1. Therefore, a rule regarding the sequence of transmission and reception is required after a pair between the arithmetic processing units is generated by the above-described method to make a one-to-one correspondence.

Therefore, in the ninth embodiment, as the first step, data is sent from the smaller identification number to the larger identification number, and the second
As a step, the data transfer sequence is determined so that the data is sent from the larger identification number to the smaller identification number. That is, for example, the arithmetic processing device 1 and the arithmetic processing device 2
When and are combined, first, the arithmetic processing device 1 transmits data to the arithmetic processing device 2, and immediately thereafter, the arithmetic processing device 2 transmits data to the arithmetic processing device 1.

As a result, the sequence of transmitting and receiving the calculation result between the arithmetic processing units is formulated.

On the contrary, in the tenth embodiment of the parallel communication system between arithmetic processing units according to the tenth aspect, as the first step, the data is sent from the one having the larger identification number to the one having the smaller identification number, and as the second step. The data transfer sequence is determined so that the data having the smaller identification number is sent to the one having the larger identification number. For example, when the arithmetic processing unit 1 and the arithmetic processing unit 2 are combined, data is first transmitted from the arithmetic processing unit 2 to the arithmetic processing unit 1, and immediately thereafter, data is transmitted from the arithmetic processing unit 1 to the arithmetic processing unit 2. I am trying to send you.

As a result, the sequence of transmitting and receiving the calculation result between the arithmetic processing units is formulated.

[0087]

First, the effect of the present invention will be described quantitatively. For example, the size of the matrix is M and the number of arithmetic processing units is K.
It is assumed that the entire matrix is K-divided and allocated to each arithmetic processing unit. From that state, the time required to create a situation in which all processing units hold data for the entire matrix by communication between the processing units is calculated as follows.

Generally, the time T required to transmit data from the arithmetic processing unit to another arithmetic processing unit can be written as T = A + B × W. A is the time required for communication preparation, which is always required for one communication regardless of the amount of data to be transmitted. That is, the value of A does not depend on the amount of data. B × W is a term proportional to the data amount, and W is the data amount (word number)
And B is the transfer time required to transfer one word.

The one-to-one combination of the arithmetic processing units is K (K
−1), the total communication time T T (K) = K (K−1) × (A + B × M / K) without parallelization of communication is (1). When the number of divisions W is increased, the total communication time T (K) increases almost in proportion to the number of divisions K. When the parallel communication method between the first to third arithmetic processing devices of the present invention is adopted, the communication is completely parallelized, so that the communication time required for one arithmetic processing device is the same as the communication of the entire system. It's time. Data transmission destination is (K-1) for each processing unit
Since there is one transmission, one reception for each unit,
The total communication time when the present invention is applied is T (K) = 2 (K-1) * (A + B * M / K) (2). That is, the term including A increases with the number of arithmetic processing devices, but the term including B proportional to the data amount hardly depends on the number of arithmetic processing devices.

The above is shown in the graph of FIG. The horizontal axis represents the number of arithmetic processing units K, and the vertical axis represents the time T required for communication.
(K), the relationship between the equation (1) (broken line 8 in FIG. 3) in which communication is not parallelized, and the relationship in equation (2) (solid line 9 in FIG. 3) in which communication is parallelized according to the present invention. Are shown in comparison.

According to the first aspect of the present invention, it is possible to minimize the waiting time during the data transmission / reception of the arithmetic processing unit.

According to the invention of claim 2, it becomes possible to minimize the waiting time at the time of transmitting and receiving the data of the arithmetic processing unit.

According to the third aspect of the invention, it is possible to minimize the waiting time when the arithmetic processing unit transmits and receives data.

According to the invention of claim 4, it becomes possible to minimize the waiting time at the time of transmitting / receiving data of all the arithmetic processing devices.

According to the fifth aspect of the invention, even when the total number of arithmetic processing devices is smaller than the number of data divisions, it is possible to minimize the waiting time when the arithmetic processing devices transmit and receive data. .

According to the invention of claim 6, even when the total number of arithmetic processing units is smaller than the number of data divisions, it is possible to minimize the waiting time when the arithmetic processing units transmit and receive data. .

According to the invention of claim 7, even when the total number of arithmetic processing devices is less than the number of data divisions, it is possible to minimize the waiting time when the arithmetic processing devices transmit and receive data. .

According to the invention of claim 8, even when the total number of arithmetic processing units is smaller than the number of data divisions, it is possible to minimize the waiting time during the data transmission / reception of all arithmetic processing units. become.

According to the ninth aspect of the invention, it is possible to formulate the sequence of transmitting and receiving the calculation result between the calculation processing devices.

According to the tenth aspect of the present invention, it is possible to formulate the sequence of transmitting and receiving the calculation result between the calculation processing devices.

[Brief description of drawings]

FIG. 1 is a diagram for explaining first, second, and fourth embodiments of a parallel communication system between arithmetic processing units according to the present invention.

FIG. 2 is a diagram for explaining fifth, sixth and eighth embodiments of the parallel communication system between arithmetic processing units according to the present invention.

FIG. 3 is a graph showing the relationship between the number of arithmetic processing devices and the time required for communication when the communication of the operation result is not parallelized as in the prior art and when the communication of the operation result is parallelized according to the present invention.

FIG. 4 is a block diagram showing a configuration in the case where a plurality of arithmetic processing units divide and perform arithmetic operations.

[Explanation of symbols]

N Identification number of each arithmetic processing unit M Identification number of the arithmetic processing unit of the other party to which the present invention is applied m Positive integer not exceeding the number of divisions 1H Host computer 2-0 to 2-7 Arithmetic processing unit 3H Host storage device 4H Host communication means 5-0-5-7 Individual storage device 6-0-6-7 Individual communication means

Claims (10)

[Claims] 1. An arithmetic processing unit of 2 ⁿ (n is a positive integer) units each having a unique identification number, which is assigned to a divided data group on a one-to-one basis and operates on the assigned data group. And a parallel communication system between arithmetic processing devices, which is provided for each arithmetic processing device, and includes communication means for mutually transmitting and receiving the arithmetic result of its own arithmetic processing device and the arithmetic result of each other arithmetic processing device. In the step of converting the identification number of each arithmetic processing unit by a numerical value of each digit when an arbitrary positive integer m smaller than the number of arithmetic processing units (= 2 ⁿ ) is represented by a binary system, An arithmetic processing unit that treats the number of each arithmetic processing unit created by the converting step as an identification number of the arithmetic processing unit and simultaneously generates a set of arithmetic processing units capable of communicating the arithmetic result. In between Communication system. 2. The step of converting, wherein the positive integer m is represented by a binary number for each numerical value of each digit of the identification number of each arithmetic processing unit when the binary number is used. Of the digit of the identification number corresponding to the digit in which is set, and the positive integer m of the digit of the identification number corresponding to the digit in which 0 is set in the binary number 2. The method according to claim 1, further comprising the step of leaving the numerical value as it is without inverting it.
A parallel communication method between the arithmetic processing units described in. 3. The step of converting is 0 in the numerical value representing the positive integer m in the binary system for each numerical value of each digit of the identification number of each arithmetic processing unit when expressed in the binary system. Of the digit of the identification number corresponding to the digit in which is set, and the positive integer m is represented in binary notation 2. The method according to claim 1, further comprising the step of leaving the numerical value as it is without inverting it.
A parallel communication method between the arithmetic processing units described in. 4. The parallel communication system between arithmetic processing units according to claim 1, wherein the positive integer m changes to 1, 2, ..., 2 ⁿ −1. 5. A number of units (= 2 ⁿ + k <2) assigned to a divided data group, operating the assigned data group, having a unique identification number, and having a number smaller than the number of divisions (= 2 ⁿ + k <2
^{(N + 1)} , k is a natural number, and n is a positive integer) and the arithmetic processing device provided for each arithmetic processing device and the arithmetic result of its own arithmetic processing device and the arithmetic result of each other arithmetic processing device. In a parallel communication system between arithmetic processing units provided with a communication means for transmitting and receiving mutually, each positive integer m smaller than the number of the arithmetic processing units (= 2 ⁿ + k) is represented by a binary system. Depending on the number of digits,
A step of converting the identification number of each arithmetic processing device, and an operation capable of treating the number created by the converting step for each arithmetic processing device as the identification number of the arithmetic processing device and simultaneously communicating the operation result. In the step of generating a set of processing devices and the set generated by the step of generating the set, the identification number is the number of the arithmetic processing devices (= 2 ⁿ + k)
, The communication of the calculation results of the arithmetic processing units of the group is performed, and the arithmetic processing of all the groups whose identification numbers do not exceed the number (= 2 ⁿ + k) of the arithmetic processing units. A parallel communication method between arithmetic processing units, which has a step of waiting until the communication of the devices is completed. 6. The step of converting is one of the numerical values representing the positive integer m in binary notation for each numerical value of each digit of the identification number of each arithmetic processing unit when expressed in binary notation. Of the digit of the identification number corresponding to the digit in which is set, and the positive integer m of the digit of the identification number corresponding to the digit in which 0 is set in the binary number 6. The method according to claim 5, further comprising the step of leaving the numerical value as it is without inverting it.
A parallel communication method between the arithmetic processing units described in. 7. The step of converting is 0 in the numerical value representing the positive integer m in the binary system for each numerical value of each digit of the identification number of each arithmetic processing unit when expressed in the binary system. The digit of the digit of the identification number corresponding to the digit in which is set is inverted, and the digit of the digit of the identification number corresponding to the digit in which 1 is set is represented in the binary number representing the positive integer m. 6. The method according to claim 5, further comprising the step of leaving the numerical value as it is without inverting it.
A parallel communication method between the arithmetic processing units described in. 8. The positive integer m is from 1 to 2 ^{(n + 1)} −1.
The parallel communication system between arithmetic processing units according to any one of claims 5 to 7, wherein: 9. A sequence of transmitting and receiving arithmetic results of two arithmetic processing units is first sent from an arithmetic processing unit having a smaller identification number to an arithmetic processing unit having a larger identification number, and then an arithmetic processing unit having a larger identification number. The arithmetic operation result is sent from the device to a small arithmetic processing unit.
8. A parallel communication system between arithmetic processing units according to any one of 8. 10. A sequence of transmitting and receiving an arithmetic result between two arithmetic processing units is first sent from an arithmetic processing unit having a large identification number to an arithmetic processing unit having a small identification number, and then an arithmetic processing unit having a small identification number. 2. The processing result is sent from the device to a large processing device.
A parallel communication system between arithmetic processing units according to any one of items 1 to 8.