JPH08263372A - Device for collection of cache miss information and tuning - Google Patents

Abstract

PURPOSE: To tune the performance by a computer by collecting cache miss information with respect to the object program outputted from the compiler and putting this information to the use of performance tuning and feeding back the obtained cache miss information to the compiler. CONSTITUTION: A control part 4 traces an execution instruction of a measuring object 2 outputted from a compiler 1 and extracts the data address accessed by the instruction and transfers it to a cache simulation part 5 together with compile information 3. The cache simulation part 5 simulates a cache memory; and if the transferred data address is not within the address range of data which is considered to be taken into the cache memory, a cache miss is detected, and the frequency in access of cache miss information 6 and the frequency in cache miss are counted up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for collecting cache miss information on an object program output by a compiler and tuning the program based on the cache miss information.

[0002]

It is known that a large part of the execution time of a program that is not I / O bound is concentrated in only a few percent of the written program text.
Therefore, if the device is devised so that this few percent portion is efficiently executed, the execution performance of the entire program will be improved. A performance analysis tool is known that counts the number of times each executable statement in a program is executed in order to detect only a few percent of the area where the program execution is concentrated. For example, information processing, VOL 20, NO. 8, PP703-711
(1979) discusses such a dynamic analysis tool.

[0003]

Although it is possible to collect the number of executions of each execution statement in a program by using a performance analysis tool of the prior art, the access performance of data handled by the execution statement in the program is taken into consideration. Not not. In particular, there is a problem in that performance deterioration is not taken into consideration when running a program that handles a large-sized array in an information processing apparatus having a cache memory.

The present invention collects cache miss information about an object program output by a compiler,
The purpose is to be useful for performance tuning.

It is another object of the present invention to feed back the obtained cache miss information to the compiler for performance tuning by the compiler.

[0006]

According to the present invention, an execution instruction of an object program is traced to extract a data address of data accessed by the instruction, a cache memory is simulated based on this data address, The present invention is characterized by a cache miss information collection device that detects this state as a cache miss when it can be considered that the relevant data has not been taken into the cache memory, and counts up and outputs the number of accesses and the number of cache misses for the data address. To do.

The present invention further refers to this cache miss information and is independent so that it can be executed in parallel with this instruction when the ratio of the number of cache misses of the data address relating to the execution instruction to the number of accesses is a predetermined value or more. The tuning device is provided with a function of changing the execution order of the instructions so that the subsequent instructions are executed in parallel.

[0008]

The number of accesses and the number of cache misses can be aggregated for all data addresses accessed by instructions that access data in the main memory such as load / store instructions. By making improvements, it is possible to improve the execution performance of the program.

Further, the cache miss information can be fed back to the compiler to carry out the instruction schedule in consideration of the cache miss, which can contribute to the improvement of the execution performance of the program.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing the outline of the configuration and processing flow of an apparatus for collecting and tuning cache miss information according to this embodiment. The compiler 1 inputs the source program 9 and inputs the measurement object 2 and the compilation information 3
Is generated and output. The measurement object 2 is an object program that is generated by the compiler 1 and is a target of tuning. The compilation information 3 is information about the source program 9 and the measurement object 2 created by the compiler 1. The control unit 4 traces the execution of the measurement object 2, and every time a load / store instruction is issued from the measurement object 2, the access instruction address indicating the main memory storage location of the load / store instruction and these load / store instructions are stored. The access data address of the data to be accessed and the cache simulation unit 5 are passed. The control unit 4 also passes the compile information 3 of the related source program 9 to the cache simulating unit 5. The cache simulating unit 5 simulates the access status of the cache memory for the access instruction address and the access data address received from the control unit 4, and counts the number of accesses and the number of cache misses for each access instruction address and access data address. The cache miss information 6 is output. The screen display unit 7
The source program 9 and the cache miss information 6 are input and the number of accesses and the number of cache misses are displayed on the display screen 8 for each line of the source program. The screen display unit 7 also displays the access count and the cache miss count for the array appearing in the source program 9 on the display screen 8. The compiler 1 inputs the cache miss information 6 and takes the number of cache misses of the data accessed by the load / store instruction into consideration, and optimizes the object program so as to improve the performance.
The compile information 3, the cache miss information 6 and the source program 9 are information stored in the storage device of the information processing device. The compiler 1, the measurement object 2, the control unit 4, the cache simulation unit 5, and the screen display unit 7 are processing units, and are realized by executing a program stored in the storage device of this information processing apparatus.

FIG. 2 is a diagram showing a data structure of the compilation information 3. The source file name is the name of the file in which the source program 9 is stored. The line number is the number of each source statement line of the source program 9. The access instruction address stores the access instruction address of the source statement corresponding to each line number. The source file name in the latter half of the compilation information 3 is the name of the file in which the source program 9 is stored,
The array name is the name of the array that appears in the source program, the start address is the start address of the array,
The size is the size of the entire array, and the element size is the size of the elements that make up the array. The number of elements is the size of each array divided by the element size.

FIG. 3 is a diagram showing a data structure of the cache miss information 6. FIG. 3A is a table of the number of accesses and the number of cache misses corresponding to the line position of the source program. The access instruction address, source file name and line number are information obtained from the compilation information 3. FIG. 3B is a table of the number of accesses and the number of cache misses for each access data address. The access data address is the address of the data passed from the control unit 4 to the cache simulating unit 5, and includes the access data address of each element forming the array. Figure 3 (c)
Is an array address table, array name, start address,
It consists of size and element size. These pieces of information are obtained from the compilation information 3, and the access data address of each element forming the array can be calculated based on these pieces of information and can be associated with the information of FIG. 3B.

The control unit 4 activates the measurement object 2, executes the instructions contained in the measurement object 2 one by one according to the sequence, and as a result of tracing, stores the address of the load / store instruction and the data accessed by the instruction. The data address and is extracted and passed to the cache simulating unit 5. In the present embodiment, instructions other than load / store instructions are not passed to the cache simulating unit 5 because they do not access the main memory and are not related to cache misses, but in general, the instruction address and data of all the instructions that access the main memory. It is necessary to pass the address and the cache simulating unit 5. The control unit 4 refers to the compile information 3 before tracing the measurement object 2 and passes the relevant compile information to the cache simulating unit 5.

Generally, the cache memory is divided into a plurality of blocks and fetches instructions and data in the main storage device in units of blocks. Here, a block is a main memory area having a certain address range. A cache miss is a state in which there is no copy of the block on the main memory in the cache memory. When a cache miss occurs, any block in the cache memory is replaced by the newly accessed block. The cache simulating unit 5 simulates the operation of such a cache memory, and has a built-in table having the same number of entries as the number of blocks of the cache memory. The head address of the block is stored in each entry. If the block address obtained from the access instruction address and the access data address passed from the control unit 4 matches the address stored in any entry of this table, the cache data has been hit, and if they do not match. A cache miss has occurred. When a cache miss occurs, the cache simulating unit 5 replaces the block address of any entry on this table with the start address of the newly accessed block according to the block replacement algorithm of the actual cache memory.
The cache simulating unit 5 counts up the corresponding access count on the cache miss information 6 for the access instruction address and the access data address passed from the control unit 4 in this way, and also determines whether or not a cache miss has occurred. If it is determined that a cache miss has occurred, the number of corresponding cache misses in the cache miss information 6 is counted up.

The cache simulating unit 5 receives the compile information 3 from the control unit 4 prior to counting up the number of accesses and the number of cache misses.
It is expanded as cache miss information 6 as shown in (a) and FIG. 3 (c). In the access status table for each access data address of FIG. 3B, when the control unit 4 starts tracing the measurement object 2 and receives the actual access data address, if it is a new access data address, cache miss information is displayed. 6 is additionally registered and the number of times is counted up, and if it is already registered, only the number of times is counted up.

FIG. 4 is a flowchart showing the processing procedure until the line-by-line access status of the source program and the access status by array are displayed. Control unit 4
Reads the source file name, line number, access instruction address, array name and array start address, size, element size information from the compilation information 3 and passes it to the cache simulating unit 5 (step 21). The cache simulating unit 5 expands these compilation information as fixed information of the cache miss information 6 on the storage device. Next, the control unit 4 traces the instructions executed by activating the measurement object 2 one by one, collects the obtained access instruction address and access data address, and passes them to the cache simulating unit 5 (step 22). The cache simulating unit 5 refers to the table simulating the cache memory and determines whether or not there is a cache miss (step 23). Next, the cache simulating unit 5 updates the access count and the cache miss count for the relevant address on the cache miss information 6 according to this determination (step 24). If the execution of the measurement object 2 has not been completed, the control unit 4 (step 25Y
ES), and returns to step 22 to continue the processing. When the execution of the measurement object 2 is completed (step 25N
O), and passes control to the screen display unit 7. The screen display unit 7 refers to the source program 9 and the cache miss information 6, and displays the number of accesses and the number of cache misses on the display screen 8 in correspondence with the source statement of each line of the source program (step 26). Next, the screen display unit 7 refers to the table of the number of accesses and the number of cache misses for each access data address shown in FIG. 3B on the cache miss information 6, and each access data address is the start address of any array. Whether or not it is included in the array area determined by the size is determined, and if it is included, the elements of the array are stored in association with the access count / cache miss count (step 27). Finally, the screen display unit 7 accumulates the access count and cache miss count for each array element for the entire array and displays the access count and cache miss count for the entire array and each array element (step 28).

FIG. 5 is a diagram showing an example of the display screen 8 for displaying the access status for the entire array and each element of the array. The number of accesses and the number of cache misses are displayed in the block indicating each array element.

Since the access status is displayed for each line of the source program as described above, it is possible to detect a line with a large number of accesses and cache misses and improve the source program so that the cache is used effectively. . In addition, it is possible to check the access status of an array to know which array has performance degradation, which can be useful for improving performance.

In the above embodiment, the compile information 3 is passed to the cache simulating section 5 via the control section 4, but the cache simulating section 5 directly inputs the compile information 3 without passing through the control section 4. You may do it. At this time, the control unit 4 has only the function of tracing the execution of the measurement object 2.

An embodiment of the program tuning process performed by the compiler 1 will be described below.

FIG. 6A is a diagram showing a part of the program in the form of an object program as an example. The numbers ~ are numbers indicating the sequence of instructions. A, B
And C indicate array elements, and r1 to r9 indicate registers and their numbers. Of the instruction execution time of each instruction, the instruction acceptance time is the time from the acceptance of the instruction until the completion of acceptance of the next instruction (the number of machine cycles, etc.). The instruction processing time is the time from the acceptance of an instruction to the end of the processing, and is the same as the instruction acceptance time unless a cache miss is considered. Considering cache miss, the instruction processing time is longer than the instruction reception time. FIG.6 (b) is
The cache miss information 6 is a part of the cache miss information 6 and indicates the number of access times and the number of cache misses of the array elements A, B, and C.

7a and 7b are flowcharts showing the flow of the tuning process performed by the compiler 1.
The compiler 1 fetches the first instruction P from the program (step 31), and if it is a load / store instruction (YES in step 32), the number of accesses and the number of cache misses are based on the access data address of the data stored in the main memory. Is taken out (step 33). If the cache miss ratio obtained by dividing the cache miss count by the access count is larger than a preset ratio (for example, 50%) (YES in step 34), the instruction processing time T in consideration of the cache miss for the instruction P is set (step). 35). In the program example of FIG. 6, the instruction corresponds to the instruction P that has reached step 35, and T is set to 6. Next, the program searches for an instruction N that uses the register loaded / stored by the instruction P (step 36).
In the program example of FIG. 6, the instruction corresponds to the instruction N. Next, the processing time T1 of another instruction which is independently processed in parallel between the instruction P and the instruction N is calculated (step 37). In the program example of FIG. 6, the instruction corresponds to another instruction, and the processing time T1 is 1. T if there is no other command that satisfies the condition
1 is 0. Next, if there is an instruction I that follows the instruction N and that can be executed independently before the instruction N, the instruction I is taken out and the processing time T2 is obtained (step 38). Figure 6
In the example, the instruction corresponds to the instruction I. Next, processing time T1
Then, T1 is added to T2 (step 39). Next, if the processing time T1 is smaller than the processing time T (YES in step 40), the instruction I is moved after the other instruction (step 41), and the process returns to step 38 to continue the processing. That is, the instruction execution order is changed so that the instruction I is executed in parallel with the instruction P. In the example of FIG. 6, the instruction is inserted between the instructions, and then the instruction I can also be moved, so that the instruction I is inserted between the instructions. If the processing time T1 is not shorter than the processing time T, or there is no subsequent instruction I that satisfies step 38 (step 40 NO) and all the instructions have not been checked (step 42 NO), the process returns to step 31 and the subsequent instruction is executed. The above process is repeated. If the instruction P is not a load / store instruction (NO in step 32) or the cache miss ratio is small (NO in step 34), the process returns to step 31 and the above processing is repeated. When all the instructions in the program are inspected (YES in step 42), the process ends.

According to the above embodiment of the tuning process,
During the instruction processing time of a load / store instruction that causes a cache miss, subsequent instructions that are independent of this load / store instruction can be executed in parallel, and as a result, performance should be improved compared to when tuning processing is not performed. You can In the example of FIG. 6, the processing time from the instruction is 13 when the tuning processing of the present embodiment is not performed (the instruction is executed in parallel with the instruction), whereas the tuning processing of the present embodiment is performed. In this case, the processing time is 9 and the performance is improved by about 1.4 times.

[0025]

According to the present invention, cache miss information can be collected for an object program output by a compiler, and can be used for performance tuning. Further, since the obtained cache miss information is fed back to the compiler, performance tuning can be performed by the compiler.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an apparatus for collecting and tuning cache miss information according to an embodiment.

FIG. 2 is a diagram showing an example of a data structure of compilation information 3;

FIG. 3 is a diagram showing an example of the data structure of cache miss information 6;

FIG. 4 is a flowchart showing the flow of processing until the line-by-line access status of the source program and the array access status are displayed.

FIG. 5 is a diagram showing an example of a display screen displaying an access status of an array.

FIG. 6 is a diagram showing a part of a program by a case.

FIG. 7a is a flowchart (first half) showing a flow of a tuning process performed by the compiler of the embodiment.

FIG. 7b is a flowchart (second half) showing the flow of tuning processing performed by the compiler of the embodiment.

[Explanation of symbols]

2 ... measurement object, 3 ... compilation information,
4 ... control unit, 5 ... cache simulation unit,
6 ... Cash miss information

Claims (2)

[Claims] Claim: What is claimed is: 1. A processing means for tracing an instruction of an object program output by a compiler one by one in accordance with its execution sequence and extracting an address on a main storage device of data accessed by the instruction, and simulating a cache memory. When the address is not within the address range of the data considered to be fetched in the cache memory, it is detected as a cache miss, and the number of accesses and the number of cache misses for the address are counted up to obtain cache miss information. A device for collecting cache miss information, which comprises: 2. A processing means for tracing instructions one by one in accordance with an execution sequence of an object program output by a compiler and extracting an address on a main storage device of data accessed by the instruction, and simulating a cache memory. When the address is not within the address range of the data considered to be fetched in the cache memory, it is detected as a cache miss, and the number of accesses and the number of cache misses for the address are counted up to obtain cache miss information. The compiler refers to the cache miss information, and is executed in parallel with the instruction when the ratio of the cache miss count of the address for the instruction to the access count is equal to or more than a predetermined value. Get independent subsequent instructions in parallel Device to collect and tuning of a cache miss information and providing a processing means for changing the execution order of instructions so as to line.