JP2012208615A - Instruction execution analysis device, instruction execution analysis method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the usage efficiency of cache memory.SOLUTION: An instruction execution analysis device performs: performs a simulation in which a main memory device is accessed and an instruction is executed to extract, as an inefficient memory block, a memory block where memory-access targets are concentrated on a part of data (an inefficient block extraction process 2) and extract, as an inefficient instruction, an instruction causing a memory access to the inefficient block (an inefficient instruction extraction process 3) in the simulation, thereby enabling: prevention of data with a high frequency of access to the same block of cache memory and data with a low frequency of such access being intermixed; and improvement of the usage efficiency of the cache memory.

Description

  The present invention relates to a technique for improving the utilization efficiency of a cache memory.

The information processing apparatus is composed of a processor device, a main memory device, and an input / output device. Especially for a device that requires execution performance, it operates at a high frequency and utilizes a processor device having a cache memory.
At this time, the hit rate of the cache memory affects the performance.
In general, the hit rate is 95% or higher, and a high-speed one achieves a hit rate close to 99%.
In other words, it is not uncommon for the performance of the entire system to drop significantly with only a few percent drop in the cache memory hit rate.
Therefore, for example, as disclosed in Patent Document 1, it is proposed that tuning is performed by collecting cache memory behavior information centered on the hit rate.

The method described in Patent Document 1 includes a simulator that simulates an instruction, and simulates an instruction and a cache memory.
According to the method described in Patent Document 1, it is possible to display the number of accesses and the number of cache misses (number of accesses-number of hits) for each element of an array for a program having a large array.
The method described in Patent Document 1 improves the source program so as to effectively use the cache by detecting lines with a large number of accesses and cache misses.
That is, since an array having a large cache miss has a large delay, code is generated by the compiler so that another instruction is executed in the meantime.

Japanese Patent Laid-Open No. 08-263372

However, the information obtained by the method of Patent Document 1 is the number of accesses and the number of misses in the program data array, and it is unclear what kind of influence it has on the entire cache.
For example, if the number of cache misses is displayed as 0, it appears that the cache is functioning effectively, but only certain elements in the same cache block have access counts of 10,000 times. If the number of times = 1, and the other elements are the number of accesses = 1, and the number of misses = 0, the cache cannot be said to be used effectively.
Since the access frequency = 1 element is less frequently used, there is no influence even if it is not placed in the cache memory.
Rather, it can be said that it is efficient to use the cache memory for another data in another array having a high frequency of use.
In other words, it can be imagined that such an array increases the number of cache misses of other arrays.
In other words, an array element that is accessed efficiently with few cache misses may have an adverse effect on other arrays. However, in the method of Patent Document 1, it is easy to trace back to such a cause. I can't.
One technique for effectively using cache memory is to only harden cache blocks that have a high number of accesses and harden those that have a low number of accesses so that they do not get on the cache block. It is necessary.
One of the causes of a decrease in cache use efficiency is a mixture of high access frequency and low access frequency.
In particular, in recent high-performance processors, as the cache capacity increases, the size of the cache block tends to increase, and this tendency has become increasingly prominent.
Further, in the method of Patent Document 1, it is difficult to easily determine which part of the program caused such a cause, so that efficient program correction is difficult.

  One of the main objects of the present invention is to solve the above-mentioned problems, and it is possible to prevent data with high access frequency and data with low access from being mixed in the same block of the cache memory, thereby improving the use efficiency of the cache memory. The main purpose is to improve.

An instruction execution analysis apparatus according to the present invention includes:
Analyzing the status of memory access to the main memory device in a simulation in which a memory access to the main memory device is executed and executing an instruction, and based on the analysis result, out of a plurality of memory blocks in the main memory device An inefficient block extraction unit that extracts a memory block whose memory access target is biased toward some data in the memory block as an inefficient block;
An inefficient instruction extracting unit that extracts an instruction that satisfies a predetermined condition as an inefficient instruction among the instructions that have generated memory access to the inefficient block extracted by the inefficient block extracting unit; To do.

  According to the present invention, in the simulation, a memory block whose memory access target is biased toward a part of the data in the memory block is extracted as an inefficient block, and the instruction that caused the memory access to the inefficient block is Since the instructions are extracted as efficient instructions, it is possible to prevent data with high access frequency and data with low access frequencies from being mixed in the same block of the cache memory, and improve the use efficiency of the cache memory.

FIG. 3 is a flowchart showing a processing procedure according to the first embodiment. FIG. 4 is a flowchart showing inefficient block extraction processing according to the first embodiment. The flowchart figure which shows the calculation process of the byte number of the high access frequency and low access frequency which concern on Embodiment 1. FIG. FIG. 4 is a flowchart showing inefficiency instruction extraction processing according to the first embodiment. FIG. 4 is a diagram illustrating an output example of an inefficient block and an inefficient instruction according to the first embodiment. FIG. 10 is a diagram showing an example of a source program according to the second embodiment. The figure which shows the example of the source program in which the message which concerns on Embodiment 2 was inserted. FIG. 9 is a flowchart showing a processing procedure according to the second embodiment. The figure which shows the example of the correspondence table of the source program which concerns on Embodiment 2, and a binary code. FIG. 3 is a diagram illustrating a configuration example of an instruction execution analysis apparatus according to the first embodiment. FIG. 4 is a diagram illustrating a configuration example of an instruction execution analysis apparatus according to a second embodiment. FIG. 3 is a diagram illustrating a hardware configuration example of an instruction execution analysis apparatus according to the first and second embodiments.

In the first embodiment and the second embodiment, for example, in a high-performance information processing apparatus, a cache memory block includes a mixture of frequently accessed and low-accessed blocks, and the cache memory cannot be efficiently used. In the case where the original performance of the processing device cannot be exhibited, the cause will be clarified and a method for instructing the correction location of the source program for performance improvement will be described.
More specifically, the core part of the present method, that is, up to extracting the inefficient instruction from the binary code is shown in the first embodiment, and an example in which the core part is actually applied, that is, the source program is shown. An example of instructing a correction location is shown in the second embodiment.

Embodiment 1 FIG.
The core part of the above method will be described with reference to FIGS.
FIG. 1 shows an overall flow of the instruction execution analysis method according to the present embodiment.
2 and 4, important components in the flow shown in FIG. 1 will be described.
FIG. 3 adds a description of the specific elements in FIG.
FIG. 10 shows a configuration example of an instruction execution analysis apparatus that realizes the instruction execution analysis method shown in FIG.

  FIG. 1 is an overall flow of the instruction execution analysis method according to the present embodiment.

Reference numeral 1 denotes input data, which are a binary code and an execution environment.
The execution environment refers to initial data or data that changes due to external factors during execution.
2 is an inefficient block extraction process, and 3 is an inefficient instruction extraction process.
An inefficient block refers to a block in which the use efficiency of the entire block is low because only a part of data is frequently used for one cache block and the other part is hardly used.
An inefficient instruction refers to an instruction that is a cause for generating an inefficient block.
As shown in FIG. 2, the inefficient block extraction process 2 is roughly divided into a memory access count measurement process and an inefficient block determination process.
As shown in FIG. 4, the inefficiency instruction extraction process 3 is broadly divided into an inefficient block access count measurement process and an inefficient instruction determination process.
Details of FIGS. 2 and 4 will be described later.
Reference numeral 4 denotes output data, which is a list of inefficient instructions and information on inefficient instructions.
FIG. 5 shows a specific output example.
Details of FIG. 5 will be described later.

FIG. 10 shows a configuration example of the instruction execution analysis apparatus 100 that realizes the instruction execution analysis method shown in FIG.
The instruction execution analysis apparatus 100 is, for example, a tool (instruction execution analysis tool) installed in the information processing apparatus.

In the instruction execution analysis apparatus 100, the simulation unit 101 performs instruction execution simulation using the binary code and the execution environment 200.
More specifically, the simulation unit 101 simulates a processor device such as a CPU (Central Processing Unit) and moves to a main memory device (for example, a main memory device of an information processing device in which the instruction execution analysis device 100 is mounted). The memory access is executed to simulate the execution of the instruction of the binary code.
The main memory device is divided into a plurality of memory blocks corresponding to the number of cache blocks of the cache memory included in the processor device.
The simulation unit 101 performs processes 203, 204, 206, and 207 in FIG. 2 and processes 303, 304, 307, and 308 in FIG.

When there is a start instruction 300, the inefficient block extraction unit 102 performs the inefficient block extraction process 2 in FIG.
More specifically, the inefficient block extraction unit 102 analyzes the state of memory access to the main memory device in the simulation of the simulation unit 101, and based on the analysis result, among the plurality of memory blocks in the main memory device A memory block whose memory access target is biased toward a part of the data in the memory block is extracted as an inefficient block.

The inefficient instruction extraction unit 103 performs the inefficient instruction extraction process 3 of FIG. 1 and outputs a list of inefficient instructions and information 400 related to the inefficient instructions.
More specifically, the inefficient instruction extraction unit 103 sets an instruction that satisfies a predetermined condition among instructions that cause memory access to the inefficient block extracted by the inefficient block extraction unit 102 as an inefficient instruction. Extract.
Further, a display device (not shown) is connected to the instruction execution analysis apparatus 100, and the inefficient instruction extraction unit 103 performs information on the extracted inefficient instruction and the address of the inefficient instruction as shown in FIG. Are output to the display device as a list of inefficient instructions and information 400 related to the inefficient instructions.

In the inefficient block extraction unit 102, the memory access measurement unit 1021 performs processing (measurement processing of the number of memory accesses) 201, 202, and 205 in FIG.
The inefficient block determination unit 1022 performs processing (inefficiency block determination processing) 208 to 212 in FIG. 2 described later.

In the inefficient instruction extraction unit 103, the inefficient block access measurement unit 1031 performs processing 301, 302, 305, and 306 (measurement of the number of accesses to the inefficient block) in FIG.
The inefficient instruction determination unit 1032 performs processing (inefficiency instruction determination processing) 309 to 312 in FIG. 4 to be described later.

FIG. 2 shows a flow of the inefficient block extraction process 2 of FIG.
The process consists of steps 201 to 212, which can be roughly divided into two processes. The first half 201 to 207 is the memory access count measurement, and the second half 208 to 212 is the inefficient block determination flow. Yes.
In the following, the instruction execution analysis method shown in FIG. 1 will be described as an example in which the instruction execution analysis apparatus 100 shown in FIG. 10 is used.

  The first half (201 to 207) is intended to simulate instruction execution by a simulator (simulation unit 101 in FIG. 10) and measure the number of memory accesses.

  In 201, the memory access measuring unit 1021 initializes the memory access counter MC [Addr] for all addresses (Addr), that is, clears it to zero.

  In 202, the memory access measurement unit 1021 initializes the instruction pointer (IP) to an initial value. That is, IP indicates the address of the instruction to be executed first.

In 203, the simulation unit 101 fetches an instruction (Inst) from the address indicated by the IP.
In general, since one instruction is not necessarily one byte, the number of bytes necessary for composing the instruction enters Inst.

In 204, the simulation unit 101 simulates an instruction (Inst).
The simulation unit 101 internally implements the same internal resources (arithmetic unit, register, cache memory, etc.) as a real processor device by software, stores intermediate states in these resources, and performs various processing, thereby enabling real processing. Produces the same state as the processor unit.

In 205, the memory access measuring unit 1021 updates the access count of the corresponding address (Addr) when there is a memory access to the main memory device in executing the instruction (Inst).
Specifically, 1 is added to MC [Addr].

  In 206, the simulation unit 101 determines whether instruction execution has been completed. Various conditions such as the number of execution instructions, the number of execution cycles, the execution of a specific instruction, and the arrival of an IP at a specific address can be considered as termination conditions, but they are not specified in this specification.

In 207, the simulation unit 101 updates the instruction pointer (IP) to a value indicating the next instruction.
If the executed instruction is not a branch instruction, the new IP is a value obtained by adding the instruction length to the old IP.
In the case of a branch instruction, IP indicates a branch destination address.

  The loop from 203 to 207 is repeated until the end condition 206 is satisfied. When the end condition 206 is satisfied, the simulation ends and the measurement of the number of memory accesses is completed.

  Next, the second half (208 to 212) inefficient block determination processing will be described.

  In 208, the inefficient block determination unit 1022 initializes the block number (N) to 0.

In 209, the inefficient block determination unit 1022 calculates the number of bytes with high access frequency and the number of low bytes within the block.
The number of bytes with high access frequency is calculated in the array BA_High [N], and the number of bytes with low access frequency is calculated in the array BA_Low [N].
Details will be described with reference to FIG.

In 210, the inefficient block determination unit 1022 determines whether or not the block is an inefficient block.
When there are bytes with high access frequency and there are many bytes with low access frequency, it is determined that the block is inefficient.
Specifically, BA_High [N] ≧ 1 and BA_High [N] ≧ BlockSize × JudgeRatio.
JudgeRatio is a parameter for changing the judgment criterion and can take a value from 0 to 1. For example, if 0.5 is specified, more than half of all the blocks are low-frequency accesses and high-frequency access is 1 When there are more than bytes, it is determined as an inefficient block.
If it is an inefficient block, the inefficient block determination unit 1022 sets 1 to the array NE [N] indicating that the block N is inefficient (Not Efficiency), and otherwise sets 0.

  In 211, the inefficient block determination unit 1022 confirms whether or not the above processing has been performed on all the blocks. If the processing has been performed, the processing is completed. Otherwise, the block number N is set in 212. 1 is added and updated, the process returns to step 209, and the processes from 209 to 212 are repeated.

  With the above processing, an array NE [] indicating inefficient blocks is obtained for all blocks.

Here, the calculation method of the number of bytes with high access frequency and the number of low bytes within the block at 209 will be described with reference to FIG.
The purpose of the process 209 in FIG. 2 is to obtain an array BA_High [N] and an array BA_Low [N] of the block N.
The process 209 in FIG. 2 includes seven steps 2091 to 2097.

In 2091, the inefficient block determination unit 1022 initializes the array BA_High [N] and the array BA_Low [N] to 0.
In 2092, the inefficient block determination unit 1022 calculates thresholds ThH and ThL.
The threshold ThH is a threshold for determining whether or not the access frequency is high, and the threshold ThL is a threshold for determining whether or not the access frequency is low.
These threshold values can be given as external parameters when the behavior of the program is clear, but it is generally difficult to have clear information externally so as to determine the threshold values.
Therefore, the threshold value is created according to the internal operation result.
Specifically, for a block, a sufficiently large value is set to ThH, and a sufficiently small value is set to ThL with respect to the average memory access count (AverageMC).
In this example, ThH is four times the average memory access, and ThL is half the average memory access.
AverageMC is obtained by dividing the total number of memory accesses (MC [Addr] (where Addrεblock N)) of the memory block (memory block N) by the number of bytes (BlockSize) of the block.

  In 2093, the inefficient block determination unit 1022 initializes an address (Addr) and a counter (I), which are variables used in the following loop.

In 2094, the inefficient block determination unit 1022 performs threshold determination of the number of accesses for each byte.
If the memory access count MC [Addr] is greater than or equal to the threshold ThH, 1 is added to BA_High [N].
If the memory access count MC [Addr] is less than or equal to the threshold ThL, 1 is added to BA_Low [N].

  In 2095, the inefficient block determination unit 1022 adds 1 to the counter value (I) and updates it.

In 2096, the inefficient block determination unit 1022 determines the end of the loop.
That is, when the counter (I) is equal to the number of bytes (BlockSize) of the block, this processing is terminated.
Otherwise, the inefficient block determination unit 1022 adds 1 to the address (Addr) in 2097, returns to 2094, and repeats the processing of 2094 to 2097 until the end condition is satisfied.

  When the above loop ends, the array BA_High [N] and the array BA_Low [N] are respectively input with the high access frequency and the low access frequency bytes.

FIG. 4 shows a flow of the inefficiency instruction extraction process 3 of FIG.
The process consists of 301 to 312 steps, which can be roughly divided into two processes. The first half 301 to 308 is the number of accesses to the inefficient block, and the second half 309 to 312 is the inefficient instruction determination. It is a flow.
The first half (301 to 308) is intended to simulate instruction execution by a simulator (simulation unit 101 in FIG. 10) and measure the number of accesses to inefficient blocks.

  In 301, the inefficient block access measuring unit 1031 initializes the inefficient access counter MC_InstAC [IP] for each instruction for all instruction pointers (IP), that is, clears it to zero.

In 302, the inefficient block access measurement unit 1031 initializes the instruction pointer (IP) to an initial value.
That is, IP indicates the address of the instruction to be executed first.

  In 303, the simulation unit 101 fetches an instruction (Inst) from the address indicated by the IP.

  In 304, the simulation unit 101 simulates an instruction (Inst) with an internal simulator.

In 305, if the inefficient block access measuring unit 1031 has memory access to the main memory device in executing the instruction (Inst), the inefficient block access measuring unit 1031 searches whether the corresponding address (Addr) is an inefficient block.
Specifically, since the quotient (integer value) of Addr / BlockSize is the block number N, it can be determined whether or not the block is an inefficient block by reading the array NE [N] obtained by the inefficient block extraction.
When NE [N] = 1, the variable NoEfficiency = 1 is set since it is an inefficient block, and when NE [N] = 0, the variable NoEffectiveness = 0 is set because the block is not an inefficient block.

  In 306, the inefficient block access measuring unit 1031 updates the inefficient access counter NE_InstAC [IP] for each instruction by adding 1 if the inefficient block is accessed.

In 307, the simulation unit 101 determines whether the instruction execution is completed.
Various conditions such as the number of execution instructions, the number of execution cycles, the execution of a specific instruction, and the arrival of an IP at a specific address can be considered as termination conditions, but are not specified in this specification.

In 308, the simulation unit 101 updates the instruction pointer (IP) to a value indicating the next instruction.
If the executed instruction is not a branch instruction, the new IP is a value obtained by adding the instruction length to the old IP.
In the case of a branch instruction, IP indicates a branch destination address.

The loop from 303 to 308 is repeated until the end condition of 307 is satisfied.
When the end condition 307 is satisfied, the simulation ends and the measurement of the number of memory accesses is completed.

  Next, the second half (309 to 312) inefficient block determination processing will be described.

In 309, the inefficient instruction determination unit 1032 sets the minimum value of the instruction storage address to Addr.
This value is system-dependent, but 0 is set in this embodiment.

At 310, the inefficient instruction determination unit 1032 determines an inefficient instruction.
If the inefficient access counter NE_InstAC [Addr] for each instruction is greater than or equal to the threshold Th_NE_Inst, it is determined that the instruction is inefficient, and 1 is set in the array NE_Inst [Addr] representing the result, and 0 is set if the instruction is not inefficient. .
The threshold Th_NE_Inst is given from the outside of the system according to the purpose.
If you want to know all the instructions that are accessing inefficient blocks, give Th_NE_Inst = 1, and if you want to know more refined information, give Th_NE_Inst a large value.

In 311, the inefficient instruction determination unit 1032 determines the end of the loop.
That is, it is checked whether or not the maximum value of the instruction storage address has been reached. If it has been reached, this processing ends.
Otherwise, at 312, the instruction storage address is updated by 1 and the process returns to 310 to repeat the processes of 310 to 312.

  When the above processing is completed, an array NE_Inst [] indicating whether or not the instruction is an inefficient instruction and an array NE_Inst_AC [] indicating the number of times the instruction has accessed the inefficient block are obtained.

FIG. 5 shows an output example.
In this example, the address Addr, the instruction Inst = Mem [Addr], and the number of accesses to the inefficient block Ne_Inst_AC [Addr] are displayed for Addr where NE_Inst [Addr] = 1.

As described above, in the present embodiment, in the simulation, a memory block whose memory access target is biased toward a part of the data in the memory block is extracted as an inefficient block, and a memory access to the inefficient block is generated. Are extracted as inefficient instructions.
Then, as illustrated in FIG. 5, since the extracted inefficient instruction is displayed together with the address of the inefficient instruction, it is possible to prevent data with high access frequency and low data from being mixed in the same block of the cache memory, The utilization efficiency of the cache memory can be improved.

As described above, in the present embodiment,
An instruction execution analyzer having the following means has been described.
(A) means for inputting a binary code of a program corresponding to a specific processor and an execution environment;
The execution environment refers to initial data or data that changes due to external factors during execution.
(B) means for simulating the execution of instructions of the processor;
When accessing the memory, this processor is premised on having a cache memory for shortening the execution time.
(C) means for extracting inefficient blocks in instruction memory access;
An inefficient block refers to a block in which the use efficiency of the entire block is low because only a part of data is frequently used for one cache block and the other part is hardly used.
(D) means for extracting inefficient instructions;
An inefficient instruction refers to an instruction that is a cause of generation of the inefficient block.

In the present embodiment, as an implementation method of the inefficient block extraction means,
(A) means for simulating execution of instructions of the processor;
(B) means for measuring the number of memory accesses;
(C) means for measuring the number of high-frequency accesses to the bytes in the block;
(D) means for measuring the number of infrequent accesses to the bytes in the block;
(E) The means for determining whether the corresponding block is inefficient or not using the number of bytes of high-frequency access and the number of bytes of low-frequency access has been described.

Further, in the present embodiment, the instruction execution analysis apparatus provided with the following means has been described.
(A) means for calculating a threshold value for determining whether or not there is a high-frequency access;
(B) A means for calculating a threshold for determining whether or not the access is infrequent.

Further, in this embodiment, as an implementation method of the inefficient instruction extraction means,
(A) means for simulating execution of instructions of the processor;
(B) means for measuring the number of accesses to the inefficient block for each instruction;
(C) The means for comparing the number of accesses to the inefficient block with the threshold for all instructions has been described.

Embodiment 2. FIG.
Next, a method for more effectively using the instruction execution analysis method shown in the first embodiment will be described.
When the user actually uses the instruction execution analysis method according to the first embodiment, it is desirable that instructions and hints are directly written in the source program from the format shown in FIG.

For example, consider a source program as shown in FIG.
This program describes only the C language grammar that is relevant to the present embodiment.
In FIG. 6, a program name is defined on the first line, and variables and arrays are defined on the second line.
There are three arrays, a, b, and c, and the number of elements is 10,000.
A loop is constituted by the control variable i from the third line to the sixth line, and the array b and the array c are added to the array a and assigned.
At this time, as shown in the fourth row, the index j of the array b is cut off the first digit of the variable i and takes only a multiple of 10.
Therefore, the array b has an inefficient block with a different number of accesses for each element.
On the other hand, array a and array c are efficient blocks.

FIG. 7 is an example of a source program with inefficient instruction marking.
In the program of FIG. 6, the message / * reference to the array b [j] is inefficient in the sixth line is inserted.
With such a message, the user knows that the memory reference of b [j] in the expression on the fifth line is inefficient, and this arrangement should be improved.
For example, if the array b is defined as the minimum necessary array (b [1000]) and j = int (i / 10), it can be easily imagined that the utilization efficiency of the array b [j] increases.
Generally, when the data size is reduced in this way, the utilization efficiency of the cache memory is improved and the performance of the system is improved.

FIG. 8 illustrates a flow for realizing the above.
In the figure, 11 is a source program, for example, as shown in FIG.
Reference numeral 12 denotes a compiler and a linker.
13 is a binary code.
Reference numeral 14 denotes one of the linker outputs, which is a table (hereinafter referred to as a correspondence table) for associating a source program with a binary code, for example, as shown in FIG.
Reference numeral 15 denotes an execution environment.
Reference numeral 2 denotes an inefficient block extraction process.
Reference numeral 3 denotes inefficiency instruction extraction processing.
4 is a list of inefficient instructions.
5 is a process for linking inefficient instructions to the source program.
Reference numeral 6 denotes a source program with inefficient instruction marking, for example, as shown in FIG.

FIG. 11 shows a configuration example of the instruction execution analysis apparatus 100 according to the present embodiment.
11, elements having the same reference numerals as those in FIG. 10 are the same as those in FIG.
The source program processing unit 104 performs a process 5 for linking the inefficient instruction to the source program in FIG. 8 and inserts a message as shown in FIG. 7 into the source program.
That is, the source program processing unit 104 specifies the position where the inefficient instruction is described in the binary code source program 600 in which the instruction to be simulated is described as the inefficient instruction description position, and the inefficient instruction description A message notifying that the instruction described in the inefficient instruction description position is an inefficient instruction is inserted at the position.

  The source program / binary code correspondence table 500 corresponds to the source program / binary code correspondence table 14 of FIG. 8, and is shown in FIG. 9, for example.

  The source program 600 corresponds to the source program 11 in FIG.

  The source program 700 with inefficient instruction marking corresponds to the source program 6 with inefficiency instruction marking in FIG. 8 and is, for example, shown in FIG.

  Hereinafter, processing according to the present embodiment will be described with reference to FIGS.

When 11 source programs are processed by 12 compilers and linkers, executable binary code 13 and correspondence table 14 are generated.
When the binary code 13 and the execution environment 15 are input to the inefficient block extraction process 2 (inefficient block extraction unit 10), a list of inefficient blocks is output as described in the first embodiment.
When the list of inefficient blocks is input to the inefficient instruction extraction process 3 (inefficient instruction extraction unit 103), the inefficient instruction list 4 is output as described in the first embodiment.
The inefficiency instruction list 4 and the correspondence table 14 are input to the inefficiency instruction source program linking process 5 (source program processing unit 104), whereby the inefficiency instruction marked source program 6, that is, in FIG. A source program like this is output.
The correspondence table 14 is specifically as shown in FIG. 9 and describes information such as the line number of the source program, the address of the corresponding instruction, the instruction and the variable accessed by the instruction.
The source program processing unit 104 finds the instruction address listed in the inefficient instruction list (FIG. 5) in the correspondence table (FIG. 9) and searches for the line number and variable name, thereby correcting the source program correction line number. And find the variable being accessed with the inefficient instruction.
In this example, there is an instruction address = 1000H in the first line of the table of FIG. 5, so the instruction address = 1000H is searched for in the correspondence table of FIG. 9, the source program line number at that time is the fifth line, and the variable name is It can be seen that this is an array b [j].
Based on this information, the source program processing unit 104 can generate FIG. 7 by inserting a message after the fifth line in FIG. 6 which is the inefficient instruction description position.

  As described above, according to the present embodiment, it is possible to present, to the user, a correction location for improving the use efficiency of the cache memory in the source program.

As described above, in this embodiment, the instruction execution analysis apparatus including the following means in addition to the configuration of the first embodiment has been described.
(A) Means for associating inefficient instructions with the source program based on the correspondence table (linker output) between the source program and the binary code,
(B) Means for marking variable names of source programs linked to inefficient instructions.

Finally, a hardware configuration example for realizing the instruction execution analysis apparatus 100 shown in the first and second embodiments will be described.
FIG. 12 is a diagram illustrating an example of hardware resources for realizing the instruction execution analysis apparatus 100 illustrated in the first and second embodiments.
Note that the configuration in FIG. 12 is merely an example of a hardware configuration, and the instruction execution analysis apparatus 100 is not limited to the configuration described in FIG. 12 and may be realized by other configurations.

In FIG. 12, the instruction execution analysis apparatus 100 includes a CPU 911 (also referred to as a central processing unit, a central processing unit, a processing unit, an arithmetic unit, a microprocessor, a microcomputer, and a processor) that executes a program.
The CPU 911 is connected to, for example, a ROM (Read Only Memory) 913, a RAM (Random Access Memory) 914, a communication board 915, a display device 901, a keyboard 902, a mouse 903, and a magnetic disk device 920 via a bus 912. Control hardware devices.
Further, the CPU 911 may be connected to an FDD 904 (Flexible Disk Drive), a compact disk device 905 (CDD), a printer device 906, and a scanner device 907. Further, instead of the magnetic disk device 920, a storage device such as an SSD (Solid State Drive), an optical disk device, or a memory card (registered trademark) read / write device may be used.
The RAM 914 is an example of a volatile memory. The storage media of the ROM 913, the FDD 904, the CDD 905, and the magnetic disk device 920 are an example of a nonvolatile memory. These are examples of the storage device.
A communication board 915, a keyboard 902, a mouse 903, a scanner device 907, an FDD 904, and the like are examples of input devices.
The communication board 915, the display device 901, the printer device 906, and the like are examples of output devices.

The communication board 915 is connected to the network.
For example, the communication board 915 is connected to a LAN (local area network), the Internet, a WAN (wide area network), a SAN (storage area network), and the like.

The magnetic disk device 920 stores an operating system 921 (OS), a window system 922, a program group 923, and a file group 924.
The programs in the program group 923 are executed by the CPU 911 using the operating system 921 and the window system 922.

The RAM 914 temporarily stores at least part of the operating system 921 program and application programs to be executed by the CPU 911.
The RAM 914 stores various data necessary for processing by the CPU 911.

The ROM 913 stores a BIOS (Basic Input Output System) program, and the magnetic disk device 920 stores a boot program.
When the instruction execution analyzer 100 is activated, the BIOS program in the ROM 913 and the boot program in the magnetic disk device 920 are executed, and the operating system 921 is activated by the BIOS program and the boot program.

  The program group 923 stores programs that execute the functions described as “˜unit” and “˜means” in the description of the first and second embodiments. The program is read and executed by the CPU 911.

In the file group 924, in the description of the first and second embodiments, “determination of”, “simulation of”, “calculation of”, “search of”, “measurement of”, “update of” ”,“ Setting of ”,“ processing of ”,“ insertion of ”,“ selection of ”,“ input of ”,“ output of ”, etc. Data, signal values, variable values, and parameters are stored as items of “˜file” and “˜database”.
The “˜file” and “˜database” are stored in a recording medium such as a disk or a memory.
Information, data, signal values, variable values, and parameters stored in a storage medium such as a disk or memory are read out to the main memory or cache memory by the CPU 911 via a read / write circuit.
The read information, data, signal value, variable value, and parameter are used for CPU operations such as extraction, search, reference, comparison, calculation, calculation, processing, editing, output, printing, and display.
Information, data, signal values, variable values, and parameters are stored in the main memory, registers, cache memory, and buffers during the CPU operations of extraction, search, reference, comparison, calculation, processing, editing, output, printing, and display. It is temporarily stored in a memory or the like.
In addition, the arrows in the flowcharts described in the first and second embodiments mainly indicate input / output of data and signals.
Data and signal values are recorded on a recording medium such as a memory of the RAM 914, a flexible disk of the FDD 904, a compact disk of the CDD 905, a magnetic disk of the magnetic disk device 920, other optical disks, a mini disk, and a DVD.
Data and signals are transmitted online via a bus 912, signal lines, cables, or other transmission media.

Further, in the description of the first and second embodiments, what is described as “to part” and “to means” may be “to circuit”, “to device”, and “to device”. It may be “˜step”, “˜procedure”, “˜processing”.
That is, the “instruction execution analysis method” according to the present invention can be realized by the steps, procedures, and processes shown in the flowcharts described in the first and second embodiments.
In addition, what is described as “˜unit” and “˜means” may be realized by firmware stored in the ROM 913.
Alternatively, it may be implemented only by software, or only by hardware such as elements, devices, substrates, and wirings, by a combination of software and hardware, or by a combination of firmware.
Firmware and software are stored as programs in a recording medium such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, and a DVD.
The program is read by the CPU 911 and executed by the CPU 911.
That is, the program causes the computer to function as “˜unit” and “˜means” of the first and second embodiments. Alternatively, the procedures and methods of “to part” and “to means” of the first and second embodiments are executed by a computer.

As described above, the instruction execution analysis apparatus 100 according to the first and second embodiments includes a CPU as a processing device, a memory as a storage device, a magnetic disk, a keyboard as an input device, a mouse, a communication board, and a display device as an output device, This is realized by a computer including a communication board.
As described above, the functions indicated as “˜unit” and “˜means” are realized by using these processing devices, storage devices, input devices, and output devices.

  DESCRIPTION OF SYMBOLS 100 Instruction execution analyzer, 101 Simulation part, 102 Inefficient block extraction part, 103 Inefficient instruction extraction part, 104 Source program processing part, 1021 Memory access measurement part, 1022 Inefficient block determination part, 1031 Inefficiency block access measurement part 1032 Inefficient instruction determination unit.

Claims (10)

Analyzing the status of memory access to the main memory device in a simulation in which a memory access to the main memory device is executed and executing an instruction, and based on the analysis result, out of a plurality of memory blocks in the main memory device An inefficient block extraction unit that extracts a memory block whose memory access target is biased toward some data in the memory block as an inefficient block;
An inefficient instruction extracting unit that extracts an instruction that satisfies a predetermined condition as an inefficient instruction among the instructions that have generated memory access to the inefficient block extracted by the inefficient block extracting unit; Instruction execution analysis device. The instruction execution analyzer is connected to a display device,
The inefficient instruction extraction unit includes:
The instruction execution analysis apparatus according to claim 1, wherein the extracted inefficient instruction is output to the display device together with an address of the inefficient instruction. The inefficient block extraction unit includes:
3. The instruction execution analysis apparatus according to claim 1, wherein an inefficient block is extracted from a plurality of memory blocks corresponding to the number of cache blocks of a predetermined cache memory. The inefficient block extraction unit includes:
For each memory block, among the data in the memory block, extract high access data with high access frequency and low access data with low access frequency during the simulation,
4. The instruction execution analysis apparatus according to claim 1, wherein inefficient blocks are extracted based on the number of high access data and the number of low access data in each memory block. The inefficient block extraction unit includes:
An extraction criterion for extracting high access data and an extraction criterion for extracting low access data are derived based on an average number of memory accesses in the plurality of memory blocks during the simulation. The instruction execution analysis apparatus according to claim 4. The inefficient instruction extraction unit includes:
The state of memory access to the main memory device in the simulation in which the memory access to the main memory device is executed and the instruction is executed is analyzed, and the memory access to the inefficient block is generated based on the analysis result 6. The instruction according to claim 1, wherein an instruction is specified, and an instruction that has generated a predetermined number of memory accesses to the inefficient block is extracted as an inefficient instruction among the specified instructions. Instruction execution analyzer. The instruction execution analyzer further includes:
The position where the inefficient instruction extracted by the inefficient instruction extracting unit is described as the inefficient instruction description position in the binary code source program in which the instruction executed in the simulation is described, and the source A source program processing unit for inserting a notification message for notifying that an instruction described in the inefficient instruction description position is an inefficient instruction at an inefficient instruction description position in the program. The instruction execution analyzer according to any one of 1 to 6. The source program processing unit
A notification message notifying that the setting of the variable included in the instruction described in the inefficient instruction description position in the source program is inefficient is inserted into the inefficient instruction description position in the source program. The instruction execution analysis apparatus according to claim 7, wherein: Computer
Analyzing the status of memory access to the main memory device in a simulation in which a memory access to the main memory device is executed and executing an instruction, and based on the analysis result, out of a plurality of memory blocks in the main memory device An inefficient block extraction step for extracting a memory block whose memory access target is biased toward partial data in the memory block as an inefficient block;
The computer is
An inefficiency instruction extraction step for extracting, as an inefficiency instruction, an instruction that satisfies a predetermined condition among the instructions that have caused memory access to the inefficiency block extracted in the inefficiency block extraction step; Instruction execution analysis method. Analyzing the status of memory access to the main memory device in a simulation in which a memory access to the main memory device is executed and executing an instruction, and based on the analysis result, out of a plurality of memory blocks in the main memory device An inefficient block extraction step for extracting a memory block whose memory access target is biased toward partial data in the memory block as an inefficient block;
Causing the computer to execute an inefficiency instruction extraction step of extracting, as an inefficiency instruction, an instruction that satisfies a predetermined condition among the instructions that have generated memory access to the inefficiency block extracted in the inefficiency block extraction step. A program characterized by

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