JP2006285430A - Cpu memory access analysis device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output a CPU memory access state with a low band width without influencing the behavior of a system so as to optimize processing speed of software by means of CPU memory access analysis in the system LSI. <P>SOLUTION: The system LSI is provided with; a cache access detection means which detects a cache mishit signal; a process change detection means which detects the change of a process; an output control means which controls an output selection means so that process change information and cache mishit information may be each outputted to the outside of the system LSI when it receives process change signals and cache mishit signals, respectively; and the output selection means which generates the process change information or the cache mishit information according to the output control means to output it to the outside of the system LSI. The system LSI outputs a memory access state at the time of the cache mishit as a virtual address correlated with a process ID. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a CPU memory access analysis device that can improve software processing speed in a system LSI such as a SoC (System On Chip) composed of a CPU, a memory, and other peripheral circuits.

  The CPU processing speed is improved at an annual rate of 10%, but the improvement rate of the memory processing speed is lower than that of the CPU. As a result, penalties for memory access are increasing year by year.

  In order to analyze the memory access of the CPU, it is only necessary to extract the cache access state of the CPU, and the measurement method includes measurement by a simulator and measurement by an actual machine.

  As a conventional method for measuring CPU memory access by a simulator, there is a method of extracting the memory access state by simulating the operation of the CPU to be measured by software.

  As a conventional method for measuring CPU memory access by a real machine, an address and data at the time of a cache miss hit are obtained from the CPU external bus, the number of miss hits is counted up for each cache entry corresponding to the address, and the value is mainly used. There are a method of holding in memory, a method of collecting the number of miss hits by hardware, etc. by software using interrupts and holding it in the main memory, or a method of outputting to the outside (for example, patent document) 1). FIG. 10 shows a conventional CPU memory access analysis method described in Patent Document 1. In FIG.

In FIG. 10, the address output from the CPU 200 to the address bus outside the CPU at the time of a cache miss hit is acquired by the access address storage means 110. The address acquired by the access address storage means 110 is compared by the comparison means 140 to determine whether it is within the address area preset by the comparison address storage means 130. When the comparison unit 140 detects a match, the control unit 180 notifies the control unit 180, and the control unit 180 uses the lower address extraction unit 150 and the upper address storage unit 160 from the entry in the cache miss address distribution table 310 on the main memory. The counter value is read out, 1 is added to the value by the adding means 170, and the result is written back to the original entry. As a result, the cache miss distribution is output to the cache miss address distribution table 310.
Japanese Patent No. 2790119

  However, the CPU memory access analysis method by the simulator has a problem that the measurement time is increased and the CPU peripheral circuit is modeled, which is different from the operation in the actual system. Further, in the conventional analysis method using a real machine such as Patent Document 1, system resources (CPU, bus, or main memory) are consumed to extract the CPU memory access state, thereby hindering the actual operation of the system. Had problems. Furthermore, in order to improve the processing speed of software using the measurement result of CPU memory access, it is necessary to measure a high-speed CPU memory access operation on the order of program execution time much longer than the CPU operating frequency. It is difficult to mount an analysis method using a conventional actual machine such as Patent Document 1 on a system LSI because the memory capacity to be mounted is limited and the number of external output terminals is limited.

  The present invention solves the above-described conventional problems, and outputs a CPU memory access state necessary for improving the software processing speed to the outside of the system LSI at a low bit rate without affecting the system behavior. The purpose is to provide.

  In order to solve the conventional problem, a CPU memory access analysis device according to the present invention includes, in a system LSI, a cache access detection unit that detects a cache miss hit signal, a process switching detection unit that detects process switching, According to the output control means for controlling to output the process switching information when the process switching signal is received, and to output the cache miss information to the outside of the system LSI when the cache miss hit signal is received. It has an output selection means for generating process switching information or cache miss hit information and outputting it to the outside of the system LSI, and outputs the memory access state at the time of the cache miss hit as a virtual address associated with the process ID. And

  With this configuration, it is possible to output the CPU memory access status with a small bandwidth without affecting the system behavior, optimizing the bottleneck in terms of software performance, and reducing the overall system processing speed. Can be improved.

  According to the CPU memory access analysis device of the present invention, the CPU memory access state can be extracted at a low bit rate without affecting the system behavior.

  This is a mechanism in which the CPU memory access analyzer extracts information necessary for software optimization from the memory access state acquired from the CPU, that is, cache miss hit information and process switching information, and outputs them intermittently. By being built in the system LSI.

  Further, according to the CPU memory access analysis device of the present invention, the output bit rate is reduced, so that it is possible to perform memory access analysis on a macro order compared to the CPU operating frequency of program execution time, and cache The detailed information on the miss hits makes it easy to optimize the part that is a bottleneck in terms of software processing speed.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a configuration diagram showing an example of a CPU memory access analysis apparatus according to Embodiment 1 of the present invention. A system LSI 10 shown in FIG. 1 includes a CPU memory access analysis device 100, a CPU 200, a memory 300, and a system bus 400. The CPU memory access analysis apparatus 100 includes a cache access detection unit 101, a process switching detection unit 102, an output control unit 103, and an output selection unit 104.

  Further, the CPU 200 includes a CPU core 201, an MMU (Memory Management Unit) 202, and a cache memory 203.

  In this embodiment, an OS (Operating System) 301 held in the memory 300 is operating on the CPU 200, and a plurality of processes such as a process A 302 and a process B 303 held in the memory 300 are operating on the OS 301. is doing.

  The CPU core 201 outputs a virtual address to the MMU 202 in order to fetch the instruction code from the memory. The MMU 202 converts the virtual address into a corresponding physical address, and outputs the physical address together with the cache access request signal to the cache memory 203 when the physical address is an address space to be cached. When the cache memory 203 receives a physical address from the MMU 202 by a cache access request signal, the cache memory 203 determines whether or not an instruction code corresponding to the physical address is held in the cache memory 203, and if the instruction code is found or if a cache hit occurs. The retained instruction code is output to the CPU core 201. When the instruction code is not found or a cache miss occurs, the CPU core 201 receives the miss hit signal output from the cache memory 203, and the cache memory 203 acquires the instruction code corresponding to the physical address from the memory 300. Wait until. At the same time, the cache memory 203 outputs the physical address to the memory 300 via the system bus 400 and obtains a corresponding instruction code. When the cache memory 204 acquires the instruction code, the CPU core 201 fetches the instruction code from the cache memory 203 again with the same physical address.

  Further, when the process operating on the OS 301 is switched from, for example, the process A 302 to the process B 303, the OS 301 writes the process ID for identifying the process B 303 in a register held by the CPU core 201, so that the process ID is stored in the MMU 201. Is output. The MMU 202 manages a virtual address space for each process based on the process ID.

  The cache access detection unit 101 detects a cache miss based on the cache access request signal output from the MMU 202 and the cache miss signal output from the cache memory 203, and outputs the cache miss signal to the output control unit 103.

  When the output control means 103 receives the cache miss hit signal, it outputs an event identifier for identifying a cache miss hit event, the value “1” to the output selection means 104, and the output selection means 104 outputs from the CPU core 201. An output control signal is output so as to select the virtual address and the event identifier.

  The output selection unit 104 outputs the virtual address and the event identifier in response to an output control signal from the output control unit 103.

  Further, the process switching detection unit 102 compares the process ID output from the MMU 202 with the process ID held by the process switching detection unit 102. If they do not match, the process switching detection unit 102 updates the held process ID with the process ID output from the MMU 202, and at the same time, the process switching signal is updated to the output control unit 103 and the output selection unit 104 is updated. Output process ID.

  When the output control means 103 receives the process switching signal, it outputs an event identifier for specifying process switching, the value “2” to the output selection means 104, and the output selection means 104 is output from the process switching detection means 102. An output control signal is output so as to select the process ID and the event identifier.

  The output selection unit 104 outputs the process ID and the event identifier in response to an output control signal from the output control unit 103.

  In this way, when a cache miss hit occurs, the CPU memory access analysis apparatus 100 outputs the virtual address output from the CPU 200 and the event identifier specifying the cache miss hit event as cache miss hit information. When process switching occurs, the switched process ID and an event identifier for identifying a process switching event are output as process switching information.

  FIG. 2 is a flowchart for explaining the operation of the output control means 103 in Embodiment 1 of the present invention.

  When the output control unit 103 receives a cache miss hit signal from the cache access detection unit 101 or a process switching signal from the process switching detection unit 102, the output control unit 103 performs event determination. If it is a cache miss hit event, the process proceeds to step S2002, and if it is a process switching event, the process proceeds to S2004 (step S2001).

  When receiving the cache miss hit event, the output control means 103 outputs an event identifier for identifying the cache miss hit event, here the value “1” to the output selection means 104 (step S2002).

  Further, the output control means 103 outputs an output control signal to the output selection means 104 so as to output the virtual address output from the CPU 100 and the event identifier output in step S2002 (step S2003).

  On the other hand, when receiving the process switching event, the output control means 103 outputs an event identifier for identifying the process switching event, here the value “2”, to the output selection means 104 (step S2004).

  Further, the output control unit 103 outputs an output control signal to the output selection unit 104 so as to output the process ID output from the process switching detection unit 102 and the event identifier output in step S2004 (step S2005).

  According to such a configuration, the memory access state is output only at the time of cache miss hit and at the time of process switching, so that the memory access state at the time of cache miss hit as shown in FIG. Can be output as a virtual address associated with the process ID. By using this result and taking statistics based on the number of cache misses as shown in FIG. 3 (b), it becomes possible to find a portion that is a bottleneck in terms of program performance. This is because the virtual address output by the CPU memory access analyzer 100 can be associated with the program code based on the map file output at the time of linking the program, the program disassembly result, or the debug information. This is because the OS 301 can associate the process ID with the process name (program name).

  In the embodiment of the present invention, the case where the CPU fetches the instruction code is shown as an example of the CPU memory access analysis device, but the same applies to the case where the CPU reads data from the memory or stores it in the memory. The memory access status can be output. Therefore, this CPU memory access analysis apparatus may be used for a Harvard cache that handles instructions and data separately, or may be used for a unified cache that handles instructions and data in the same way.

(Embodiment 2)
FIG. 4 is a block diagram showing an example of a CPU memory access analysis apparatus according to Embodiment 2 of the present invention. The system LSI 10 shown in FIG. 4 is similar to the first embodiment in that the CPU memory access analysis apparatus 100, the CPU 200, the memory 300, and the system bus 400 are provided. The memory access analysis apparatus 100 further includes an event counter 505 and a cache hit counter 506, a cache access detection unit 501 instead of the cache access detection unit 101, an output control unit 503 instead of the output control unit 103, and an output An output selection unit 504 is provided instead of the selection unit 104.

  The cache access detection unit 501 detects a cache hit or a cache miss hit based on the cache access request signal and the cache miss hit signal output from the CPU 200, and outputs a cache hit signal or a cache miss hit signal, respectively.

  When the cache hit counter 506 receives the cache hit signal, it adds 1 to the held counter and outputs the result to the output selection means 504.

  When the event counter 505 receives the cache miss hit signal, the event counter 505 increments the counter held by one. In addition, the CPU 200 can set a count threshold in the event counter 505 via the system bus 400. When the value “10” is set as the event threshold value in the event counter 505, the event counter 505 outputs an event threshold detection signal to the output control unit 503 when the cache miss hit signal is received 10 times, and resets the counter.

  The output control means 503 performs the same operation as in the first embodiment when it receives a cache miss hit signal. When a process switching signal is received, an event identifier for specifying process switching and a value “2” are output to the output selection unit 504, and the output selection unit 504 is output from the process switching detection unit 102. An output control signal is output so as to select the process ID, the event identifier, and the output value of the cache hit counter 506. Further, when the event threshold detection signal is received from the event counter 505, the event identifier for specifying the cache hit count notification event and the value “3” are output to the output selection means 504, and the output selection means 504 includes the cache hit counter. An output control signal is output so as to select the output value of 506 and the event identifier, and at the same time, the cache hit counter 506 is reset.

  The output selection unit 504 performs the same operation as in the first embodiment when a cache miss hits. At the time of process switching, the process ID, the event identifier, and the number of cache hits are output by an output control signal from the output control means 503. Further, when the cache miss hit signal appears 10 times, the cache hit count and the event identifier are output by the output control signal from the output control means 503.

  In this way, the CPU memory access analysis apparatus 100 outputs the cache miss information shown in the first embodiment when a cache miss hit occurs, and at the time of process switching, the changed process ID and process switching are performed. The event identifier to be identified and the number of cache hits until the process switching occurs after 10 cache miss hits are output as process switching information. In addition, when 10 cache miss hits occur, an event identifier that identifies the cache hit number notification event and the number of times the cache memory hit during the 10 cache miss hits are output as cache hit number notification information To do.

  According to such a configuration, the number of cache hits can be output at intervals of 10 cache miss hits, and the number of cache hits can also be output during process switching. The cache hit rate can be obtained for each.

  In the embodiment of the present invention, the example of counting the number of cache misses is shown as an example of the event counter 505, but the corresponding event is not limited to this. As another example, the event counter 505 can count the number of cache hits. In this case, a more detailed trace of the program can be obtained by outputting the event identifier that identifies the cache hit count notification event and the virtual address at the time when the threshold is reached in addition to the cache hit count. In this case, the cache hit counter 506 is unnecessary.

(Embodiment 3)
FIG. 5A illustrates an example of the cache memory trace compression method according to Embodiment 3 of the present invention. The CPU 200 includes a set associative cache memory, here, a 4-way set associative cache memory 603. The cache memory 603 includes four blocks (ways 0, 1, 2, 3), and each block includes 256 entries including a 20-bit tag and 16-byte data.

  The 32-bit virtual address output from the CPU core 201 is converted into a 32-bit physical address by the MMU 202. Here, the MMU 202 indicates that the virtual address “0x2000C1A0” has been converted to the physical address “0x800081A0”. Since the MMU 202 manages the address space as a 4 KB page, the upper 20 bits of the virtual address indicating the virtual page number are converted into the upper 20 bits of the physical address indicating the corresponding physical page number. Here, the virtual page number “0x2000C” corresponds to the physical page number “0x80008”.

  As shown in FIG. 5A, the values of bits 11 to 4 of the physical address converted by the MMU 202 are called entry addresses and are used to designate entries in each block. The upper 20 bits of the physical address are called a tag address and are used to select a block in comparison with a tag in an entry in each block. The lower 4 bits of the physical address are called a byte address and are the address of data in the entry. That is, when the cache memory 603 is accessed by the physical address “0x800081A0” and the corresponding block is not found, a miss hit occurs. In this case, in order to store the data on the memory 300 indicated by the physical address in the data part of the cache memory 603, the way 0 is determined as the block to be replaced and the refill target block, and the entry address “0x1A” of the physical address is set. The tag address “0x80008” of the physical address is stored in the tag at the indicated position.

  When the cache memory 603 is accessed with the same physical address “0x800081A0” from the cache miss hit until the data in the entry “0x1A” of the way 0 is refilled, a cache hit occurs.

  As a result, when taking a history of cache memory access addresses, if a cache miss occurs, if the physical address and the way number that was the target of refilling are saved, the way is changed until the same entry in the same block is replaced. By only outputting the number, the lower 12 bits corresponding to the entry address and byte address of the physical address, the physical address at the time of a cache hit can be obtained and the output data can be compressed.

  In FIG. 5A, when a cache miss hits, the physical address “0x800081A0” and the way number “0” are output, and at the subsequent cache hit, the lower 12 bits “0x1A0” and the way number “0” of the physical address are output. Just output.

  Furthermore, since the virtual address and the physical address have a one-to-one correspondence, the virtual address “0x2000C1A0” and the way number 0 are output when a cache miss hits, and the lower 12 bits of the virtual address “ “0x1A0” and way number 0 may be output.

  FIG. 5B is a flowchart for explaining the operation of the cache memory trace compression method according to the third embodiment of the present invention.

  When a cache hit event or a cache miss hit event is received, event determination is performed. If it is a cache hit event, the process proceeds to step S3003, and if it is a cache miss event, the process proceeds to step S3002 (step S3001).

  When the cache miss hit event is received, the virtual address and the way number to be refilled are output (step S3002).

  On the other hand, if a cache miss hit event is received, the lower address of the virtual address, here the lower 12 bits, and the way number of the hit block are output (step S3003).

  According to this method, as shown in FIG. 6, when a cache miss hits, the virtual address and the refilled way number are stored, and when the cache hit occurs, the lower 12 bits of the virtual address and the way number of the hit block are stored. Saved. At the time of a cache hit, the virtual address is obtained by referring to the virtual address at the time of the cache miss hit matching the value by searching the trace history in reverse using the lower 12 bits of the virtual address and the way number of the hit block as a key. Can be found.

  In FIG. 6, it can be seen that the virtual address at the time of hit of index 3 is “0x20000010” from the virtual address of index 0, and the virtual addresses of indexes 5 and 6 are “0x30000010” and “0x20000310”, respectively. I understand.

  Therefore, in this embodiment, if this method is used, it is possible to compress 18 bits per hit as compared with a method in which a virtual address is output every time a cache hit or a miss hit. This is because the number of hits is much larger than the number of miss hits, and 2 bits indicating the way number of the block to be refilled at the time of the miss hit can be ignored.

  In order to analyze the cause of the cache miss hit, it is important to know which entry in which block has been replaced. However, as shown in FIG. 6A, the MMU refers to the upper 22 bits of the physical address as the page address in order to perform page management every 1 KB, while the cache memory tags the upper 20 bits of the physical address. The address of the physical address referenced by the cache memory and the number of bits of the byte address are referred to by the MMU, such as the address 4 to 11 bits as the entry address and the lower 4 bits as the byte address. If the number of bits of the address other than the page number of the physical address, which is called an address, is larger than the number of bits of the address, the entry replaced at the time of a cache miss cannot be resolved by the above method of outputting a virtual address at the time of a cache miss.

  In such a case, the difference between the address composed of the entry address and the byte address and the in-page address. In FIG. 6A, the difference between the lower 12 bits and the lower 10 bits of the physical address, the 10th bit. If the 11th bit is output together with the way number and virtual address when a cache miss occurs, the problem can be solved.

  In the embodiment of the present invention, as an example of memory management of the MMU 203, an example in which page management is performed with a size of 4 KB is shown, but the page size is not limited to this. This is because the virtual address and the physical address have a one-to-one correspondence.

  Further, although the 4-way set associative cache memory 603 is shown as an example of the set associative cache memory, the number of ways is not limited thereto. Further, the entry size in the cache memory and the tag size and data size in each block are not limited to this.

(Embodiment 4)
FIG. 7 is a block diagram showing an example of a CPU memory access analysis apparatus according to Embodiment 4 of the present invention. The system LSI 10 shown in FIG. 7 is similar to the second embodiment in that it includes a CPU memory access analysis device 100, a memory 300, and a system bus 400, but includes the cache memory 603 instead of the CPU 200. The CPU 800 outputs a process ID, a virtual address, a cache access request signal, a cache miss hit signal, and a way number. Further, in the eighth embodiment, the CPU memory access analysis apparatus 100 further includes a time counter 707 instead of the event counter 505, and outputs control means 703 and output selection means 504 instead of the output control means 503. Instead, output selection means 704 is provided.

  The time counter 707 adds 1 to the counter in synchronization with a clock input from outside the system. Further, the CPU 200 can set a count threshold value in the time counter 707 via the system bus 400. In this example, since the clock of 10 MHz is input to the time counter 707 and the value “100” representing 10 microseconds is set as the threshold value, the time counter 707 outputs the output control means every 10 microseconds. A time event detection signal is output to 703, and the counter is reset.

  When receiving the process switching signal, the output control means 703 performs the same operation as in the second embodiment. When a cache miss hit signal is received, an event identifier for specifying a cache miss hit event and a value “1” are output, and the output selection unit 704 outputs a virtual address output from the CPU 200, a refill target, An output control signal is output so as to select the way number of the block and the event identifier, and when a time event detection signal is received from the time counter 707, an event for specifying a time stamp notification event The identifier and value “4” are output. Further, when the cache hit signal output from the cache access detection unit 501 is received, the output selection unit 704 outputs the lower 12 bits of the virtual address output from the CPU 200, the hit way number, and the cache hit counter 506. When the output control signal is output so as to select the output value and the event identifier, and the cache hit signal is not received, the output selection means 704 outputs the output value of the cache hit counter 506, the event identifier, The output control signal is output so that only the signal is output. At the same time, the cache hit counter 506 is reset.

  The output selection unit 704 performs the same operation as in the second embodiment at the time of process switching. When a cache miss occurs, the virtual address, the way number, and the event identifier are output by an output control signal from the output control means 703. Also, every 10 microseconds, the number of cache hits and the event identifier are output by an output control signal from the output control means 703. At the same time, when the cache hits, the lower 12 bits of the virtual address and the way Print the number.

  In this way, the CPU memory access analysis apparatus 100 outputs the process switching information shown in the second embodiment at the time of process switching, and in addition, when a cache miss occurs, the virtual address output from the CPU 200 And the refill target way number and the event identifier specifying the cache miss hit event are output as cache miss hit information. Further, when 10 microseconds have elapsed, an event identifier for specifying a time stamp notification and the number of times the cache has been hit in 10 microseconds are output as cache hit number notification information. The lower 12 bits of the output virtual address and the hit way number are output.

  FIG. 8 is a flowchart for explaining the procedure of the output control means 703 according to the fourth embodiment of the present invention.

  When the output control unit 703 receives a cache miss hit signal from the cache access detection unit 501, a process switching signal from the process switching detection unit 102, or a time event detection signal from a time counter, the output control unit 703 performs event determination. If it is a cache miss hit event, the process proceeds to step S4002, and if it is another event, the process proceeds to S4004 (step S4001).

  When receiving the cache miss hit event, the output control means 703 outputs an event identifier for identifying the cache miss hit event, here the value “1”, to the output selection means 704 (step S4002).

  Further, the output control means 703 outputs an output control signal to the output selection means 704 so as to select the virtual address and way number output from the CPU 100 and the event identifier output in step S4002 (step S4003).

  On the other hand, when the output control unit 703 receives a process switching signal or a time event detection signal, the event determination is further performed. If it is a process switching event, the process proceeds to step S4005. If a time event is detected, the process proceeds to S4007 (step S4004).

  When receiving the time event event, the output control unit 403 outputs an event identifier for identifying the process switching event, here the value “2” to the output selection unit 404 (step S4005).

  The output control unit 703 outputs an output control signal to the output selection unit 704 so as to select the process ID output from the process switching detection unit 102, the event identifier output in step S4005, and the number of cache hits output from the cache hit counter. Is output (step S4006).

  When receiving the time detection event, the output control means 403 outputs an event identifier for identifying the time stamp notification event, here the value “4”, to the output selection means 704 (step S4007).

  At this time, it is determined whether or not a cache hit signal is received from the cache access detection means 501. If it is a cache hit event, the process proceeds to step S4009, and if it is any other event, the process proceeds to S40010 (step S4008).

  When the time detection event and the cache hit event are received simultaneously, the output control means 403 outputs the lower 12 bits and way number of the virtual address output from the CPU 200, the event identifier output in step S4007, and the cache hit counter. An output control signal is output to the output selection means 704 so as to select the number of cache hits (step S4009).

  On the other hand, if the time detection event and the cache hit event are not received at the same time, an output control signal is sent to the output selection means 704 so as to select the event identifier output in step S4007 and the number of cache hits output from the cache hit counter. Is output (step S4010).

  The cache hit counter 506 is reset (step S4011).

  According to such a configuration, as shown in FIG. 9A, the compressed virtual address at the time of cache hit is output every time stamp event cycle, here, every 10 microseconds. Compared to 2, the program operation can be traced at a lower bit rate. Further, as shown in FIG. 9B, the number of cache hits is output at a cycle of 10 microseconds, and the number of cache hits is also output at the time of process switching, so that the number of cache hits can be calculated for each process. The cache hit rate in elapsed time units for each process can be obtained.

  In this embodiment, an example in which the CPU memory access analysis device is built inside the system LSI is shown, but it may be built inside the CPU.

  In order to output the memory access state to the outside of the system LSI at a low bit rate, a buffer buffer may be used on the output side of the CPU memory access analyzer.

  Further, in order to output the memory access state of a specific process, the output control means may hold the process ID in advance and output the memory access state of only the specific process.

  In addition, in order to output a memory access state for a specific address space such as a user space or a kernel space, the output control means holds in advance an address area to be analyzed, and outputs the memory access state of the specific address space. May be.

  The CPU memory access analysis apparatus according to the present invention has an effect of extracting a CPU memory access state at a low bit rate without affecting system resources, and software processing in a system LSI such as SoC (System On Chip). It is useful for optimization in terms of speed, and for purposes such as improving the processing speed of the entire system.

Configuration diagram in Embodiment 1 of the present invention Flowchart of output control means in Embodiment 1 of the present invention (A) The figure which shows the output result in Embodiment 1 of this invention (b) The statistical figure of the number of cache misses in Embodiment 1 of this invention Configuration diagram in Embodiment 2 of the present invention (A) Explanatory diagram of cache memory trace compression principle according to the third embodiment of the present invention (b) Flow chart of cache memory trace compression operation according to the third embodiment of the present invention (A) Explanatory diagram at the time of exception in the third embodiment of the present invention (b) Diagram showing the output result in the third embodiment of the present invention Configuration diagram in Embodiment 4 of the present invention Flowchart of output control means in Embodiment 4 of the present invention The figure which shows the output result in Embodiment 4 of this invention. Configuration of conventional CPU memory access analyzer

Explanation of symbols

10 System LSI
DESCRIPTION OF SYMBOLS 100 CPU memory access analyzer 101 Cache access detection means 102 Process switching detection means 103 Output control means 104 Output selection means 200 CPU
201 CPU core 202 MMU
203 Cache memory 300 Memory 301 OS
302 Process A
303 Process B
400 system bus 501 cache access detection means 503 output control means 504 output selection means 505 event counter 506 cache hit counter 603 cache memory 703 output control means 704 output selection means 707 time counter 800 CPU

Claims (7)

A system LSI including a cache memory, an MMU (Memory Management Unit), a CPU composed of a CPU core, an externally or built-in memory, and a peripheral circuit,
The system LSI includes a cache access detection means for detecting a cache hit or a miss hit by a cache miss signal output from the CPU, and
Process switching detection means for detecting that the process has been switched based on the process ID output from the CPU and updating the retained process ID;
The output selection unit is controlled by a process switching signal from the process switching detection unit or a cache miss hit signal from the cache access detection unit, and at the same time, a process switching event or a cache miss hit corresponding to these signals. Output control means for outputting an event identifier for identifying an event;
When the process is switched by the output control signal output from the output control means, the event identifier and the process ID output from the process switch detection means are selected and output as process information, and when the cache miss hits, the event By providing an identifier and an output selection means for selecting the virtual address output from the CPU and outputting it as cache miss hit information, it is possible to detect the cache miss hit without affecting the behavior of the system to be measured. A CPU memory access analyzing apparatus that outputs a memory access state as a virtual address associated with a process ID. An event counter for counting cache hit or cache miss hit events;
The output control means resets the event counter when the event counter reaches a preset threshold, outputs an event identifier that identifies a cache hit event by a cache hit signal output from the cache access detection means, 2. The CPU memory access analyzing apparatus according to claim 1, wherein the output selecting unit is controlled to output an event identifier and a virtual address output from the CPU as cache hit information. A cache hit counter that counts the number of cache hits according to a cache hit signal output from the cache access detection means;
When the event counter reaches a preset threshold, the event counter and the cache hit counter are reset by a cache hit signal output from the cache access detecting means, and an event identifier for identifying a cache hit event, The count value held by the hit counter before reset and the virtual address output from the CPU are output as cache hit information, and when a process switching notification is output from the process switching detection means, a process switching event is generated. 3. The CPU memory access analyzing apparatus according to claim 2, wherein the output selection determining unit is controlled to output an event identifier to be specified, a process ID, and a count value held by a cache hit counter. The cache memory in the CPU is a set associative method,
The virtual address output by the CPU has a one-to-one correspondence with the physical address converted by the MMU. When a cache hit occurs, the hit way number and the lower address of the physical address that uniquely determines the cache entry at the time of hit When the cache hits, the combination of the address and the physical address has a one-to-one correspondence, and the hit way number and the virtual address at the time of the hit are the same size as the lower address of the physical address. Outputs the address, and when the cache miss hits, outputs the way number to be refilled and the virtual address at the time of the miss hit. Cache memory Scan compression method. A system LSI comprising a set associative cache memory, an MMU, a CPU comprising a CPU core, an external or built-in memory, and a peripheral circuit,
The system LSI includes a cache access detection means for detecting a cache hit or a miss according to a cache miss signal output from the CPU, and
Output control means for controlling the output selection means by the output of the cache access detection means, and simultaneously outputting an event identifier for specifying a cache hit event or a cache miss hit event;
When a cache miss hit occurs, the event identifier, the virtual address output from the CPU, and the way number to be refilled are selected and output by the output control signal output from the output control means. When a cache hit occurs, the event identifier, the lower address in the virtual address at the time of the hit, and the hit way number are selected and the cache hit information is output, so that the entire virtual address is cache hit / missed. 5. The CPU memory access analysis device using the method according to claim 4, wherein the output data amount is compressed as compared with the case of outputting at the time of hit. A time counter for counting elapsed time;
The output control means controls the output selection means to reset the time counter when the time counter reaches a preset threshold value and to output an event identifier specifying a time elapsed event as time stamp information. 2. The CPU memory access analysis apparatus according to claim 1, wherein A cache hit counter that counts the number of cache hits according to a cache hit signal output from the cache access detection means;
When the time counter reaches a preset threshold value, the time counter and the cache hit counter are reset, and an event identifier for specifying a time elapsed event and a count value held by the cache hit counter before the reset are time stamped When the process switching notification is output from the process switching detection unit, the event identifier for identifying the process switching event, the process ID, and the count value held by the cache hit counter are output. 7. The CPU memory access analyzing apparatus according to claim 6, wherein the output selection determining means is controlled.

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