JPH08255494A - Non-volatile semiconductor storage device - Google Patents

Abstract

PURPOSE: To increase the speed of read operation almost without augmenting the chip size by making a set by a selector block and an adjacent block on the source line side of the selector block or the bit-line contact side and using a decoding system. CONSTITUTION: A NAND cell block is constituted of a plurality of NAND cells sharing a source line, and a plurality of the NAND cell blocks are arrayed so as to share a bit line on one end side and share a source line on the other end side. The gate line SG2 of a source-line side selector transistor is connected in common between the source-line side selector transistor and the adjacent NAND cell block. The gate line SG2 is decoded in a set, thus shortening the charge-discharge time of voltage to a source-line side selector gate, then allowing read operation at high speed without increasing the chip size.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM).

[0002]

2. Description of the Related Art A NAND cell type EEPROM capable of high integration is known as one of EEPROMs. This is to connect a plurality of memory cells in series so that their sources and drains are shared by adjacent ones, and connect them to a bit line as a unit. The memory cell usually has a FET-MOS structure in which a floating gate (charge storage layer) and a control gate are stacked. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the select gate, and the source side is also connected to the source line via the select gate. The control gates of the memory cells are continuously arranged in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows.

The data write operation is performed in order from the memory cell located farthest from the bit line. A high voltage Vpp (about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential VppM (about 10V) is applied to the control gate and the select gate of the memory cell on the bit line side. , 0 V or an intermediate potential is applied to the bit line according to the data.

When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, "1". When an intermediate potential is applied to the bit line, electron injection does not occur, so the threshold value does not change and remains negative. This state is "0".

For data erasing, the control gate connected to the memory cell to be erased is set to 0V, the bit line and the source line are set in a floating state, and the control gates and all select gates connected to the memory cell not to be erased, A high voltage of 20 V is applied to the p-type well and the n-type substrate. As a result, in the memory cell to be erased, electrons in the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

In the data read operation, the control gate of the selected memory cell is set to 0V, the control gates and the selection gates of the other memory cells are set to the power supply potential Vcc (= 5V), and whether or not a current flows in the selected memory cell. It is performed by detecting whether or not.

The bit line contact side select gate and the source line side select gate of such a NAND cell type EERROM are both formed of two wirings having different resistances which are formed in parallel with each other with an interlayer insulating film interposed therebetween. The book wirings are connected at several locations (or dozens of locations) in the memory cell array. In this select gate connection region, the distance between the two select gates that sandwich the bit line contact is relatively long. Therefore, the two select gates that sandwich the bit line contact must be connected to two wires separately. There is.

On the other hand, since the distance between the two select gates sandwiching the source line is short, it is not possible to separately perform wiring connection at the two select gates sandwiching the source line. Two select gates sandwiching the line are short-circuited, and wiring is connected as the same node. Therefore, in the NAND cell type EEPROM, the two select gates sandwiching the source line are at the same potential.

In the row decoder in such a NAND cell type EEPROM, only decode signals in block units exist as decode signals. For this reason, the SG2 node, which requires a special decoding method in which a selected block and a block adjacent to the selected block on the source line side are set as a set, is not decoded, but a method is used in which all blocks have the same potential.

During the write / read operation, the bit line contact side select gate SG1 is in the "L" state in the non-selected block, and the bit line and the memory cell are not in the non-selected block by the bit line contact side select gate. Since it is in the conductive state, no malfunction occurs in the non-selected block regardless of the voltage of the source-side selection gate SG2. In other words, since a highly reliable write / read operation can be realized, there is no problem in operation reliability even if all the source side select gate SG2 potentials in the non-selected block are the same potential as the SG2 potential in the selected block. In consideration of the above point, the method of making the source line side select gate have the same potential in all blocks has been used conventionally.

As is clear from the above description of the operation, the NA
In the ND cell type EEPROM, at the time of read operation, control gates other than the selected one control gate in the selected block, one bit line contact side selection gate in the selected block, and source line side selection in all blocks are selected. The gate is charged to the power supply voltage. Also, before the read operation is completed, the node charged to Vcc is discharged to 0V. In this case, the number of source line side select gates to be charged to the Vcc potential and discharged to 0V is several hundred to several.
Since the number is several thousand and the capacitance becomes an enormous value, there is a problem that the time required for charging / discharging the source line side select gate becomes long and the time required for read operation becomes long.

In order to shorten the time required for charging / discharging the source line side select gate, the wiring width of the lines other than those in the memory cell array among the lines used as the path for performing the charge / discharge operation of the source line side select gate. However, there is a problem in that the chip area is significantly increased by using a method such as widening the size or increasing the size of the element involved in the charging / discharging operation.

[0014]

As described above, the conventional NA is used.
In the ND cell type EEPROM, since the source line side select gates in all blocks are set to the same potential, there is a problem that the charge / discharge operation time of the source line side select gates becomes long and the read operation becomes long. . Further, in order to solve this problem, if the wiring width is increased or the element size is increased, the control circuit area and the wiring area are increased, which causes a problem that the chip area is increased.

The present invention has been made in consideration of the above circumstances, and an object thereof is to achieve an EE that enables a high-speed read operation with almost no increase in the chip area.
It is to provide a PROM.

[0016]

In order to solve the above problems, the present invention employs the following configurations.

That is, according to the present invention (claim 1), a plurality of nonvolatile memory cells are connected between a bit line and a source line,
Further, a select transistor is arranged between the memory cell and at least one of a bit line and a source line to form a block, and a plurality of the blocks share a bit line on one end side and a source line on the other end side. Non-volatile semiconductor including a memory cell array arranged as described above, a column decoder for selecting a bit line of the memory cell array, and a row decoder for selecting a word line of the memory cell and a gate line of the selection transistor In the memory device, the row decoder selects at least one of the gate lines of the source line side selection transistors and the gate lines of the bit line side selection transistors which are adjacent to each other in the block as a set. To do.

According to the present invention (claim 2), a plurality of non-volatile memory cells are connected, one end side is connected directly or via a select transistor to a bit line, and the other end side is connected directly or via a select transistor. To form a memory cell unit by connecting to a source line, and a plurality of the memory cell units are arranged so as to share the source line to form a block. A memory cell array which is arranged so as to be shared and the source line is shared on the other end side, a column decoder which selects a bit line of the memory cell array, a word line selection of the memory cell and a gate line selection of the selection transistor A non-volatile semiconductor memory device including a row decoder for performing the above, wherein the row decoder is a source line side select transistor that is adjacent between the blocks. At least one of the gate lines and the bit line side select gate lines of the transistors and selects in a set.

According to the present invention (claim 3), a plurality of non-volatile memory cells are connected in series, one end side is connected to a bit line via a selection transistor and the other end side is connected to a source line via a selection transistor. To form a memory cell unit, and a plurality of the memory cell units are arranged so as to share a source line to form a block. A memory cell array arranged so as to share the source line on the end side;
A non-volatile semiconductor memory device comprising: a column decoder for selecting a bit line of the memory cell array; and a row decoder for selecting a word line of the memory cell and a gate line of the selection transistor. The gate line of the adjacent source line side selection transistor is
The row decoder is connected in common and connected to the wiring driven by the row decoder by the same contact, and is not connected to the gate lines of the source line side select transistors other than the adjacent blocks. It is characterized in that the gate lines of the source line side select transistors adjacent to each other between the blocks are selected as one set.

The preferred embodiments of the present invention are as follows. (1) In a memory cell, a charge storage layer and a control gate are stacked on a semiconductor substrate, and electric rewriting is performed by exchanging charges between the charge storage layer and the substrate. (2) The row decoder is adjacent to each gate line (selection gate line) of the adjacent selection transistors, and the drain electrode is located on the selection gate line so that two drain lines sandwich the two selection gate lines. A first transistor having a gate electrode connected to a first word line selection signal for selecting the first word line of the first transistor and a drain electrode connected to the source electrode of the first transistor to connect two selection gate lines. A second transistor having a gate electrode connected to a second word line selection signal that selects the second word line of the two word lines in the sandwiched position. (3) When the two word lines sandwiching the gate line pair of the adjacent select transistors are not selected together, the select gate line pair sandwiched by the two word lines is in a floating state.

[0021]

In the present invention, as the decoding method of the selection transistor, since the method of decoding by selecting the selected block and the adjacent block on the source line side or the bit line side of the selected block as a set is used, the source which is charged / discharged during the read operation is used. The number of gate lines of the selection transistors on the line side or the bit line side can be two in total, one in the selected block and one in the adjacent selected block. In the NAND cell type EEPROM, the source line side select transistor is decoded as a source line side select transistor decoding method by setting a selected block and a source line side adjacent block of the selected block as a set. The number of gate lines can be two in total, one in the selected block and one in the block adjacent to the source line of the selected block.

As described above, according to the present invention, the gate charging / discharging time of the select transistor during the read operation can be shortened and the read operation can be speeded up without increasing the chip area.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a NAN according to an embodiment of the present invention.
It is a block diagram showing a D-cell type EEPROM system configuration. A bit line control circuit 2 is provided for performing data write, read, rewrite, write verify read, and erase verify read on the memory cell array 1. The bit line control circuit 2 is connected to the data input / output buffer 6 and receives as an input the output of the column decoder 3 which receives the address signal from the address buffer 4. Further, a row decoder 5 is provided for controlling the control gate and the select gate for the memory cell array 1, and the p substrate (or p substrate) on which the memory cell array 1 is formed.
Substrate potential control circuit 7 for controlling the potential of the mold well)
Is provided.

2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array,
3A and 3B are cross-sectional views taken along the lines AA 'and BB' of FIG. 2A, respectively. A plurality of N's are formed on the p-type silicon substrate (or p-type well) 11 surrounded by the element isolation oxide film 12.
A memory cell array composed of AND cells is formed. Explaining one NAND cell, in this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell.

Each of the memory cells has a floating gate 14 (14 ₁ , 14 ₂ ,
, 14 ₈ ), and control gates 16 (16 ₁ , 16 ₂ , ..., 16 ₈ ) are formed on the interlayer insulating film 15 to form a structure. The n-type diffusion layers 19 serving as the source / drain of these memory cells are connected in a form of being adjacent to each other, whereby the memory cells are connected in series.

Select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are formed on the drain side and the source side of the NAND cell at the same time as the floating gate and the control gate of the memory cell. CV on the substrate on which elements are formed
The D oxide film 17 covers the bit line 18, and the bit line 18 is provided thereon. The bit line 18 is in contact with the drain side diffusion layer 19 at one end of the NAND cell. The control gates 16 of the NAND cells arranged in the row direction are commonly arranged as control gate lines CG (1), CG (2), ..., CG (8). These control gate lines become word lines.
The select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also continuously arranged in the row direction as select gate lines SG ₁ , SG ₂ .

The selection gates 14 ₉ and 14 ₁₀ and the substrate 1
The gate insulating film 13 between the gate insulating layer 1 and the gate insulating layer 1 may be formed thicker than the gate insulating film in the memory cell portion so as to increase the reliability thereof.

FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix.

FIG. 5 shows a plurality of NAs in the memory cell array.
6A and 6B are plan views of the ND cell array, FIG. 6A and FIG. 6B are plan views of portions (I) and (II) in FIG. 5, and FIG. 6C is a plan view of FIG. It is CC 'sectional drawing. In addition, FIG.
The reference numerals indicating the respective nodes are the same as those in FIG.

In the NAND cell type EEPROM, as shown in FIG.
As can be seen from FIG. 3, the node 14 wiring is used as the gate electrode of the select gate transistor, and the interlayer insulating film 1
The node 16 wiring is formed in parallel with the node 14 wiring with the node 5 interposed therebetween. Since the node 14 wiring normally has a high resistance, when only the node 14 wiring is used as the selection gate line, the charging / discharging time of the selection gate line becomes long, and in this case, the operation time of each chip is long. Invites time.

In order to shorten the charging / discharging time of the select gate line, the node 16 wiring and the node 14 wiring whose resistance is set several times lower than that of the normal node 14 wiring are provided at several places (or dozens of places) in the memory cell array. The method of connecting with is used. In this case, a region for connecting the node 16 wiring and the node 14 wiring is provided in the memory cell array, and a region of width L3 (hereinafter referred to as select gate) provided between the NAND cell arrays in FIG. Called the connection area)
Is that. In this selection gate connection region, as shown in FIG.
As in (a) and (b), the node 16 wiring and the node 14 wiring are connected in both the bit line contact side selection gate SG1 and the source line side selection gate SG2.

In the bit line contact side select gate SG1, since the SG1 inter-wiring distance L1 sandwiching the bit line contact is long, SG1 sandwiching the bit line contact is formed.
In the above, the connection between the node 16 and the node 14 can be made separately. However, the source line side select gate SG
2, the SG2 inter-wiring distance L2 across the source line
Since it is short, it is not possible to separately connect the node 16 and the node 14 in SG2 with the source line sandwiched between them. Therefore, as shown in FIG. The SG2 node of is connected between the node 16 and the node 14 in a connected state.

The source line side selection gate SG2 is at the same potential between adjacent blocks sandwiching the source line. Also,
In this selection gate connection area, the nodes 16 and 14 are connected.
Are connected by low resistance wiring material. FIG. 6C shows the case where the node 16 and the node 14 are connected using the same wiring material as the bit line. In addition, the wiring material different from that of the bit line, the node 16 and the node 14 is used to make the node 1
It is also possible to connect between 6 and node 14. It is also possible to form a wiring material different from the node 16 in parallel with the node 14 and connect the wiring material different from the node 16 to the node 14 in the selection gate connection region.

FIG. 7 shows an array of NAND cell blocks and an array of selection / control gates. Each NAND cell block is composed of a plurality of NAND cells sharing a source line. A plurality of NAND cell blocks are arranged so that one end shares the bit line and the other end shares the source line. As described in the description of FIG. 6, it can be seen that SG2 has the same potential between the blocks sandwiching the source line side. Therefore, one NAND
When a cell block is selected, the SG2 potential of the block adjacent to the source line side of the selected block (hereinafter, simply referred to as an adjacent block) is SG2 in the selected block.
It becomes the same potential as the 2 potential.

FIG. 8 shows a timing chart of the read operation of the NAND cell type EEPROM in which the SG2 node is wired as shown in FIGS. However, SG2 in the source line side adjacent block in FIG. 8 indicates SG2 in the source line side adjacent block of the selected block.

In the operation shown in FIG. 8, it is said that the threshold voltage of the memory cell of "1" data is higher than the allowable range (higher than 0 V and lower than the voltage applied to the non-selected control gate in the selected block during the read operation). The current flowing through the NAND cell (NAND cell including the selected memory cell in the “0” data) that causes a current to flow during the read operation is increased (the voltage applied to the non-selected control gate in the selected block). Is higher, the current flowing through the NAND cell is larger)
The read operation is performed when the non-selection control gate potential in the selected block is set to a voltage higher than the power supply voltage Vcc during the read operation for the purpose of shortening the read required time. However, it is assumed that a voltage higher than Vcc is generated by the read high voltage generating circuit in the chip. The operation timing of FIG. 8 will be briefly described below.

Before the read operation is started, the bit line is at a potential of 0V or more and Vcc or less. At the start of the read operation, one of the eight control gates in the selected block is selected by the row address. When the read operation is started, first, all bit lines are charged to Vcc. Subsequently, the non-selection control gates (7) in the selected block, SG in the selected block
1, SG2 in the selected block and SG2 in the adjacent block (on the source line side of the selected block) are charged from 0V to Vcc. In this case, the time required to charge to the Vcc potential is the time determined by the resistance and capacitance of each control gate / select gate wiring in the memory cell.

The non-selection control gate in the selected block, SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) are all wiring materials of the node 16 in FIG. The same material is used (however, SG1 and SG2 have the same wiring material as the node 16 with the lower resistance of the wiring), and since the wiring capacity is also about the same, the non-selection control gate in the selected block, the selected block SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block)
Then, the charging time is about the same (corresponding to (A) in FIG. 8).

Next, the non-selection control gate in the selected block,
Each node of SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) is an output node VC of the read high voltage generation circuit.
Connected to GH. Then, the read high voltage generation circuit starts to generate a voltage higher than Vcc, and a voltage higher than Vcc is supplied to the output node VCGH of the read high voltage generation circuit. Each node of SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) is also charged to a voltage higher than Vcc.

At this time, the portion which becomes the load capacitance of the high voltage for reading is the control gate 7 lines, the selection gate 3 and the high voltage node in the row decoder (VPPRW node in FIG. 9 (p channel in HV broken line). (Including the n-well capacitance in which the transistor is formed) and one of the nodes N1 and N2). When the read high voltage reaches the desired potential level VH, the VCGH node and the node connected to the VCGH node are kept at the VH potential for a while, and data is read from the selected memory cell to the bit line.

Subsequently, the non-selection control gate in the selected block, SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block).
Each node is discharged from VH to 0V. In this case, the time required for discharging to 0V potential is the time determined by the resistance and capacitance of each control gate and select gate wiring in the memory cell. The non-selection control gate in the selected block, the SG1 in the selected block, the SG2 in the selected block, and the SG2 in the adjacent block (on the source line side of the selected block) are the same as the wiring materials of the node 16 in FIG. (However, SG1 and SG2 have the same wiring material as that of the node 16 which has the lower resistance among the wirings) and the wiring capacitance is also the same, so that the non-selection control gate in the selected block and SG1 in the selected block are The SG2 in the selected block and the SG2 in the adjacent block (on the source line side of the selected block) have the same required charging time (corresponding to (C) in FIG. 8).

Then, the read high voltage generating circuit ends the generation of the voltage higher than Vcc, and the VCGH node is set to the Vcc potential. Further, the voltage of the bit line is read by the sense amplifier and output to the outside of the chip, and then the read operation is completed.

As is clear from the operation timing of FIG. 8, the SG in the selected block among SG2 in all the blocks
2 and S in the adjacent block (on the source line side of the selected block)
Only the two SG2s of G2 are at the VH potential from Vcc during the read operation, and all the SG2s other than the two are kept at 0V.

Thus, when a block is selected,
SG2 in the adjacent block is also selected together with SG2 in the selected block (source line side of the selected block),
SG2 in the adjacent block is set to the same potential as SG2 in the selected block (on the source line side of the selected block) (for example, 0V → Vcc → VH → 0V is set during the read operation) and in other blocks. SG2 is a set voltage in the non-selected block (for example, 0V during the read operation).
It is a feature of the present invention to set to.

However, the present invention is not limited to the read operation, and when the present invention is used, the SG2 potential in the selected block and the SG2 in the non-selected block (excluding the adjacent block on the source line side of the selected block). When the potentials are set to different potentials, SG2 in the adjacent block (on the source line side of the selected block) is kept at the same potential as the SG2 potential in the selected block even during the read operation.

FIG. 9 shows a configuration example of the row decoder 5 for realizing the above-described present invention. The n-well potential where the p-channel transistor is formed within the HV broken line in FIG. 9 is VPPR.
It is set to the W node potential. Signal RDENB is NAND
Signal RD that is a signal for activating the cell block selection operation
While ENB is at "H", the block corresponding to the row address is in the selected state. The block decode signal is a signal in which the type of input signal is different in each block, and in the block corresponding to the row address, all the block decode signals are "H" and the signal RDENB is in the "H" selected state. Becomes

The signals ERASE and ERASEB are "H" and "L" during the erase operation, and "L" and "H" except during the erase operation. Also, the signals SGD, CG1 to
8, SGS, and Vuss are signals that have the same operation timing in any block regardless of selected / adjacent / non-selected blocks. The VPPRW node is connected to VC during the read operation.
It is at the same potential as the GH node and is charged to the high voltage for programming / erasing during programming / erasing operations.

When this row decoder is used, U
When one of the P and DOWN blocks is selected, the other is the adjacent block on the source line side of the selected block. If neither the UP block nor the DOWN block is selected, both the blocks become just non-selected blocks, and the UP block and the DO block are not selected.
Neither WN is a block adjacent to the selected block on the source line side.

In addition, except during the erase operation, the node N1,
N2 has the same potential as VPPRW and 0V in the selected block, and 0V and V in the adjacent block on the source line side of the selected block and other non-selected blocks, respectively.
It has the same potential as PPRW. Therefore, in this row decoder, the SG in the selected block is operated during operations other than the erase operation.
1, CG (1) to CG (8) are SGD and CG, respectively.
The potentials of 1 to CG8 are sent.

In the block adjacent to the source line side of the selected block and in other non-selected blocks, CG1 to CG
8 is 0V, SG1 is Vuss (or (Vuss-V
thn) potential; provided that Vthn is an E type, threshold voltage of n-channel MOS transistors Qn2 to Qn15) potential.

Further, except during the erase operation, in the selected block and in the block adjacent to the source line side of the selected block, both the transistors Qn7 and Qp4 or the transistor Qn7.
Since both the transistors n10 and Qp5 are turned on and one of the transistors Qn8 and Qn9 is turned off, SG2 is set to the SGS potential. In the other blocks, four transistors Qn7, Qp4, Qn10, and Qp5 are off, both Qn8 and Qn9 are on, and SG2 is Vuss (or (Vuss
-Vthn)) potential.

During the erase operation, the nodes N1 and N2 are
Are the same potential as 0V and VPPRW in the selected block, respectively, and the same potential as VPPRW in the source line side adjacent block of the selected block and other non-selected blocks, respectively.
It becomes 0V. Therefore, during the erase operation, CG1 to CG8 are at 0 V and SG1 is at Vuss (or (Vuss-Vthn) potential) potential in the selected block. In the adjacent block on the source line side of the selected block and in other non-selected blocks, the potentials of SGD and CG1 to CG8 are sent to SG1, CG (1) to CG (8), respectively.

In the erase operation, when only one of the blocks sandwiching the source line is selected, both the transistors Qn7 and Qp4 or the transistor Qn10 are selected in the selected block and in the adjacent block on the source line side of the selected block. , Qp5 are both on, and one of the transistors Qn8, Qn9 is off, so SG2 is set to the SGS potential. In other non-selected blocks, the transistors Qn8, Qp4, Q
Since all four transistors of n10 and Qp5 are in the on state and both of the transistors Qn8 and Qn9 are in the off state, SG2 is set to the SGS potential.

Even during the erase operation, even when a plurality of blocks such as chip erase are selected at the same time, and when both blocks sandwiching the source line are selected, the row decoders corresponding to the both selected blocks are selected. As long as all the transistors Qn7, Qp4, Qn10 and Qp5 are turned off and both the transistors Qn8 and Qn9 are turned on, SG2 in both the selected blocks becomes the Vuss (or (Vuss-Vthn)) potential. The row decoder of FIG. 9, which is an example of the configuration of the present invention, is characterized by the configuration of the (*) part as compared with the conventional configuration of the row decoder, and this configuration realizes the operation timing of FIG.

Further, FIG. 10 shows the operation timing at the time of the read operation of the row decoder related signals for realizing the read operation shown in FIG. However, the adjacent block in FIG. 10 indicates a source line side adjacent block of the selected block, and the non-selected block in FIG. 10 refers to the selected block and the source line side adjacent block of all the selected blocks. It indicates the removed blocks.

FIG. 11 shows the operation timing of the nodes in the memory cell array and the row decoder in the data erase operation. However, the adjacent block in FIG. 11 indicates a source line side adjacent block of the selected block, and the non-selected block in FIG. 11 is the selected block and the source line side adjacent block of all the blocks. It indicates the removed blocks. The operation timing of the SG2 node in FIG. 11 is when only one of the blocks sandwiching the source line is selected in the erase operation.

When a plurality of blocks such as chip erase are simultaneously selected during the erase operation, and both blocks sandwiching the source line are selected, the operation timing of the SG2 node in both selected blocks is selected. Figure 1
It is shown in FIG.

Next, the effect of the present invention will be described.

FIG. 15 shows an arrangement of conventional NAND cell blocks and an arrangement of selection / control gates. As can be seen from FIG. 15, conventionally, all SG2 nodes in all blocks are connected and set to the same potential. FIG. 16 shows the circuit configuration of the row decoder 5 in the conventional system. FIG.
Then, the SGS voltage externally input to the row decoder is directly input to the SG2 node without being decoded,
Since the SGS voltage is the same potential in all blocks, the SG2 node has the same potential in all blocks. The reason why the SG2 node potential is conventionally set in this way will be described below.

As shown in FIG. 6, since the distance between the select gates on the source line side is short in the connection region between the node 16 and the node 14 with the source line sandwiched between them, the source gate is not connected to the source gate in the connection region. The node 16 and the node 14 in both blocks sandwiching the line are connected to connect the node 16 and the node 14, and the SG2 node potential becomes the same potential in both blocks sandwiching the source line.

In the row decoder shown in FIG. 16, since only decode signals in block units exist as decode signals, SG signals to be decoded in block units are used.
1, the same circuit as CG (1) to CG (8) cannot be used to decode the SG2 node to be decoded by setting the selected block and the adjacent block on the source line side of the selected block, and therefore the selected block and the selected block. The method of decoding by setting adjacent blocks on the source line side has not been used.

During the write / read operation, the bit line contact side select gate SG1 is in the "L" state in the non-selected block, and the bit line and the memory cell are not in the non-selected block by the bit line contact side select gate. Since it is in the conductive state, no malfunction occurs in the non-selected block regardless of the voltage of the source-side selection gate SG2. That is, since a highly reliable write / read operation can be realized, there is no problem in terms of operation reliability even if all the source side select gate SG2 potentials in the non-selected block are the same as the SG2 potential in the selected block. It was Further, during the erase operation, SG2 nodes in all blocks are all charged to the high voltage for erasing, so that it is not necessary to decode SG2 nodes. Therefore, a method has been used in which all SG2 nodes in all blocks are connected to have the same potential.

However, in the conventional method in which all SG2 nodes in all blocks are connected, the capacity of the SG2 node becomes enormous, so that the charging / discharging time of the SG2 node becomes long and the SG2 node is charged. There is a problem that the time required for operations including the discharge operation becomes long. FIG.
FIG. 7 shows the operation timing at the read operation when the conventional method is used.

The operation timing differs from that shown in FIG. 8 in that the time required to charge the SG2 node from 0 V to Vcc in FIG. 17 (corresponding to (ki) in FIG. 17) and the time required to discharge VH potential to 0 V ( 17 is longer than the charging / discharging required time of FIG. 8 (corresponding to (A) and (C) of FIG. 8, respectively), and Vcc of each node by the read high voltage generating circuit. To VH potential charging time (Fig. 1
7 and 8 correspond to (K) and (B), respectively, and are shown in FIG.
7 is longer than that in FIG. This is because the SG2 node capacity is much larger in the conventional method than in the method of the present invention. The details will be described below.

First, the difference between the time required to charge the SG2 node from 0V to Vcc and the time required to discharge the VH potential to 0V will be described. As described above, in FIG. 8, non-selection control gates in the selected block, SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block) are charged from 0V to Vcc. The required time and the time required to discharge the VH potential to 0V are both determined by the resistance and capacitance of each wiring in the memory cell.

The non-selection control gate in the selected block, the SG1 in the selected block, the SG2 in the selected block, and the SG2 in the adjacent block (on the source line side of the selected block) are the wiring materials of the node 16 in FIG. The same material is used (however, SG1 and SG2 have the same wiring material as the node 16 with the lower resistance of the wiring), and since the wiring capacity is also about the same, the non-selection control gate in the selected block, the selected block SG1 in the selected block, SG2 in the selected block, and SG2 in the adjacent block (on the source line side of the selected block)
Then, the charging time is about the same (corresponding to (A) in FIG. 8).

In this case, the SG2 signal → transistor Qn7, Qp4, Qn10 in the row decoder is used to charge the SG2 from 0V to Vcc and discharge it from the VH potential to 0V.
Qp5 → SGS node → SGS potential control circuit. Further, since the SGS potential control circuit for executing the charging / discharging is located away from the row decoder, there is a wiring resistance between the SGS node and the SGS potential control circuit in the row decoder, and the SGS potential control circuit. There is a resistance also in the transistor for executing the charge / discharge operation.

In the operation shown in FIG. 8, since the capacity of the memory cell of the SG2 node is as small as about two SG2,
Charge operation from 0V to Vcc of SG2 and 0V from VH potential
Since the wiring resistance and the transistor resistance did not pose a problem in the discharge operation to the, the time required for the charge / discharge operation of the SG2 node was about the same as that of the non-selection control gate in the selected block and SG1 in the selected block.

However, in the method of connecting all SG2 nodes in all blocks as in the operation of FIG.
G2 node capacity = (one SG2 capacity) × (SG2
, The total number of blocks), and the total number of blocks is usually several hundreds to several thousands, so the capacity of the SG2 node becomes a huge value.

In this case, during the charging / discharging operation of the SG2 node, the wiring resistance of the SGS node or the resistance of the transistor in the SGS potential control circuit becomes a problem, and the SG
The charging / discharging time required for two nodes is SG in the memory cell.
2 is much longer than the time determined by the resistance and capacitance of the wiring, is much longer than the non-selection control gate in the selected block and SG1 in the selected block, and is longer than the charging / discharging time of SG2 when the present invention is used. Will also be much longer.

Also in FIG. 17, (K) and (K) are significantly longer than (K) and (K), and FIG.
(Ki) and (ko) in 7 are much longer than (a) and (u) in FIG. Thus, in the conventional method,
There has been a problem that the time required for charging and discharging the SG2 becomes long, and as a result, the operation speed decreases. In the conventional method, in order to shorten the charging / discharging time of the SG2 node, the width of the wiring of the SGS node is increased and the size of the transistor in the SGS potential control circuit is increased to reduce the wiring / transistor resistance. There is a method, but S
In order to shorten the GS charging / discharging required time to the level of the case where this method is used, it is necessary to increase the SGS wiring width and the transistor size by several tens of times or more, which significantly increases the chip size.

Next, a comparison between the conventional method and the present invention in the time required for charging the Vcc to VH potential of each node by the read high voltage generating circuit will be described. The VH potential is a potential generated and supplied by the read high voltage generating circuit in the chip,
The current supply capability of this generating circuit is much lower than the current supply capability of the power supply voltage or the ground voltage. Therefore, VC of each node
The time required to charge the potential from C to VH is governed by the current supply capability of the generation circuit and the load capacitance of the high voltage for reading, rather than the wiring resistance of each node and the resistance of the transistor.

When the current supply capacities of the generation circuits are the same, the present invention and the conventional system will be compared. In the present invention, the read high voltage load capacitance has seven control gates, three select gates, and a high voltage node in the row decoder (VPPRW node in FIG. 9 (p-channel transistor in HV broken line). n well capacitance) and one of the nodes N1 and N2), and the load capacitance of the read high voltage in the conventional method is 7 control gates, several hundred to several thousand select gates, and the high voltage in the row decoder. A node (a VPPRW node in FIG. 9 (including the N-well capacitance in which the p-channel transistor is formed within the HV broken line) and one of the nodes N1 and N2).

The load capacitance is different in the number of select gates, and the conventional system has a larger capacity for hundreds to thousands of select gates. Since the capacity of several hundreds to several thousands of selection gates is larger than [capacity of 7 control gates + capacity of high voltage node in row decoder], the conventional method is more suitable as the load capacity of the high voltage for reading. Several times larger than. Therefore, the time required to charge the VH potential from Vcc of each node by the read high voltage generation circuit is several times longer in the conventional method than in the present invention (in FIG. 17 (K) than in FIG. 8 (A)). Equivalent to long).

On the other hand, when the conventional method is used, in order to shorten the time required to charge the Vcc to VH potential, the current supply capacity of the read high voltage generating circuit is increased several times or more in order to use the present invention. . That is, it is necessary to make the pattern area of the read high voltage generating circuit several times or more, which causes a large increase in the chip area. On the other hand, according to the present invention, the time required to charge the VH potential from Vcc can be shortened and the read operation can be speeded up.

The present invention has been described mainly with reference to the read operation when the non-selection control gate potential in the selected block is set to a voltage higher than the power supply voltage Vcc during the read operation. The invention is not limited to the embodiment described above. For example, the present invention is also effective in the read operation when the non-selection control gate potential in the selected block or the like is charged only to the power supply voltage Vcc during the read operation. 14 and 18 show the read operation timings when the present invention and the conventional method are used when the high voltage for reading is not used during such a read operation. When the present invention is used, the time required to charge the SG2 to Vcc potential and the time required to discharge to 0V can be shortened as compared with the conventional method ((d) and (e) in FIG. 14). (Corresponding to shorter than (c) and (c) in FIG. 17), it can be seen that the read operation can be speeded up.

Further, the circuit configuration of the row decoder 5 shown in FIG. 9 can be variously modified without departing from the gist of the present invention. For example, instead of the part of (*) in FIG. The present invention is effective when a) to (e) are used.
Instead of the (*) part in FIG. 9, (a) in FIG.
When (c) and (d) are used, the SG2 potential in the non-selected block (excluding the block adjacent to the source line side of the selected block) cannot be set to 0V during the read / write operation, resulting in Vt.
SG2 potential can be lowered only up to hp (however, V2
thp is a transistor Qp17, Qp18, Qp19, Qp20
The threshold voltage of the bit line contact side select gate SG1 is in the “L” state in the non-selected block during the write / read operation, and the bit line and the memory cell are selected in the non-selected block. Since it is turned off by the gate, malfunction does not occur regardless of the voltage of the source-side selection gate SG2 in the non-selected block, that is, there is no problem in reliability.

When (e) in FIG. 13 is used in place of the (*) part in FIG. 9, it is in the non-selected block during the write / read operation (the block adjacent to the source line of the selected block). SG2 node of (excluding) is in a floating state, but there is no problem in reliability for the same reason as in the case of using (a) (c) (d) in FIG.

When (e) in FIG. 13 is used instead of the (*) part in FIG. 9, only when both blocks sandwiching the source line are selected during the erase operation. SG2s in both selected blocks become floating. In this case, however, all nodes in the memory cell array other than the control gates are charged to the high voltage for erasing, so the SG2 node in the floating state is It is considered that there will be no problem in terms of reliability due to charging to a high voltage for erasing due to capacitive coupling with surrounding nodes. Nevertheless, when (e) in FIG. A detailed study of the potential increase due to the ring is required.

Further, in the case of using (e) in FIG. 13, a leak current that is not a problem except in the floating state, that is, when electric charge is supplied through the transistor (see FIGS. 9 and 13 ( In the cases (a) to (d) are used, even if a negligible leak current exists in the SG2 node, if the SG2 node is floating, the SG2 node (node 14 in FIG. 3) is caused by the leak current. ₁₀ and 16 ₁₀ ) decrease and the p-type well (or p-type substrate) forming the memory cell array (corresponding to node 11 in FIG. 3) is at the high voltage for erasing.
There is a risk that the potential difference between the SG2 node and the p-type well (or p-type substrate) becomes large, leading to destruction or failure.

However, the case of using (e) in FIG. 13 is the case where the number of elements in the part of (☆) is the minimum,
Since the pattern area of the row decoder is slightly smaller than that of the other cases, the row decoders shown in FIGS.
As for which of (a) to (e) is used, which is the best cannot be said in any way.

As an example of the configuration of the row decoder 5, the SG2 nodes in both blocks sandwiching the source line are connected in the row decoder so far as shown in FIG.
The present invention is not limited to the above embodiment. For example, like the row decoder shown in FIG. 19, the SG2 nodes in both blocks sandwiching the source line are not connected in the row decoder, and the circuit in the part of (*) in FIG. 9 is also in the row decoder. Then SG2 in both blocks that sandwich the source line
The present invention is effective even when connecting to any of the nodes.

In the row decoder used in the present invention,
Compared to the conventional row decoder, the number of transistors is increased by 3 to 4 per block, but the row decoder includes about 50 transistors per block. Therefore, the circuit of the row decoder to be used. When the configuration is changed from the conventional one to that of the present invention, the pattern area increase amount of the row decoder is about 10% at maximum. However, as for the effect on the entire chip area, the amount of increase in the chip area when the read operation speed is increased by using the conventional method to the same extent as the read operation speed when the present invention is used depends on the change of the row decoder. It is much larger than the increase in chip area. Therefore, it is much more effective to use the present invention in order to speed up the read operation.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. In the above embodiment, when adjacent source line side select gates are connected and set to the same potential, the adjacent source line side select gates are set and decoded, and the bit line contact side select gates are decoded block by block. However, instead of the source line side select gates, the adjacent bit line contact side select gates are connected and set to the same potential, and the adjacent bit line contact side select gates are set and decoded. The present invention is also effective when the line-side selection gate is decoded for each block.

FIG. 20 shows a NAND cell block array diagram in such an embodiment, and FIG. 21 shows a configuration example of a row decoder. The embodiment shown in FIGS. 20 and 21 is particularly effective when the distance between the select gates on the bit line contact side is shortened and it becomes difficult to separate the adjacent select gates on the bit line contact side. Similar to the embodiment described above, a high speed operation can be realized even if two adjacent select gates on the bit line contact side are set to the same potential.

FIG. 22 shows a NAND cell block array diagram in another embodiment. The features of the embodiment shown in FIG. 22 will be described below. As the design rule becomes smaller, the distance between the select gates on the bit line contact side and the distance between the select gates on the source line side are both reduced. It becomes difficult for both sides. When the embodiment shown in FIG. 22 is used, the adjacent select gates are at the same potential on both the bit line contact side and the source line side, so that there is no need to separate the select gate lines, which facilitates processing. High-speed operation can be realized.

The embodiment of FIG. 22 is, for example, a circuit portion for setting the source line side select gate potential of FIG. 9 (Qn7, Qn in FIG. 9).
n8, Qn9, Qn10, Qp4, Qp5) and the circuit part for setting the select gate potential on the bit line contact side in FIG. 21 (Qn1, Qn2, Qn15, Qn16, Qp1, Qp8 part in FIG. 21) are combined. Can be realized easily. Further, in the NAND cell type, when either the bit line contact side select gate or the source line side select gate is not present, the present invention is also effective when the present invention is applied to the remaining select gates.

Up to now, the NAND cell type EEPROM has been used.
In the above description, the case where the number of the bit line contact side selection gates and the number of the source line side selection gates in the single NAND cell are both one is described as an example, but the present invention is not limited to these examples. . For example, it is also effective when the number of one or both of the bit line contact side selection gate and the source line side selection gate in the single NAND cell is two or more. 23 to 30 show an embodiment in which there are a plurality of bit line contact side select gates and a plurality of source line side select gates.

23 and 24 show an embodiment in which only the select gate (one per block) adjacent to the source line is set to the same potential, and FIGS. 25 and 26 show the source between adjacent blocks sandwiching the source line. This is an example in which all the k line-side selection gates have the same potential. Also, FIG.
7, FIG. 28, FIG. 29 and FIG. 30 are respectively FIG. 23 and FIG.
4, FIG. 25 and FIG. 26 are embodiments in which the selection gate to which the present invention is applied is changed from the source line side to the bit line contact side. However, FIG. 24, FIG. 26, and FIG.
8 and 30, the row decoder circuit shown in FIG. 9 and the like is partially omitted, but the block selection signals have the same meaning.

So far, the present invention has been applied to the NAND cell type EE.
Although the embodiment in the case of being applied to the PROM has been shown, the present invention is also effective in other memory cell units. For example, DINOR cell type EEPROM and AND cell type EEP
The present invention can be applied to a ROM.

FIG. 31 shows an equivalent circuit diagram of the memory cell array in the DINOR cell type EEPROM. DINO
For details of the R cell type EEPROM, see "H. Onoda et a
l..IEDM Tech. Digest, 1992, pp.599-602 ". Also, Fig. 32 shows an equivalent circuit diagram of a memory cell array in an AND cell type EEPROM. AND cell type EEPR
For details of OM, see “H.Kume et al., IEDM Tech.
Degest, 1992, pp.991-993 ”.

The present invention is also based on the DINOR cell type EEPR.
An example of the case applied to the OM is shown in FIGS. 33 and 34. However, DSL1 (UP), DSL2 (UP),
DSL1 (DOWN) and DSL2 (DOWN) are block selection signals, and N1 (UP) and N2 (U in FIG. 9 are used.
P), N1 (DOWN) and N2 (DOWN).

Further, the present invention is an AND cell type EEPROM.
35, 36, 37, and 38 when applied to FIG.
Shown in However, the signal ASL1 (U
P), ASL2 (UP), ASL1 (DOWN), AS
L2 (DOWN) is a block selection signal, and the signals N1 (UP), N2 (UP), N1 (DOWN),
It is a signal corresponding to N2 (DOWN).

In the above embodiments, an example in which the number of memory cells between the bit line and the source line is plural has been shown, but the present invention is not limited to the above embodiments. For example, it is also effective when the number of memory cells between the bit line and the source line is one as shown in FIGS.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified without departing from the scope of the invention.

[0097]

As described above, according to the present invention, as the decoding method of the selection transistor, the method of decoding by selecting the selected block and the adjacent block on the source line side or the bit line contact side of the selected block as a set is used. , The total number of gate lines of the selection transistors on the source line side or the bit line side, which is charged / discharged during the read operation, is 1 in the selected block and 1 in the adjacent selected block.
It can be a book. For example, in the case of the NAND cell type, by decoding the two source line side select gates adjacent to the source line as a set, the time required for charging / discharging the voltage to the source line side select gate can be shortened. Therefore, it is possible to realize an EEPROM having a faster read operation than the conventional one, without increasing the chip size.

[Brief description of drawings]

FIG. 1 is a NAND cell type EE according to an embodiment of the present invention.
FIG. 3 is a block diagram showing the system configuration of a PROM.

FIG. 2 is a plan view and an equivalent circuit diagram of one NAND cell portion of the memory cell array.

3 is a sectional view taken along line AA ′ and BB ′ of FIG.

FIG. 4 is an equivalent circuit diagram of a memory cell array in which NAND cells are arranged in a matrix.

FIG. 5 is a plan view of a plurality of NAND cell arrays in a memory cell array.

6A and 6B are a plan view and a cross-sectional view of a select gate in a memory cell array.

FIG. 7 is a diagram showing an arrangement of NAND cell blocks and an arrangement of selection / control gates.

FIG. 8 is a timing chart of a read operation of a NAND cell type EEPROM.

FIG. 9 is a circuit configuration diagram of a row decoder according to an embodiment of the present invention.

10 is an operation timing chart at the time of a read operation of signals related to the row decoder of FIG.

FIG. 11 is an operation timing chart of nodes in a memory cell array and a row decoder in a data erase operation.

FIG. 12 is an operation timing chart of the SG2 node in both selection blocks when the amount block sandwiching the source line is selected during the erase operation.

FIG. 13 is a view showing a modified example of the part of the (*) part in FIG.

FIG. 14 is a data read operation timing chart according to another embodiment of the present invention.

FIG. 15 is a diagram showing an arrangement of NAND cell blocks and an arrangement of selection / control gates in a conventional method.

FIG. 16 is a circuit configuration diagram of a row decoder in a conventional system.

FIG. 17 is an operation timing chart at the time of read operation when the conventional method is used.

FIG. 18 is a timing chart of a data read operation according to another conventional example.

19 is a diagram showing a modification of the circuit configuration of the row decoder shown in FIG.

FIG. 20 is a NAND circuit according to still another embodiment of the present invention.
FIG. 3 is a diagram showing an arrangement of cell blocks and an arrangement of selection / control gates.

FIG. 21 is a circuit configuration diagram of a row decoder according to still another embodiment of the present invention.

FIG. 22 is a NAND according to still another embodiment of the present invention.
FIG. 3 is a diagram showing an arrangement of cell blocks and an arrangement of selection / control gates.

FIG. 23 is a diagram showing a NAND cell block array in the case where only the select gate (one per block) adjacent to the source line has the same potential.

FIG. 24 is a diagram showing a row decoder configuration in the case where only the select gates (one per block) adjacent to the source lines have the same potential.

FIG. 25 is a NAN in the case where corresponding blocks have the same potential between adjacent blocks that sandwich all k source line side selection gates;
The figure which shows a D cell block arrangement | sequence.

FIG. 26 is a diagram showing a row decoder configuration in a case where adjacent blocks sandwiching all k source line side selection gates have the same potential in corresponding blocks.

FIG. 27 shows N in the case where the selection gate to which the present invention is applied is changed from the source line side to the bit line contact side.
The figure which shows an AND cell block arrangement | sequence.

FIG. 28 is a diagram showing a row decoder configuration when the selection gate to which the present invention is applied is changed from the source line side to the bit line contact side.

FIG. 29 shows N in the case where the selection gate to which the present invention is applied is changed from the source line side to the bit line contact side.
The figure which shows an AND cell block arrangement | sequence.

FIG. 30 is a diagram showing a row decoder configuration when the selection gate to which the present invention is applied is changed from the source line side to the bit line contact side.

FIG. 31 is an equivalent circuit diagram of a memory cell array in a DINOR cell type EEPROM.

FIG. 32 is an equivalent circuit diagram of a memory cell array in an AND cell type EEPROM.

FIG. 33 is a diagram showing a block arrangement when the present invention is applied to a DINOR cell type EEPROM.

FIG. 34 is a diagram showing a row decoder configuration in FIG. 33.

FIG. 35 is a diagram showing a block arrangement when the present invention is applied to an AND cell type EEPROM.

FIG. 36 is a diagram showing a row decoder configuration in FIG. 35.

FIG. 37 is a diagram showing a block arrangement when the present invention is applied to an AND cell type EEPROM.

38 is a diagram showing a row decoder configuration in FIG. 37. FIG.

FIG. 39 is an equivalent circuit diagram of a memory cell array in a parallel connection type EEPROM.

FIG. 40 is an equivalent circuit diagram of a memory cell array in another parallel-connected EEPROM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Bit line control circuit 3 ... Column decoder 4 ... Address buffer 5 ... Row decoder 6 ... Data input / output buffer 7 ... Substrate potential control circuit 11 ... P-type silicon substrate 12 ... Element isolation oxide film 14 ... Floating gate (Charge storage layer) 16 ... Control gate 17 ... Interlayer insulating film 18 ... Bit line 19 ... N-type diffusion layer SG ... Select gate line CG ... Control gate line

Claims (4)

[Claims] 1. A block in which one or more nonvolatile memory cells are connected between a bit line and a source line, and a select transistor is arranged between the memory cell and at least one of the bit line and the source line. A memory cell array configured by arranging a plurality of the blocks so that one end side shares a bit line and the other end side shares a source line; and a column decoder that selects a bit line of the memory cell array, A non-volatile semiconductor memory device comprising: a row decoder for selecting a word line of the memory cell and a gate line of the selection transistor, wherein the row decoder includes source line side selection transistors adjacent to each other between the blocks. Non-volatile semiconductor memory characterized in that at least one of the gate lines and the gate lines of the bit line side selection transistors are selected as one set. apparatus. 2. A memory cell in which a plurality of non-volatile memory cells are connected, one end side is connected directly or via a selection transistor to a bit line, and the other end side is connected directly or via a selection transistor to a source line. A unit is formed, and a plurality of the memory cell units are arranged so as to share a source line to form a block, and a plurality of the blocks share a bit line on one end side and a source line on the other end side. A nonvolatile memory including a memory cell array arranged so as to be shared, a column decoder for selecting a bit line of the memory cell array, and a row decoder for selecting a word line of the memory cell and a gate line of the selection transistor. A semiconductor memory device, wherein the row decoder selects each gate line and bit line side of the source line side selection transistor adjacent between the blocks. A non-volatile semiconductor memory device, characterized in that at least one of the gate lines of select transistors is selected as a set. 3. A plurality of non-volatile memory cells connected in series,
One end side is connected to a bit line through a selection transistor and the other end side is connected to a source line through a selection transistor to form a memory cell unit, and a plurality of the memory cell units share a source line. A memory cell array in which a plurality of blocks are arranged such that one end shares a bit line and the other end shares a source line; and a bit line of the memory cell array. A non-volatile semiconductor memory device comprising: a column decoder for selecting a memory cell; and a row decoder for selecting a word line of the memory cell and a gate line of the select transistor. The gate lines of the transistors are commonly connected and connected to the wiring driven by the row decoder by the same contact, and are adjacent to each other. The row decoder is not connected to the gate lines of the source line side select transistors other than the adjacent blocks, and the row decoder selects the gate lines of the source line side select transistors adjacent to each other between the blocks as a set. Nonvolatile semiconductor memory device. 4. The memory cell is characterized in that a charge storage layer and a control gate are laminated on a semiconductor substrate, and electric rewriting is performed by transfer of charges between the charge storage layer and the substrate. The non-volatile semiconductor memory device according to claim 1.