JPH08255191A - Logic simulator and hardware description conversion device - Google Patents

Abstract

PURPOSE: To perform simulation fast by referring to a kind, etc., that a designer has set for an object during the simulation. CONSTITUTION: A simulation processing part 2 performs signal value update processing for a signal by a signal substitution execution part 20 and performs process execution processing for a process by a process execution part 21. At this time, the kind of the object stored in an object kind storage part 1 is referred to and the object stored in an object storage part 3 is processed only as to process items determined for the object kind. In this case, the simulation processing part 2 when performing the signal value update processing for the signal by the signal substitution execution part 20 finds the object kind of the signal by referring to the object kind storage part 1 and processes the object only as to the process items determined for the signal kind of the obtained signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CAD (Computer Aided Design) system for supporting hardware design,
In particular, it relates to a logic simulator (function / logic simulator) and a hardware description converter.

[0002]

[Prior art]

(1) In recent years, along with the increase in the scale of hardware to be designed such as LSI, a CAD system has been developed that supports design from a higher order process such as functional design for the purpose of improving design efficiency.

The input data of the CAD system is V
A hardware description language (hereinafter referred to as HDL) for hardware design such as HDL and Verilog HDL is used.

Since these HDLs can handle delays and asynchronous operations, the language specifications are designed based on the concept of event driven simulation. Here, the event-driven simulation is a method in which only when the output signal value of a module changes at a certain time, arithmetic processing is performed on the module that receives the output signal and the simulation proceeds. This method is widely used as a general method for handling the above delay and asynchronous operation.

A typical procedure of event driven simulation is as follows. step0: Initial process execution All parallel operation units (hereinafter, referred to as processes) are operated, and signal value update requests are registered in the time wheel (hereinafter,
Call signal substitution reservation).

Step 1: time update If there is a signal value update request at the current time, the next st
Move to ep2. If it does not exist, the time is advanced to the place where it exists, and then the process proceeds to the next step 2. Step 2: Signal substitution Update the signal value at the current time. Step 3: Process execution The process driven by the signal of Step 2 is operated to make a signal substitution reservation. Then, the process returns to step 1 above.

By the way, signals having various properties as described below are mixed in the signals in the event driven simulation. 1. Signals that act as drive signals that start the process and signals that do not. 2. A signal that simultaneously has substitution requests for multiple future times and a signal that has at most one substitution request at future times. Signals with and without attribute information to be collected during execution of simulation 4.1 Types that can be expressed as values in words (eg BIT type and CH
Signals of type (for example, ARACTER type) and signals of type (for example, TIME type) that requires two words Hereinafter, examples will be given for each of the above.

1. In the simulation model described in VHDL shown in FIG. 15 and the subsequent FIG. 16, the process P0 is activated when an event occurs in R. Thus, R acts as a drive signal. On the other hand, although the value of D is referred to, no process is activated by the occurrence of an event in D.

2. In the simulation model shown in FIG. 17, the signals E and CLK always have only one substitution reservation at a future time. However, at the maximum, the signal D has the signal substitution reservations for eight future times at the same time.

3. CK in FIGS. 15 and 16 is CK ′
Since there is a reference of “event”, it is necessary to set information as to whether or not an event has occurred at that time when a signal is assigned. Further, DIN in FIG. 18 is DIN'la
Since there is a reference st_value, it is necessary to hold the previous value of the previous one.

4. There is a standard type called TIME type in VHDL, and its value is the minimum unit fs (femtosecond).
To the maximum unit hr (hour). In order to be able to handle all TIME type units, two words are required to represent the value of a TIME type signal. For example, in the description shown in FIG. 19, since the signal A is a bit type, it is sufficient to change the value by substitution processing or the like for one word, but the signal DELAY needs to be changed for two words. .

In the conventional logic simulator, all signals are processed in the same manner without considering the characteristics of the signals as described above. Therefore, the drive processing is performed even for a signal that does not work as a drive signal, the substitution request (waveform) is updated even for a signal having only one substitution request, or even for a signal that does not need to hold attribute information. Unnecessary processing such as storing attribute information was also performed. This has been a cause of impeding the speedup of simulation.

On the other hand, some processes include those that operate only when the drive signal has a specific value and those that operate regardless of any value. For example, VHD in FIG.
In the process described in L description, when the value of the control signal CLK is "1", the value is transferred, but when it is "0", nothing is operated. On the other hand, in the process of FIG. 21, value transfer occurs regardless of whether the value of CLK is “1” or “0”.

In the conventional logic simulator, the process activation process is similarly performed without distinguishing such processes, which has been a cause of impeding the speedup of the simulation.

(2) In recent years, with the increase in the scale of hardware to be designed such as LSI, the CA that supports design from the upper step of design such as functional design for the purpose of improving the design efficiency.
The D system is being developed.

The input data of the CAD system is V
A hardware description language for hardware design such as HDL and Verilog HDL is used.
DL is being standardized by IEEE and is being widely used. FIG.
8 shows a description example of VHDL.

In VHDL, the simulation result differs for each simulator for the same HDL description.
It is strictly defined in the language specification including the simulation method in consideration of the problem of the conventional HDL that there is a case where there is no compatibility. One of these items is resolution.

The resolution is a signal such as a signal S in the description of FIG. 48, which has two or more components in the process or the lower hierarchy as a substitution source of the signal value (in FIG. 48, S is , The process P1 and the output port of the component instance statement B0 have two substitution sources). The value of the resolution signal is obtained by calling a function called a resolution function based on the values of these substitution sources.

The resolution function is defined for the data type of the signal. Further, there is a rule that the number of sources of signals of the data type for which the resolution function is not defined must be one or less.

Data type std_l of signal S in FIG.
As for the logic, for example, a resolution function as shown in FIG. 49 is defined. That is, std_logi
c is a subtype that enables resolution to the std_ulotic type, which is a nine-valued data type. The argument s of the function resolved in FIG. 49 is
This is an array of sources, and the operation is sequentially performed between the intermediate result "result" and the source in accordance with the resolution_table in Fig. 49 to obtain the result. In particular,
When the number of sources is one, the resolution result becomes the value of the source by the processing on the THEN side of the IF statement.

Resolution is typically used when modeling the bus structure of hardware. Many hardware modules interface with a bus external to the chip or have an internal bus, so that the user is conscious of the hardware structure by VHDL, for example, the specification description at the register transfer level or the gate level. , The data type used is a resolvable data type,
For example, std_logic. In this case, the resolution function is called for all signals, including the case where there is one source.

However, a signal such as a bus which originally requires resolution is a small part of the circuit,
The resolution process for other signals, that is, the function call process for returning the value of the source itself as shown in FIG. 49 has a problem that it becomes an overhead at the time of simulation. In particular, it has been one of the reasons why large-scale circuit simulation cannot be executed at high speed.

[0023]

[Problems to be Solved by the Invention]

(1) In the simulation model, signals and processes having various properties as described above are mixed,
Conventional logic simulators perform uniform processing on all signals without considering the characteristics of the signals, and also perform wasteful processing on certain signals and processes. There was a problem that I could not do it.

The present invention has been made in view of the above circumstances, and provides a logic simulator that performs processing according to the characteristics of each signal or process to eliminate wasteful processing and speed up simulation. The purpose is to provide.

(2) In the hardware specification description,
Although most signals do not require resolution, some signals, such as signals that represent bus structures, require resolution. It is written by using the data type for resolution, and as a result, in the conventional logic simulator, the resolution function is called even for the signal substitution in which the source which originally does not need resolution is one. There was a problem that it was an overhead in the simulation.

The present invention has been made in view of the above circumstances, and it is possible to speed up the simulation by detecting a signal that is originally unnecessary for resolution processing and omitting the resolution processing for the signal. It is an object of the present invention to provide a logic simulator and a hardware description conversion device.

[0027]

A logic simulator according to the present invention (Claim 1) relates, for at least one type of object, the correspondence between each element belonging to the object and the object type obtained by classifying the object according to its property. When executing the object type storage means for storing and the element of the object, the object type of the element of the object to be executed is obtained by referring to the object type storage means, and according to the processing procedure defined for each object type, It is characterized by comprising a simulation processing means for processing the elements of the object.

Here, the objects include, for example, a signal object and a process object. Each element belonging to an object is each signal when the object is a signal object, for example.

The properties of the object include, for example, a simulation cycle or time at which an event or substitution has occurred for a signal, presence / absence of attribute information related to a past value of the signal, and a waveform update including a future value update request for the signal. The presence / absence of processing, the presence / absence of a process (parallel operation unit) to be activated by an event to a signal, and the condition regarding a signal to activate the process are included.

A logic simulator according to the present invention (claim 2) is the logic simulator according to claim 1, wherein elements of the object stored in the object type storage means and the object are stored based on the hardware description to be simulated. Is further provided with an object type determining means for determining an object type corresponding to the element.

Further, the logic simulation method according to the present invention stores, for at least one type of object, the correspondence between each element belonging to the object and the object type obtained by classifying the object according to its property,
When executing the element of the object, the object type of the element of the object to be executed is obtained from the stored correspondence, and the element of the object is processed according to the processing procedure defined for each object type. To do.

Further, the logic simulation method according to the present invention, for at least one type of object, based on the hardware description to be simulated, each element belonging to the object and the object type obtained by classifying the object according to the property thereof. When the element of the object is executed, the object type of the element of the object to be executed is determined from the determined correspondence, and the processing of the element of the object is performed according to the processing procedure defined for each object type. It is characterized by performing.

The logic simulator according to the present invention (claim 3) is an analysis means for obtaining the number of sources of signals used in a simulation model to be simulated, and data to be subjected to resolution processing. A data type storing means for storing a type, and a signal assignment statement for a signal of a data type stored in the data type storing means in the simulation model, and the number of sources obtained by the analyzing means is 1 With respect to (1), there is provided a code generating means for generating a code directly substituted into the resolution signal itself.

A logic simulator according to the present invention (claim 4) is an analysis means for obtaining the number of sources of signals used in a hardware description to be simulated, and a data type for which resolution processing is omitted. And a data type stored in the data type storage means in the hardware description, the number of sources obtained by the analysis means is one, and When there is an output port or an input / output port of a lower component to be connected, it is characterized by comprising code generating means for generating a code for directly connecting the port to the resolution signal itself.

A hardware description converter according to the present invention (claim 5) is a hardware description storage means for storing a specification description in a hardware description language, and a hardware description stored in the hardware description storage means. An analysis means for obtaining the number of sources of signals in the data, a data type storage means for storing a data type for which resolution processing is omitted, and a data type storage means for storing the data type in the hardware description. And a hardware description conversion unit for generating a hardware description in which a signal declaration of a data type signal having a single source number obtained by the analysis unit is replaced with a signal declaration of a non-resolution type. It is characterized by that.

Preferably, the signal declaration of the resolution type is replaced with the signal declaration of the non-resolution type based on the signal assignment statement in the hardware description language. Further, preferably, the resolution type signal declaration is replaced with the non-resolution type signal declaration based on the component instance statement in the hardware description language. Further, preferably, the resolution type signal declaration is replaced with the non-resolution type signal declaration based on the signal assignment statement and the component instance statement in the hardware description language.

Further, the logic simulation method according to the present invention stores the data type for which the resolution processing is omitted, obtains the number of sources of the signals used in the hardware description to be simulated, and stores it. It is characterized in that a code for directly substituting the resolution signal itself is generated for the signal substitution statement for the signal of the data type and the obtained number of sources is one.

Further, the logic simulation method according to the present invention stores the data type for which resolution processing is omitted, obtains and stores the number of sources of signals used in the hardware description to be simulated. Data type, the number of sources required is one, and if there is an output port or input / output port of the lower-level component connected to the source, connect that port directly to the resolution signal itself. It is characterized by generating a code for

Further, the hardware description conversion method according to the present invention stores the data type for which resolution processing is to be omitted, obtains the number of sources of signals in the hardware description to be simulated, and The hardware description is characterized by generating a hardware description in which a signal declaration of a stored data type signal and the number of obtained sources is 1 is replaced with a non-resolution type signal declaration.

[0040]

According to the present invention (Claim 1), for at least one type of object (for example, one or both of a signal object and a process object), each element (for example, each signal) belonging to the object and the object are determined according to their characteristics. The correspondence with the classified object type is stored, and when executing each signal that is an element of the object, the object type of the element of the object to be executed is obtained from the object type storage means, and defined for each object type. The elements of the object are processed according to the processing procedure described above.

Therefore, according to the present invention, it is possible to perform the processing according to the type of the signal, the process, etc. (that is, the processing in which unnecessary processing is omitted in the type is omitted) during the logic simulation, and the simulation can be performed at high speed. Become.

As a result, it is possible to provide a simulation environment in which the simulation time is shortened, and it is possible to improve the design efficiency of the circuit and the debugging work efficiency when the designer performs the logic simulation.

According to the second aspect of the present invention, by providing the object type determining means, even if the designer does not set the type of the signal object or the process object,
The type of object can be determined automatically. Then, according to the automatically determined type of the object, it is possible to perform a process according to the type (that is, a process in which unnecessary processes for the type are omitted) and to perform the simulation at high speed.

Further, in the present invention (claim 3), the number of sources of the signals used in the hardware description to be simulated is obtained, and the signal of the data type to be subjected to the resolution processing is obtained. For the signal assignment statement for the signal whose source number is 1, the code to be directly assigned to the resolution signal itself is generated.

Therefore, according to the present invention, the resolution process can be omitted for the signal having one source during the logic simulation, and the simulation can be performed at high speed.

In the present invention (Claim 4), the number of sources of signals used in the hardware description to be simulated is obtained, and the data type to be subjected to resolution processing is omitted. If the number is one and there is an output port or input / output port of a lower component connected to the source, a code that directly connects the port to the resolution signal itself is generated.

As described above, according to the present invention, when the source of the connection destination signal of the out or inout port of the component instance statement is one, by connecting the resolution signal itself to the port, the lower hierarchy The resolution processing can be omitted in the execution of the signal assignment statement from the to the relevant port, and the simulation can be speeded up.

In the present invention (Claim 5), the number of sources of the signal in the hardware description to be simulated is obtained, and the number of sources of the signal of the data type to be subjected to the resolution processing is determined. A hardware description in which one signal declaration is replaced with a non-resolution type signal declaration is generated.

Therefore, according to the present invention, a signal of the resolution type having one source is detected, and the data type of the signal is changed to the non-resolution type. Thus, the resolution processing can be omitted and the simulation can be performed at high speed.

As described above, according to the present invention, it is possible to provide a simulation environment in which the simulation time is shortened. Therefore, it is possible to improve the circuit design efficiency and the debugging work efficiency in performing the function / logic simulation by the designer.

[0051]

Embodiments of the present invention will be described below with reference to the drawings.

(1) (Example 1) First, Example 1 will be described.

<Main Configuration / Operation of First Embodiment> The function / logic simulator according to the first embodiment has an object storage section (3) for storing objects such as signals and processes generated from the hardware description to be simulated. ), And an object type storage unit (1) for storing the correspondence between each object (for example, signal ID) and the object type in which the object is classified according to its various properties
And when the processing of the object stored in the object storage unit (3) (signal value update processing for a signal, process execution processing for a process, etc.) is executed, the object stored in the object type storage unit (1) A simulation processing unit (2) is provided, which refers to the type of the object and executes the processing of the object for the minimum necessary items determined for each type of the object.

In this embodiment, when the simulation is performed, the signal type stored for each object is used, so that the signal value update processing procedure and the process execution processing procedure are required for the signals and processes to which the type is assigned. I will limit it to the minimum processing.

(Effect) In the conventional simulator, the same processing is performed for all objects such as signals and processes regardless of their properties. Therefore, wasteful processing is often executed, which impedes the speedup of simulation. Was there.

According to this embodiment, a type is provided for an object such as a signal or a process, and when the object is executed, the type is referred to so that only the minimum necessary processing determined for each type is performed. By doing so, the simulation can be performed at high speed.

(Detailed Description) The present invention can be applied to any object such as a signal, a process, or both a signal and a process. In the first embodiment, the present invention is applied to a signal. It is given as a specific example. An example in which the present invention is applied to a process that is one of objects will be described in a modified example.

FIG. 1 shows the configuration of the function / logic simulator of this embodiment. This function / logic simulator includes an object type storage unit 1, an object storage unit 3, and a simulation processing unit 2. The object storage unit 3 is internally provided with the signal storage unit 30 and the process storage unit 3.
1 and the simulation processing unit 2 has a signal substitution execution unit 20 and a process execution unit 21 inside.

The object storage unit 3 includes the signal storage unit 30.
The signal, which is one of the objects generated from the hardware description to be simulated, is stored in
Similarly, the process is stored in the process storage unit 31.

The object type storage unit 1 stores the correspondence between each object and its object type. Here, for each signal, a signal type described later is stored.

In the simulation processing unit 2, the signal substitution executing unit 20 performs the signal value updating process for the signal, and the process executing unit 21 performs the process execution process for the process. At that time, the type of the object stored in the object type storage unit 1 is referred to, and the object stored in the object storage unit 3 is processed only for the processing items defined for the object type.

In this case, since the signal type is stored in the object type storage unit 1, the simulation processing unit 2 performs the signal value updating process on the signal by the signal substitution executing unit 20. The type is obtained by referring to the object type storage unit 1, and the object is processed only for the processing item determined for the signal type of the obtained signal.

Here, in the present embodiment, the characteristics of the signal to be handled are: Whether or not it becomes a driving signal for the process Existence of the possibility of multiple substitution reservations 3. Focus on the presence / absence of signal attribute information that is referenced during simulation. Then, eight combinations of signal types are defined as shown in FIG. 2 by a combination of the above three characteristics.

Now, when performing a simulation on a simulation model including the description as shown in FIG. 3, the object type storage unit 1 stores the signal type as shown in FIG. In FIG. 4, 8 types of signal types are coded as numerical values from 0 to 7 based on the characteristics of the signals as shown in FIG. For example, in FIG.
The signal A described therein is a drive signal for the process P2, and there are multiple substitution reservations due to waveform substitution in the process P0, and there is a reference to attribute information during simulation in the process P2. Since it is necessary to hold the previous value, it is coded as "7". On the other hand, the signal F described in FIG. 3 does not become a drive signal of any process, and there is a waveform substitution request in the process P3, but there is no reference of attribute information. For this reason, the signal F is coded as "2".

In addition to the method described above, a method of classifying a signal by giving priority to the type determination to the nature of the signal is conceivable for determining the signal type. For example, as shown in FIG.
The one having the signal property (3) of is preferentially classified into type 1,
It may be determined by setting the type other than the type 1 having the property (2) to 2, the other type having the property (1) to 3, the remaining type not having the property 4, and the like. . In this case, since the signal having the attribute information reference of the signal during the simulation is classified into the type 1 without depending on other properties, the signals A and C described in FIG. 3 are preferentially classified according to the type. Is set to 1.

In the present embodiment, the signal substitution executing section 20 of the simulation processing section 2 which performs the signal substitution processing based on the object type performs the processing shown in FIG. 6 and the subsequent FIG.

The signal substitution executing section 20 refers to the signal type of the signal stored in the object type storing section 1 during the simulation, and performs the signal substitution process according to FIGS. 6 and 7. In this case, only the minimum necessary processing that should be performed on the signal is performed, so that the simulation can be performed at high speed.

For example, when the signal A is processed by the signal substitution process, referring to FIG. 4, since the type stored in the object type storage unit 1 is 7, from case 7 in FIGS. 6 and 7, Set the attribute information of the signal, update the signal value, start the process, and update the substitution request.

Similarly, when processing the signal B, the signal B
Since the type is 6, the signal value is updated, the process is started, and the substitution request is updated as in case 6. In this case, the attribute information of the signal is not set.

Further, since the type of signal C is 5,
As in case 5, the attribute information of the signal is set, the signal value is updated, and the process is activated. In this case, the substitution request is not updated.

Since the type of signal D is 4, case4
As described above, the signal value is updated and the process is started. In this case, the substitution request is not updated and the signal attribute information is not set.

Since the type of the signal E is 3, case3
As described above, the signal attribute information is set, the signal value is updated, and the substitution request is updated. In this case, the process is not started.

Since the type of the signal F is 2, case2
As described above, the signal value of the signal is updated, and the substitution request is updated. In this case, process activation and signal attribute information setting are not performed.

Since the type of the signal G is 1, case1
As described above, the attribute information of the signal is set and the signal value is updated. In this case, the substitution request is not updated and the process is not started.

Since the type of the signal H is 8, case0
As described above, only the signal value is updated. In this case, setting of signal attribute information, process start, and substitution request update are not performed.

As described above, according to this embodiment, a type is set for an object such as a signal or a process, and when the object is executed, the type is referred to and only the minimum required processing determined for each type is performed. By doing so, the simulation can be performed at high speed.

<Modification 1 of Embodiment 1> In the embodiment 1 described above, the characteristics of the signal are: Whether or not it becomes a driving signal for the process Existence of the possibility of multiple substitution reservations 3. An example of the substitution process for the type focusing on the presence or absence of the signal attribute information referred to during the simulation has been given, but other properties that can be used when determining the type are also conceivable.

For example, in VHDL, there is a standard type called TIME, and this value can range from fs as the minimum unit to hr (hour) as the maximum unit. In order to be able to handle all TIME type units, two words are required to represent the value of a TIME type signal. In the description shown in FIG. 19, since the signals A and CLK are of the bit type, the value can be expressed by one word, but DELAY is of the TIME type, so two words are required for the value expression.

As described above, paying attention to the properties that "substitution of 2 words is required for substitution of values" and "substitution of only 1 word is necessary", substitution of 1 word should be executed. The type of signal is 1, and the type of signal for which substitution execution of 2 words is to be performed is 2. In this case, the processing of the signal substitution processing unit 20 is as shown in FIG. 8, for example.
Since the signal A is the type 1 and the signal DELAY is the type 2, the process of substituting the value of only one word and the process of substituting the value of two words are performed, respectively.

<Modification 2 of Embodiment 1> In Embodiment 1,
A signal substitution processing unit 20 according to a signal type, using an object whose type is stored in the object type storage unit 1 as a signal.
Has shown an example of accelerating the signal substitution process, but instead of performing the process according to the type of the signal, or in addition to performing the process according to the type of the signal, the process type is set to the object type storage unit 1. The process activation processing of the process execution processing unit 21 can be speeded up according to the type of process.

For example, when the type of FIG. 11 obtained from the property shown in FIG. 10 is stored in the object type storage unit 1 for the process described as shown in FIG. 9, it is unnecessary depending on the type of process. It is possible to suppress process startup and speed up simulation.

For example, the process P1 performs a meaningful operation only when the value of the drive signal CLK is "1", and when it is "0", it is false even if it is started, so that nothing is processed. Type 1 is assigned to such a process. In the process starting process of type 1, the process is started only when the value of the drive signal is "1", and the process is not started in other cases. In this way, useless activation can be omitted.

(Second Embodiment) Next, a second embodiment will be described. <Main Configuration / Operation of Second Embodiment> The function / logic simulator according to the second embodiment includes a description storage unit (4) for storing a hardware description to be simulated, a signal in the stored hardware description, and An object type determination unit (8) that determines an object type classified by various characteristics of objects such as processes, an object type (for example, a signal ID), and an object type determined by the object type determination unit (8). An object type storage unit (1) for storing correspondence, an object storage unit (3) for storing objects such as signals and processes generated from the hardware description, and an object stored in the object storage unit (3) Processing (signal value update processing for signals and process execution processing for processes Etc.) is executed, the type of the object stored in the object type storage unit (1) is referred to, and the processing of the object is performed for the minimum necessary items determined for each type of the object. And a simulation processing section (2). Further, the object type determination unit (8) stores a feature extraction unit (6) that extracts a feature (property) used for object type determination from the hardware description stored in the description storage unit (4), and the extracted feature. And a feature storage unit (7) for determining the object type from the stored features. That is, this embodiment is the same as the first embodiment.
In addition to the configuration of the modification and its modification, an object type determination unit (8) for the description storage unit (4) is further provided.

In the present embodiment, the object type determination unit (8) determines the object type of the object from the hardware description to be simulated stored in the description storage unit (4), which is the first embodiment or its modification. It is stored in the object type storage unit (1) described in the example. After that, the simulation proceeds while referring to the object type, as in the first embodiment and its modification.

(Effect) According to this embodiment, the type of the object can be automatically determined without the designer setting the types of the signal object and the process object.
Then, according to the automatically determined object type, it is possible to obtain the same effects as those shown in the first embodiment and its modification.

(Detailed Description) The present invention can be applied to any object such as a signal object, a process object, both a signal object and a process object, and the like. Here, the present invention is applied to a signal object as a specific example.

FIG. 12 shows the configuration of the function / logic simulator of this embodiment.

This function / logic simulator comprises a description storage unit 4, an object type determination unit 8, an object type storage unit 1, a simulation processing unit 2, and an object storage unit 3. The object storage unit 3 has a signal storage unit 30 and a process storage unit 31 inside, and the simulation processing unit 2 has a signal substitution execution unit 20 and a process execution unit 21 inside. In other words, the description storage unit 4 and the object type determination unit 8 are further provided in the configuration of the first embodiment and its modification.

The description storage unit 4 stores the hardware description to be simulated.

The object type determining unit 8 automatically determines at least one type of objects such as signals or processes from the stored hardware description of the simulation model. The determined type is stored in the object type storage unit 1.

The feature extraction unit 6 extracts the features used for object type determination from the hardware description stored in the description storage unit 4. The feature storage unit 7 stores the extracted features. The object type determination unit 5 determines the object type from the stored characteristics.

The configurations and functions of the object type storage unit 1, the simulation processing unit 2, the object storage unit 3, the signal substitution execution unit 20, the process execution unit 21, the signal storage unit 30, and the process storage unit 31 are the same as those of the first embodiment and its embodiments. Since it is the same as the modified example, the description thereof is omitted here.

Now, for example, it is assumed that the description storage unit 4 stores the description of the simulation model as shown in FIG. At this time, the feature extraction unit 6 extracts the feature of the signal and stores it in the feature storage unit 7. For example, the table shown in FIG. 2 is created and stored in the table format.

For example, since the signal A is a sensitivity list of the process P2, it has a property of being a driving signal for the process. Further, since the waveform is substituted in the process P0 and the last_value is referenced in the process P2, it can be understood that a plurality of substitution reservations may occur and the attribute information is referenced during the simulation. Therefore, in the table shown in FIG. 2, the properties of (1), (2), and (3) are ◯, ◯, and ◯, respectively.
Becomes On the other hand, it can be seen that the signal G does not become a drive signal of any process and there is no waveform substitution, but it has a property that attribute information is referred to. Therefore, in the table shown in FIG. 2, x, x, and o.

The type determining section 5 determines the type from the features thus extracted. FIG. 13 shows an example of the algorithm of the type determining unit 5, and FIG. 14 shows another example.

When the type determining unit 5 uses the algorithm of FIG. 13, the type is determined as shown in FIG. In the algorithm of FIG. 13, when each of property 1, property 2 and property 3 is established, 1 is set in each of the lower 2nd bit, 1st bit and 0th bit of the type code. Therefore, for example, since all the properties 1, 2, and 3 are true for the signal A, its type code is a binary number 111.
₍₂₎ That is, it becomes 7. In addition, regarding the signal F, the property 2
Since that only holds, the code is 010 ₍₂₎ ,
That is, it becomes 2.

When the algorithm of the type determining unit 5 is as shown in FIG. 14, the type is determined as shown in FIG. For example,
In the case of the signal B, the property 3 is x (see FIG. 2), and if in the first row is false. Since the property 2 is ◯, the fourth line is true and the type is 2 in the fifth line.

By storing the thus determined type in the object type storage unit 1 and performing the signal substitution process and the process starting process as described in the first embodiment and its modification, waste during the simulation is eliminated. The simulation can be speeded up.

<Modification 1 of Embodiment 2> Embodiment 2 described above
Then, although the type of the signal once stored does not change during the simulation, the signal is stored so that the attribute information is stored when the attribute of the signal such as last_value is referred to during the simulation for debugging. There is also a method of changing the attribute and reusing the type, or returning to the original type when the reference is stopped and the simulation is performed at high speed.

<Modification 2 of Embodiment 2> In Embodiment 2,
Although the VHDL description is stored in the description storage unit 4, any one can be used as long as it can extract the characteristics of the object such as the signal and process of the simulation model. It also includes parse trees and drawings.

<Modification 1 of Embodiments 1 and 2> The above description of Embodiments 1 and 2 is an example of VHDL description, and the case of the event driven method is described. It can also be applied when performing simulation by the level sorting method.

<Modification 2 of Embodiments 1 and 2> In addition, although the example described in one layer has been described above, the same can be applied to a simulation model described in a plurality of layers.

(2) (Third Embodiment) Next, a third embodiment will be described. <Main Configuration / Operation of Third Embodiment> The logic simulator according to the third embodiment stores an analysis unit (113) for obtaining the number of signal sources in a simulation model, and a data type for which resolution processing is omitted. Of the data type storage unit (112) and the assignment statement for the signal of the data type stored in the data type storage unit (112) and the obtained number of sources is 1 And a code generation unit (114) for generating a code that is directly substituted into the resolution signal itself instead of the source.

In this embodiment, the code generator (114)
Based on the analysis result by the analysis unit (113), the resolution is omitted for the signal of the type stored in the data type storage unit (112) and the number of sources is 1. Generate faster code.

<Effect> In the conventional simulator, the resolution processing is performed on all the resolution type signals even if there is only one source.

According to the present embodiment, a resolution type signal having one source is detected, and a simulation code for which no resolution is performed is generated for this signal, thereby performing simulation. Will be able to do fast.

<Detailed Description> The case of the compilation simulator will be described below as an example.

FIG. 22 shows the configuration of the logic simulator of this embodiment. This logic simulator includes a hardware description storage unit 111, a data type storage unit 112, and an analysis unit 1.
13, a code generation unit 114, and a code storage unit 115.

The hardware description storage unit 111 is shown in FIG.
It is for describing a source program written in such a VHDL language.

The data type storage unit 112 stores the data types for which resolution can be omitted. The data type is a data type having a resolution function that returns the value of the source when there is one source. For example, std_logi defined in the IEEE package.
Type c corresponds. FIG. 49 shown above is an example of the resolution function. The data type can also be automatically detected by, for example, simulating a resolution function for all one scalar element inputs and checking whether the results match the inputs. For example, if there are four-valued data types, those four
The simulation result for each input pattern may be compared with the input.

The data type thus obtained is stored in the data type storage unit 112. Here, std_logi is stored in the data type storage unit 112.
It is assumed that the c type is stored.

The analysis unit 113 includes the data type storage unit 11
The VHDL description in 1 is analyzed to detect the resolution signal, and the correspondence between the signal name, the number of sources and the data type is registered in the table. FIG. 23 shows an example of this table.

The code generation unit 114 generates a code for elaborating the VHDL description and a code for executing the statement as the C program corresponding to the VHDL description while referring to the table created by the analysis unit 113.

The code storage unit 115 stores the generated C program.

The simulator execution module is generated by linking the C program stored in the code storage unit 115 and the simulation library created in advance.

The case of the VHDL description shown in FIG. 48 will be described below.

FIG. 24 shows a processing flow of the analysis unit 113.

In step S31, each concurrent sentence is examined. In FIG. 48, a process statement P0, a concurrent signal assignment statement P1, and a component instance statement B
0 and B1 are taken out in order.

In step S33, a branch is made between the component instance statement and other cases. In FIG. 48, P
In the case of 0 and P1, NO is obtained in step S33, and the process proceeds to step S38.

At step S38, the signals substituted in the concurrent statement, that is, S0 at P0 and S at P1 are registered in the table of the format shown in FIG. This table stores resolution type signal names, data types, and the number of sources.

FIG. 25 shows the flow of table registration processing.

In step S41, if the signal is a vector signal, it is decomposed into scalar elements. For example, in FIG. 48, S1 is a vector signal, which is decomposed into scalar elements S1 (0) and S1 (1).

In the loop of steps S42 to S44, the decomposed signals are registered in the table. Therefore, when P0 and P1 are processed, the entries of S0 and S1 are created, and std_logic
, And set the number of sources to 1, respectively. When the vector signal is decomposed into a scalar, the type of the scalar element is registered by tracing the definition of the VHDL data type. For example, std_logic_vector in FIG.
If r, then std_, which is the type of the scalar element
Register the logic.

When the component instance statement is B0 or B1 in step S33, the connection relation of each port is checked (step S34), out
Alternatively, the signal connected to the inout port is registered in the table (steps S36, 37). Therefore, S and S1 (0) in B0 and S1 in B1
(0) and S1 (1) are registered in the table according to the flow of FIG. 25 described above.

As a result, the contents of the table of the analysis unit 113 are set as shown in FIG. In the table, S and S1 (0) were registered twice, so
The number of sources is 2.

Next, the code generation section 14 refers to the table of the analysis section 13 and executes C for simulation.
Generate a program. There are two types of C programs. One is elaboration code that creates an object such as a process or a signal in the VHDL description, and the other is code that executes a statement in the VHDL description. An example of the elaboration code generated by the code generation unit 14 is shown in FIG. 26 and the subsequent FIG. 27, and an example of the execution code generated by the code generation unit 14 is shown in FIG. However, as for the elaboration codes in FIGS. 26 and 27, only the portion related to the present invention is shown.

The 20th line in FIG. 26 generates a data structure h corresponding to the hierarchy of the VHDL description in FIG. Lines 22 to 26 and 44 (FIG. 27) are codes for generating information on ports, signals, resolution information, and processes by the number of first arguments.

Information contained in these structures is shown in FIG.
32. 29 shows an example of the process structure, and FIG.
Shows an example of a port structure, FIG. 31 shows an example of a signal structure, and FIG. 31 shows an example of a resolution structure.

The description of FIG. 48 includes one port, four signals, and one process (including a concurrent assignment statement), four, and
Since there are two, a code is generated by the above actual argument. Further, from FIG. 23, since there are four resolution type signals, four pieces of resolution information are generated.

The function st_f21 on the 31st line (FIG. 26)
Sets the resolution information corresponding to the field of f21 of the signal structure of FIG. Line 48 (Fig. 2
Similarly, st_f22 in 7) is set in the f22 field.

On the 27th line, pointer arrays for pointing the signal structures corresponding to the resolution sources are generated by the number of arguments. Since the total number of sources is 6 according to the table (FIG. 23) of the analysis unit 13, the actual argument is 6
Becomes

The 61st and 74th lines generate a hierarchical structure of the component instance statements B0 and B1.

The 47th line, the 54th line, and the 76th line generate a resolution source created by a process or a component instance. The source uses the signal structure shown in FIG.

The 51st line, the 58th line, the 66th line, the 67th line, the 79th line, and the 80th line connect the structures for the signal pointer column and the source.

The links between the data structures on the memory which are created when the functions of FIGS. 26 and 27 are executed are shown in FIG.
And shown in FIG.

FIG. 33 shows the link between the resolution signal S and its source. In the figure, 93 is the signal S,
Since S is a resolution signal, it has a resolution structure (920 in the figure), and from there, each source (9 in the figure) via each pointer (921, 922 in the figure).
7,98).

FIG. 34 shows the relationship between the process and the signal.
The fields f0, f1 and f2 of the process structure point to the beginning of the source sequence created by the port, signal and process, respectively. Lines 70 and 83 in FIG. 27 are calls of the function bind_buft that expands the lower hierarchy of the component using the connection destination signal structure of the port specified by the port map as an actual argument.

Scalar out or inou of the function
FIG. 35 shows a flow for generating an actual argument connected to the t port. The vector port can be treated in the same manner by regarding it as a plurality of scalar ports, for example.

For example, component instance statement B
For the port DO1 of 1, the connection destination S1 (0) is obtained in step S110, and the data type std_logic is YES in step S111 because the type is the data type stored in the storage unit 12.
When the table of FIG. 23 is referred to in step S112, the number of sources is 2. Therefore, the process proceeds to step S114,
S source signal structure cmpnt_srcsig + 0
Is passed as the second actual argument.

On the other hand, for the port DO2, the connection destination S1 (1) is obtained in step S110, and step S11
23. However, referring to the table of FIG. 23, the number of sources is 1, so the procedure proceeds to step S113.
Instead of the source of S1 (1), the signal structure intsig + 3 of S1 (1) itself is passed as the third actual argument.

FIG. 36 shows the data structure generated by the above call of bind_buft. In the figure, 121 to 123 represent the ports DI, DO1, and DO2 of the component instance B1. The f10 field of DO1 connects to the source of S1 (0), but the f10 field of DO2
The field is not the source of S1 (1), but S1 (1)
Connect to yourself.

As described above, when the source of the connection destination signal of the out or inout port of the component instance statement is one, by connecting the resolution signal itself to the relevant port, the connection from the lower layer to the relevant port is performed. In the execution of the signal assignment statement, the resolution process can be omitted, and the simulation speed can be increased.

In connection with the in port, the corresponding signal structure itself is always connected.

Here, the dotted line 124 in FIG. 36 shows the connection relationship of the port DO2 according to the conventional method. That is,
In the conventional method, even for a signal having one source, the source is used as the connection destination of the port. Therefore, the signal substitution to the relevant port becomes the substitution to the source, and the resolution function is called in the later simulation cycle, which is an overhead of the simulation.

Next, the execution code generation by the code generation unit 14 will be described.

In the execution code, the process structure f0,
The object is accessed based on the head address indicated by f1 and f2. Therefore, assuming that the destination pointed to by the f1 field of the process (91 in FIG. 34) is intsig, the signals S (93 in FIG. 34) and S0 are respectively ints
It can be accessed by ig + 0 and intsig + 1. Also,
If the destination pointed to by the f2 field is srcsig, P1
Source of S (97 in FIG. 34) is srcsig + 0
Becomes

Since only the code of the signal assignment statement is relevant to the present invention, the code generation of the signal assignment statement will be described.

FIG. 37 shows a code generation flow of a signal assignment statement for a scalar element.

For vectors, for example, the above code generation flow may be applied to each scalar element. For example, regarding the conversion of the assignment statement to S0 on the 22nd line in FIG. 48, the signal name S0 of the assignment destination is extracted in step S130, and in step S131, the data type is the data type stored in the storage unit 12. YES
Then, referring to the table of FIG. 23 in step S132, since the number of sources is 1 or less, step S1
In step 33, a code to be assigned to the signal structure of S0 is generated. As described above, S0 uses the address intsig pointed to by the f1 field of the process P0 as a reference, and int
Since it becomes sig + 1, the signal substitution execution function is assig
If n_inertial, then assign_ine
rtial (intsig + 1,3,0). Here, the argument of the above function is, in order, the pointer substitution value (coded in the simulator internal code) delay to the head of the signal structure of the substitution destination.

As described above, since S0 has one source, a signal structure srcsig + 0 representing the source (here, p is a process structure, srcsig = 1).
Instead of substituting for p-> f2), it is directly substituted for the signal structure representing S0. As a result, the execution of the resolution function for S0 can be omitted, and the simulation speed can be increased.

FIG. 28 is an example of the execution code of the whole process P0. The argument p is a pointer to the process structure, and exec_wait_for is an execution function of the wait statement.

On the other hand, with regard to the concurrent assignment statement P1, when the table of FIG. 23 is referred to in step S133 of FIG. 37, the number of sources is 2, so the result is NO, and the flow advances to step S135 to substitute the code of FIG. 38 for the source of S. To generate. When the process is executed by the code of FIG. 38, a value update request is set in the source srcsig + 0 of S0, and the resolution function execution and value update of S0 are performed in the resolution phase of the next simulation cycle.

FIG. 39 shows the execution code of the process P0 according to the conventional method when the present invention is not used.
In the case of FIG. 39, the signal structure src of the source of S0 is the same as in FIG. 38 even though the number of sources of S0 is one.
Since the substitution is performed on sig + 0, the resolution function of S0 is called in the resolution phase of the next simulation cycle, and assign_ine
The value of the second argument of rial will be set.
Therefore, calling a resolution function that returns the value of the argument itself is a simulation overhead.

As described above, according to the present embodiment, a resolution type signal having one source is detected, and a simulation code for which no resolution is performed for this signal is generated. By doing
The simulation can be performed at high speed.

<Modification 1 of Third Embodiment> In the third embodiment, FIG. 26 and FIG. 27 generated by the code generator 14 are described.
In the elaboration code of, the signal structure corresponding to the source is created even for the signal having one source. However, according to the present invention, these are not accessed at the time of simulation, so the code generation unit 14 It is also possible to output an optimized elaboration code that does not create the structure.

FIG. 40 and the subsequent FIG. 41 show such an optimized code. The code generation unit 14 refers to the table of FIG.
As the actual arguments of new_resinf and new_sigp, a code is generated which gives the number of signals having two or more sources registered in the table and the total number of sources of those signals. Further, as shown in the 46th line, the 55th line, and the 68th line, a signal having only one source registered in the table is excluded from the number of signal structures of the required source and a code is generated. To do.

As described above, the amount of memory required for simulation can be reduced by generating the optimized code.

<Modification 2 of Third Embodiment> In the third embodiment, the case of the compilation type simulator has been described, but the present invention is also applicable to an interpreter type simulator.

FIG. 42 shows the configuration of the logic simulator in this case. This logic simulator includes a hardware description storage unit 171, a data type storage unit 172, and an analysis unit 1.
73, a circuit data generation unit 174, a code generation unit 176,
A circuit data structure storage unit 175 and a code storage unit 177 are provided.

In FIG. 42, the hardware description storage unit 171, the data type storage unit 172, and the analysis unit 173 are
It is the same as the hardware description storage unit 111, the data type storage unit 112, and the analysis unit 113 in FIG. 22, respectively.

In the interpreter system, the circuit data generator 174 and the code generator 176 are the same as the code generator 1 of FIG.
Corresponds to 4. The circuit data generation unit 174
Generates a network data structure as shown in FIGS. 33, 34 and 36 and stores it in the circuit data structure storage unit 175. The code generation unit 176 generates only the execution code for the process as an instruction that can be interpreted by the simulator, and stores it in the code storage unit 177.

Here, the circuit data generation unit 174 refers to the table in the analysis unit 173 as shown in FIG. 23 and refers to the out or inout of the component instance statement.
When the connection destination signal of the port has the type of the data type storage unit 12 and the number of sources is 1, a data structure in which the resolution signal itself is connected to the port is generated instead of the source signal structure. . In addition, the code generation unit 176 uses the data type storage unit 17 whose source number is 1.
The assignment statement to the signal of the type 2 is converted into an instruction sequence to be assigned to the signal itself instead of the signal structure of the source. Then, the circuit data stored in the circuit data storage unit 175 and the instruction stored in the code storage unit 177 are loaded on the memory, and the instruction is sequentially executed.

As described above, also in the case of the interpreter type simulator, similarly, the resolution processing can be suppressed to the necessary minimum and the simulation speed can be increased. <Modification 3 of Third Embodiment> In the third embodiment and its modification, the code generation units 114 and 176 and the circuit data generation unit 174 decompose the vector signal for each scalar signal of the element, and It is determined for each resolution whether or not the resolution should be performed. However, a code that does not perform the resolution may be generated only when all the elements of the vector signal have one or less sources. .

(Fourth Embodiment) Next, a fourth embodiment will be described. <Main Configuration / Operation of Fourth Embodiment> The logic simulator according to the present embodiment includes a hardware description storage unit (181) for storing a specification description in a hardware description language and a hardware description storage unit (181). An analysis unit (183) that obtains the number of sources of signals in the stored description, a data type storage unit (182) that stores a data type for which resolution processing is omitted, and a data type storage unit (183). 182), a signal declaration of a signal of the data type stored in 182) and having a required number of sources is 1.
A hardware description conversion unit (18) that generates a hardware description replaced with a non-resolution type signal declaration.
4) is provided.

In this embodiment, the hardware description conversion unit (184) is a signal of the type stored in the data type storage unit (182) based on the analysis result by the analysis unit (183). A hardware description in which a signal having a source number of 1 is treated as a non-resolution type is generated.

<Effect> In the conventional simulator, the resolution processing is performed on all the resolution type signals even if there is only one source.

According to this embodiment, a signal of the resolution type having one source is detected, and the data type of the signal is changed to the non-resolution type by detecting the signal. , The resolution process can be omitted, and the simulation can be performed at high speed.

<Detailed Description> The case of a compilation simulator will be described below as an example.

FIG. 43 shows the configuration of the logic simulator of this embodiment. This logic simulator includes a first hardware description storage unit 181, a data type storage unit 182, an analysis unit 183, a hardware description conversion unit 184, a second hardware description storage unit 185, a code generation unit 186, and a code storage unit. 187 is provided.

The first hardware description storage section 1 in FIG. 43.
81, the data type storage unit 182, and the analysis unit 183 are the same as the hardware description storage unit 111, the data type storage unit 112, and the analysis unit 113 of the third embodiment (FIG. 22), respectively.

The hardware description conversion unit 184 determines whether the signal described in the hardware description storage unit 181 is the resolution type stored in the data type storage unit 182 and the number of sources by the analysis unit 183. For a signal whose analysis result is one or less, its data type is replaced with a signal declaration that is a non-resolution type that is the base type of the resolution type. If necessary, the signal before the change and the part referencing the signal are converted into a description in which the new signal name is replaced, and the result is converted into the second hardware description storage unit 185.
To memorize.

The code generation unit 186 generates a code for elaborating the VHDL description and a code for executing the statement as a C program corresponding to the VHDL description stored in the second hardware description storage unit 185. The code is stored in the code storage unit 187.

Hereinafter, the first hardware description storage unit 18
The VHDL description of FIG. 48 is stored in FIG. 1 and the data type storage unit 182 stores the std_logic type as an example.

The analyzing unit 183, as in the third embodiment,
The table of FIG. 23 is generated.

The hardware description conversion unit 184 converts the signal declaration of the VHDL description of FIG. 48 and the reference of the signal as described above.

FIG. 44 shows a processing flow of the conversion unit 184 for one signal declaration.

The hardware description converter 184 applies the above processing flow to all signal declarations. For example, for the signal S0 in FIG. 48, step S191,
The process proceeds to S192, S193, S194, and step S19
23, since the result is YES with reference to the table of FIG. 23, the process proceeds to step S195, and the data type std_logic of S0 is set to the base type std_ul.
Declaration changed to logic signal S0: st
d_ulotic; is output.

Next, the vector signal S1 is decomposed into each scalar element and processed in the loop of steps S196 to S1914. First, S1
For (0), its data type is std_log
Since it is ic, YES is obtained in step S198, and a new name is generated in step S199.
For example, the signal name and the element number are combined via “_”, and S1
_0. In step S1910, S1 (0)
Since the number of sources is 2, the steps S1912 and S1
Proceed to 913 and declare si without changing the data type.
gnal S1_0: std_logic; is output.

In step S1914, the old and new signal names are registered as shown in FIG. 45 for conversion of a later statement.

On the other hand, for S1 (1), step S
Although the process proceeds to 198 and S199, since YES is determined in step S1910, the data type of the signal is changed to std_logic in step S1911.
In step S1913, the declaration signal S
1_1: outputs std_logic ;.

Also, in step S1914, the old and new signal names are registered as shown in FIG. The statement part is converted by replacing the signal reference name with reference to the correspondence table of FIG. For example, in the component instance statement B0, the reference S1 (0) is replaced with S1_0, and in the component instance statement B1,
The references S1 (0) and S1 (1) are respectively referred to as S1_0 and S1_0.
Replace with 1_1.

As a result, the VHDL description shown in FIG. 46 is stored in the second hardware description storage section 185.

As described above, in the present embodiment, the signal of the resolution type stored in the data type storage unit 182 and having the number of sources of 1 or less is converted into the signal of the non-resolution data type by the VHDL. Convert it at the description level in advance and input it to the simulator.

As a result, similarly to the third embodiment, the resolution process can be suppressed to the necessary minimum and the simulation speed can be increased.

<Modification 1 of Fourth Embodiment> In the fourth embodiment, the case of the compilation type simulator has been described, but the present invention is also applicable to the interpreter type simulator.

FIG. 47 shows the configuration of the logic simulator in this case. This logic simulator includes a first hardware description storage unit 221, a data type storage unit 222, an analysis unit 223, a hardware description conversion unit 224, a second hardware description storage unit 225, a circuit data generation unit 226,
The circuit data storage unit 227, the code generation unit 228, and the code storage unit 229 are provided.

In FIG. 47, the first hardware description storage unit 221, the data type storage unit 222, the analysis unit 22.
3, the hardware description conversion unit 224, and the second hardware description storage unit 225 are respectively the first hardware description storage unit 181, the data type storage unit 182, and the first hardware description storage unit 182 of FIG.
It is the same as the analysis unit 183, the hardware description conversion unit 184, and the second hardware description storage unit 185.

The circuit data generating section 226 is shown in FIGS.
4, a network data structure as shown in FIG. 36 is generated and stored in the circuit data structure storage unit 227.

The code generation section 228 generates only the execution code for the process as an instruction that can be interpreted by the simulator, and stores it in the code storage section 229.

As described above, also in the case of the interpreter type simulator, similarly, the resolution processing can be suppressed to the necessary minimum and the simulation speed can be increased.

<Modification 2 of Fourth Embodiment> In the fourth embodiment and its first modification, the hardware description converters 184 and 2 are used.
In 24, the vector signal of the resolution data type stored in the data type storage units 182 and 222 was converted into the signal for each scalar element. However, if all the elements of the signal are to be converted, all When a signal element is not a conversion target, it may be left as it is as a vector signal and the vector data type may be converted to a non-resolution type only in the former case.

For example, signal T: std_lo
gic_vector (1to8);
T: std_logic_vector (1to
8);

Further, the hardware description conversion units 184, 2
The vector signal 24 may be converted into the non-resolution type only when all the elements of the signal are to be converted.

The present invention is not limited to the above-mentioned embodiments, but can be carried out in various modified forms without departing from the scope of the invention.

[0195]

【The invention's effect】

(1) According to the present invention, by referring to the type set by the designer or the type automatically determined for the object such as the signal or process of the simulation model during the simulation, the process during the simulation can be classified. It is possible to make the optimum one according to the above without waste. As a result, the simulation can be executed at high speed.

(2) According to the present invention, for a signal of resolution data type having a resolution function that returns the value of the source when there is one source,
When the signal has only one source, the resolution process for the signal can be omitted, and the simulation speed can be increased.

Further, it is possible to reduce the storage area of the data structure required for resolution.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a logic simulator according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a property of a signal for determining a signal type.

FIG. 3 is a diagram showing an example of a simulation model.

FIG. 4 is a diagram showing an example of signal types.

FIG. 5 is a diagram showing another example of signal types.

FIG. 6 is a flowchart showing an example of a signal substitution processing algorithm based on a signal type.

FIG. 7 is a flowchart showing an example of a signal substitution processing algorithm based on a signal type.

FIG. 8 is a diagram showing another example of a signal substitution processing algorithm based on a signal type.

FIG. 9 is a diagram showing an example of a simulation model.

FIG. 10 is a diagram showing an example of a property for determining a process type.

FIG. 11 is a diagram showing an example of process types.

FIG. 12 is a diagram showing a configuration of a logic simulator according to a second embodiment of the present invention.

FIG. 13 is a flowchart showing an example of a signal type determination algorithm.

FIG. 14 is a flowchart showing another example of a signal type determination algorithm.

FIG. 15 is a diagram showing an example of a simulation model.

FIG. 16 is a diagram showing an example of a simulation model.

FIG. 17 is a diagram showing an example of a simulation model.

FIG. 18 is a diagram showing an example of a simulation model.

FIG. 19 is a diagram showing an example of a simulation model.

FIG. 20 is a diagram showing an example of a simulation model.

FIG. 21 is a diagram showing an example of a simulation model.

FIG. 22 is a diagram showing a configuration of a logic simulator according to a third embodiment of the present invention.

FIG. 23 is a diagram showing an example of a table of an analysis unit.

FIG. 24 is a flowchart showing the processing flow of the analysis unit.

FIG. 25 is a flowchart showing the flow of table registration processing of the analysis unit.

FIG. 26 is a diagram showing an example of an elaboration code generated by a code generation unit.

FIG. 27 is a diagram showing an example of an elaboration code generated by a code generation unit.

FIG. 28 is a diagram showing an example of an execution code generated by a code generation unit.

FIG. 29 is a diagram showing an example of information included in a process structure.

FIG. 30 is a diagram showing an example of information included in a port structure.

FIG. 31 is a diagram showing an example of information included in a signal structure.

FIG. 32 is a diagram showing an example of information included in each structure of resolution.

FIG. 33 is a diagram showing a link between a resolution signal and its source.

FIG. 34 is a diagram showing a relationship between a process and a signal.

FIG. 35 is a flowchart showing the flow of actual argument generation processing of a function for expanding a lower component.

FIG. 36 is an expansion function bind_b of a lower component
The figure which shows an example of the data structure produced | generated by the call of uft.

FIG. 37 is a flowchart showing the flow of code generation processing of a signal assignment statement for a scalar element in the code generation unit.

FIG. 38 is a diagram showing an example of process execution code generated by a code generation unit.

FIG. 39 is a diagram showing an example of the execution code of the process P0 according to the conventional method.

FIG. 40 is a diagram showing an example of an optimized elaboration code.

FIG. 41 is a diagram showing an example of an optimized elaboration code.

FIG. 42 is a diagram showing an example of a configuration when the present invention is applied to an interpreter type simulator.

FIG. 43 is a diagram showing a configuration of a logic simulator according to a fourth embodiment of the present invention.

FIG. 44 is a flowchart showing a processing flow of a conversion unit for a signal declaration.

FIG. 45 is a diagram showing an example of a correspondence table in signal name conversion.

FIG. 46 is a diagram showing an example of a VHDL description generated by a code generation unit and output to a code storage unit.

FIG. 47 is a diagram showing an example of a configuration when the present invention is applied to an interpreter type simulator.

FIG. 48 is a diagram showing an example of a VHDL description.

FIG. 49 is a diagram showing an example of a resolution function of resolution data type std_logic in the description of FIG. 48.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Object storage part, 2 ... Simulation processing part, 20 ... Signal substitution execution part, 21 ... Process execution part, 3
... Object type storage unit, 30 ... Signal storage unit, 31 ...
Process storage unit, 4 ... Description storage unit, 5 ... Object type determination unit, 6 ... Feature extraction unit, 7 ... Feature storage unit, 8 ... Object type determination unit 111 ... Hardware description storage unit, 112 ... Data type storage unit, 113 ... Analysis unit, 114 ... Code generation unit, 1
15 ... Code storage unit, 171 ... Hardware description storage unit, 172 ... Data type storage unit, 173 ... Analysis unit, 1
74 ... Circuit data generation unit, 175 ... Circuit data structure storage unit, 176 ... Code generation unit, 177 ... Code storage unit, 1
81 ... First hardware description storage unit, 182 ... Data type storage unit, 183 ... Analysis unit, 184 ... Hardware description conversion unit, 185 ... Second hardware description storage unit,
186 ... Code generation unit, 187 ... Code storage unit, 221
... first hardware description storage unit, 222 ... data type storage unit, 223 ... analysis unit, 224 ... hardware description conversion unit, 225 ... second hardware description storage unit, 22
6 ... Circuit data generation unit, 227 ... Circuit data storage unit, 2
28 ... Code generation unit, 229 ... Code storage unit

Claims (8)

[Claims] 1. An object type storage unit for storing, for at least one type of object, a correspondence between each element belonging to the object and an object type obtained by classifying the object according to its property, and when executing an element of the object. , A simulation processing means for obtaining the object type of the element of the object to be executed with reference to the object type storage means, and processing the element of the object in accordance with a processing procedure defined for each object type. And a logic simulator. 2. An object type determining means for determining an element type of the object stored in the object type storing means and an object type corresponding to the element of the object based on a hardware description to be simulated. The logic simulator according to claim 1, wherein: 3. An analysis means for obtaining the number of sources of signals used in a hardware description to be simulated, a data type storage means for storing a data type for which resolution processing is omitted, and the hardware. For the signal substitution statement for the signal of the data type stored in the data type storage means in the hardware description and the number of sources obtained by the analysis means is one, the resolution signal itself is used. A logic simulator comprising: a code generation unit that generates a code to be directly substituted. 4. An analysis means for obtaining the number of sources of signals used in a hardware description to be simulated, a data type storage means for storing a data type for which resolution processing is omitted, and the hardware. The data type stored in the data type storage means in the hardware description, the number of sources obtained by the analysis means is one, and the output port or input / output of the lower component connected to the source A logic simulator comprising a code generating means for generating a code for directly connecting the port to the resolution signal itself when the port exists. 5. A hardware description storage means for storing a specification description in a hardware description language, an analysis means for obtaining the number of sources of signals in the hardware description stored in the hardware description storage means, and a resolution. Data type storage means for storing the data type for which the processing is omitted, and the number of sources obtained by the analysis means, which is a signal of the data type stored in the data type storage means in the hardware description. And a hardware description conversion means for generating a hardware description in which a signal declaration of which the number is one is replaced with a signal declaration of a non-resolution type. 6. The hardware according to claim 5, wherein a resolution type signal declaration is replaced with a non-resolution type signal declaration based on a signal assignment statement in the hardware description language. Description converter. 7. The hardware according to claim 5, wherein a resolution type signal declaration is replaced with a non-resolution type signal declaration based on a component instance statement in the hardware description language. Description converter. 8. A signal declaration of resolution type is replaced with a signal declaration of non-resolution type based on a signal assignment statement and a component instance statement in the hardware description language.
The hardware description conversion device described in 1.