JPH08255151A - Parallel computer and storing method for matrix - Google Patents

Abstract

PURPOSE: To provide parallel computers which can execute matrix calculation of small granularity at a calculation speed equal to that of a supercomputer and at low cost. CONSTITUTION: The parallel computers which calculates ligen values of a matrix and are provided with memory units 1a-1m and floating point computing elements 2a-2m as many as each other are equipped with a data transmission line which connects the memory units 1a-1m and floating point computing elements 2a-2m that are previously made to correspond to each other, a cross point switch 3 which connects the memory units 1a-1m and floating point computing elements 2a-2m in pairs according to an externally inputted control signal, and a controller 5 which generates the control signal for driving this cross point switch 3 from respective element values of the matrix through specific calculation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer for executing eigenvalue calculation of a matrix by using, for example, the Jacobi method, and a matrix storage method suitable for application to the parallel computer. The present invention relates to a parallel computer capable of realizing execution at high speed and at low cost, and a matrix storage method suitable for application to this parallel computer.

[0002]

2. Description of the Related Art Calculation of eigenvalues of a matrix is required in various fields such as computational material science and fluid analysis. The Jacobian method is one of the solutions. The Jacobian method is described in detail in, for example, “Toyama Hayato, Matrix Numerical Calculation”. Since the Jacobi method is accurate and has a large amount of half-plane calculation,
It is difficult to solve a large dimensional matrix by the Jacobi method,
Even when solving it, it was necessary to use a high-speed computer such as a super computer.

[0003]

The supercomputer is not in an environment that anyone can use, and the cost of using it is high. Also, since it is used by multiple people, the response time is longer than the actual calculation time. Since the Jacobian method has parallelism, it is possible to improve the processing speed by parallel computing with a parallel computer. However, in a general parallel computer, there is a problem that the performance is obtained when the granularity is large, but the performance is not obtained in the parallel computing having the small granularity like the Jacobian method. .

The present invention has been made in view of the above circumstances, and makes it possible to execute matrix calculations with a small granularity such as the Jacobian method at a calculation speed comparable to that of a super computer and at a low cost. An object of the present invention is to provide a parallel computer and a suitable matrix storage method applied to this parallel computer.

[0005]

The parallel computer of the present invention is
A parallel computer for calculating eigenvalues of a matrix, in which the same number of memory units and floating-point arithmetic units are provided, a data transmission line connecting the previously associated memory units and floating-point arithmetic units When,
A cross point switch for connecting the memory unit and the floating point arithmetic unit in a pair according to a control signal input from the outside, and a control signal for driving and controlling the cross point switch are calculated from each element value of the matrix in a predetermined manner. And means for generating by.

Further, the parallel computer of the present invention comprises n boards having m memory units each having a data input / output width of W bit width and a floating point arithmetic unit having a data input / output width of W bit width. When n boards with m mounted boards are connected with n Wm × Wm crosspoint switches with a data input / output width of 1 bit, all crosspoint switches have a W / n bit width of nm × nm Each of the crosspoint switches is connected to each of the memory unit and the floating point arithmetic unit by W / n bit width so as to be a crosspoint switch.

The matrix storage method of the present invention is a parallel computer for calculating the eigenvalues of a matrix, and in a parallel computer provided with m memory units and floating point arithmetic units, an n × n matrix When i + j <n + 2 is satisfied when the element at the i-th row and the j-th column of the upper triangular portion of the matrix when performing the eigenvalue calculation is satisfied, i + j <n + 2 is satisfied. When stored in a memory unit and i + j> n + 1 holds, the element is stored in the (i + jn) mod mth memory.

[0008]

The matrix calculation using the Jacobian method consists of the following two procedures. It is assumed that the matrix elements are divided and stored in advance in a plurality of memory units. First,
Procedure 1 will be described.

(Procedure 1) A memory controller provided in each memory unit and controlling the memory unit sequentially reads out matrix elements in the memory unit and associates them in advance with a floating point arithmetic unit (floating point in the embodiment). Arithmetic unit A
(Corresponding to). The floating-point arithmetic unit obtains the maximum element among the transmitted matrix elements, and the row number and column number of the element. The maximum value obtained by each floating point arithmetic unit is sent to the control unit (corresponding to the floating point arithmetic unit B and the controller of the embodiment) that controls the entire apparatus, and the control unit determines the maximum element value in the unit. And its line number,
Get the column number. Then, calculation is performed using the obtained maximum element value, and the result is transmitted to each floating point arithmetic unit.

Next, the procedure 2 will be described. (Procedure 2) The connection form of the memory unit and the floating point arithmetic unit by the cross point switch is determined according to the row number and column number of the maximum element obtained in (Procedure 1). Further, the memory controller sequentially reads the data of the matrix element from the memory unit according to the row number and the column number of the maximum element obtained in (procedure 1). Then, these element data are sent to the floating point arithmetic unit previously associated with the memory unit and the floating point arithmetic unit connected via the cross point switch.

On the other hand, in the floating point arithmetic unit, the sum of products operation is performed using the element input via the switch and the data directly input, and the result is sent again to the memory unit through the network. The memory controller stores the data sent from the switch in a predetermined position. In other words, this makes it possible to realize matrix calculation with small granularity at high speed and at low cost.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a parallel computer according to the present invention. As shown in FIG. 1, the parallel computer according to the present invention includes a plurality of memory units 1a to 1m, a plurality of floating point arithmetic units A2a to 2m, an m × m crosspoint switch 3, and a floating point arithmetic B4. , And has a controller 5 for controlling all of them. Each memory unit 1
Matrix elements are stored in a to 1m. The input / output of data of this memory unit is controlled by the memory controller. The cross point switch 3 connects the memory units 1a to 1m and the floating point arithmetic units A2a to 2m in a one-to-one manner. The crosspoint switch 3 has a connection configuration controlled by a controller 6 via a switch controller.

The floating-point arithmetic units A2a to 2m perform a floating-point multiply-accumulate operation and search for data having the maximum value in the input data string. In addition, the floating point arithmetic unit A2a
Each of .about.2 m is provided with a data transmission path between it and a predetermined memory unit, and is also connected to the cross point switch 3. Further, each of the floating point arithmetic units A2a to 2m is connected to the controller 5 via the bus 6.

The floating point calculator B4 performs addition, subtraction, multiplication and division of floating point and calculation of tan ^-1 . Further, the controller 5 controls the entire device. First, the first embodiment will be described.

In the embodiment, first, from among the matrix elements divided and stored in a plurality of memory units 1a to 1m,
The maximum element is obtained by the floating point arithmetic units A2a to 2m and the controller 5. The calculation using the maximum value is performed by the floating point arithmetic unit B4, and the result is sent to each of the floating point arithmetic units A2a to 2m.

Next, the elements of the matrix stored in the memory units 1a to 1m are sent to the floating point arithmetic units A2a to 2m via the cross point switch 3 and calculated by the floating point arithmetic unit B4. Calculations are performed between and. The calculation result is stored in the memory units 1a to 1m via the cross point switch 3.

FIG. 2 shows an algorithm for calculating the eigenvalue of a matrix using the Jacobian method. Here, as an example, a 5 × 5 matrix as shown in FIG. 3 is used, and elements are a [0,
0], a [0, 1], ..., a [0, 4], a [1,
0], a [1,1], ..., a [4,3], a [4,4]
And In addition, the memory unit and the floating point arithmetic unit A
Is 10 and the cross point switch is 10 × 10.

Then, each element of the matrix is distributed and stored in the memory unit. For example, as shown in FIG. 4, (1) memory unit (0) a [0,0], a [1,4], a [2,3], a [3,2], a [4,1 ] (2) Memory unit (1) a [0,1], a [1,0], a [2,4], a [3,3], a [4,2] (3) Memory unit (2 ) A [0,2], a [1,1], a [2,0], a [3,4], a [4,3] (4) Memory unit (3) a [0,3], a [1,2], a [2,1], a [3,0], a [4,4] (4) Memory unit (4) a [0,4], a [1,3], a It is stored as [2,2], a [3,1], a [4,0].

By storing in this way, it is possible to prevent access from concentrating on any of the memory units. First,
In this embodiment, the process of obtaining the maximum value of the matrix element is performed (step A1 in FIG. 2). The controller 5 has memory units 1a to 1 for all memory controllers.
All the matrix elements stored in m are read out, and instructions are sent to the corresponding floating point arithmetic units A2a to 2m. On the other hand, in the floating point arithmetic units A2a to 2m, the element having the maximum absolute value in each of the memory units 1a to 1m is obtained. Then, the controller 5 collects the elements having the maximum absolute values from the respective floating point arithmetic units A2a to 2m, and obtains the element having the largest absolute value among them. Here, this is a [I, J]. Then, suppose that a [1,2] is now the maximum.

Next, the controller 5 uses the a [1,
2] is compared with a predetermined value of e (step A2 in FIG. 2), and if a [1,2] is smaller than e, the process ends (Y in step A2 in FIG. 2).

Then, when a [1,2] is not smaller than e (N in step A2 of FIG. 2), the following processing is continued. First, from the memory unit, a [I, I], a
[J, J] is read out to the controller 5, and the controller 5 uses the a [I, I] and a [J, J] to the
ta is calculated, and s and c are calculated (step A3 in FIG. 2). The s and c are sent to the floating point arithmetic units A2a to 2m via the bus 6. Then, the controller 5 sends I and J to each memory controller and switch controller.

In the m × m cross point switch 3,
The input / output terminal l on the side of the memory units 1a to 1m and the input / output terminal 1 on the side of the floating point arithmetic units A2a to 2m (l- | I-J
|) Mod m is connected (step A4 in FIG. 2).
That is, when I = 1 and J = 2, the switch controller determines that the memory units (0), (1), (2), (3),
(4) is a floating point arithmetic unit A (4), (0),
Settings are made so that they are connected to (1), (2), and (3), respectively.

Next, each memory controller obtains an element to be read from I and J. As a result, data transmission as shown in FIG. 5 is performed. (1) Memory unit (0) a [4,1] → floating point arithmetic unit A (0): via data transmission line a [3,2] → floating point arithmetic unit A (4): via crosspoint switch (2) ) Memory unit (1) a [0,1] → floating point arithmetic unit A (1): via data transmission line a [4,2] → floating point arithmetic unit A (0): via crosspoint switch (3) memory Unit (2) a [1,1] → floating point arithmetic unit A (2): via data transmission line a [0,2] → floating point arithmetic unit A (1): via crosspoint switch (4) Memory unit ( 3) a [2,1] → floating point arithmetic unit A (3): via data transmission line a [1,2] → floating point arithmetic unit A (2): via crosspoint switch (5) memory unit (4) a [3,1] → floating-point arithmetic unit A (4): Via data transmission line a [2,2] → floating-point arithmetic unit A (3): via crosspoint switch Then, the floating-point arithmetic unit which receives these elements, from these elements and s and c, respectively, Calculation is performed (step A5 in FIG. 2). (1) Floating point arithmetic unit A (0) a [4,1] = c * a [4,1] + s * a [4,2] a [4,2] =-s * a [4,1] + C × a [4,2] Of the calculated results, a [4,1] is written back to the memory unit (0), and a [4,2] is written back to the memory unit (1) via the switch. Be done. (2) Floating point arithmetic unit A (1) a [0,1] = c * a [0,1] + s * a [0,2] a [0,2] =-s * a [0,1] + C × a [0,2] Of the calculated results, a [0,1] is written back to the memory unit (1), and a [0,2] is written back to the memory unit (2) via the switch. Be done. (3) Floating point arithmetic unit A (2) a [1,1] = c × a [1,1] + s × a [1,2] a [1,2] = − s × a [1,1] + C × a [1,2] Of the calculated results, a [1,1] is written back to the memory unit (2), and a [1,2] is written back to the memory unit (3) via the switch. Be done. (4) Floating point arithmetic unit A (3) a [2,1] = c * a [2,1] + s * a [2,2] a [2,2] =-s * a [2,1] + C × a [2,2] Of the calculated results, a [2,1] is written back to the memory unit (3), and a [2,2] is written back to the memory unit (4) via a switch. Be done. (5) Floating point arithmetic unit A (4) a [3,1] = c * a [3,1] + s * a [3,2] a [3,2] =-s * a [3,1] + C × a [3,2] Of the calculated results, a [3,1] is written back to the memory unit (4), and a [3,2] is written back to the memory unit (0) via the switch. Be done.

Next, the following processing is performed with the connection pattern of the cross point switch 3 unchanged (step A6 in FIG. 2). That is, each memory controller obtains an element to be read from I and J. As a result, the following data transmission is performed. (1) Memory unit (0) a [1,4] → floating point arithmetic unit A (0): via data transmission path a [2,3] → floating point arithmetic unit A (4): via crosspoint switch (2) ) Memory unit (1) a [1,0] → floating point arithmetic unit A (1): via data transmission line a [2,4] → floating point arithmetic unit A (0): via crosspoint switch (3) memory Unit (2) a [1,1] → floating point arithmetic unit A (2): via data transmission line a [2,0] → floating point arithmetic unit A (1): via crosspoint switch (4) Memory unit ( 3) a [1,2] → floating point arithmetic unit A (3): via data transmission line a [2,1] → floating point arithmetic unit A (2): via crosspoint switch (5) memory unit (4) a [1,3] → floating point arithmetic unit A (4): Via data transmission line a [2,2] → floating-point arithmetic unit A (3): via crosspoint switch Then, the floating-point arithmetic unit which receives these elements, from these elements and s and c, respectively, Calculate. (1) Floating point arithmetic unit A (0) a [1,4] = c × a [1,4] + s × a [2,4] a [2,4] = − s × a [1,4] + C × a [2,4] Of the calculated results, a [1,4] is written back to the memory unit (0), and a [2,4] is written back to the memory unit (1) via the switch. Be done. (2) Floating point arithmetic unit A (1) a [1,0] = c × a [1,0] + s × a [2,0] a [2,0] = − s × a [1,0] + C × a [2,0] Among the calculated results, a [1,0] is written back to the memory unit (1), and a [2,0] is written back to the memory unit (2) via the switch. Be done. (3) Floating point arithmetic unit A (2) a [1,1] = c × a [1,1] + s × a [2,1] a [2,1] = − s × a [1,1] + C × a [2,1] Of the calculated results, a [1,1] is written back to the memory unit (2), and a [2,1] is written back to the memory unit (3) via the switch. Be done. (4) Floating point arithmetic unit A (3) a [1,2] = c × a [1,2] + s × a [2,2] a [2,2] = − s × a [1,2] + C × a [2,2] Of the calculated results, a [1,2] is written back to the memory unit (3), and a [2,2] is written back to the memory unit (4) via the switch. Be done. (5) Floating point arithmetic unit A (4) a [1,3] = c × a [1,3] + s × a [2,3] a [2,3] = − s × a [1,3] + C × a [2,3] Among the calculated results, a [1,3] is written back to the memory unit (4), and a [2,3] is written back to the memory unit (0) via the switch. Be done.

When the above processing is completed, the processing is repeated from the beginning. This makes it possible to execute matrix calculation with a small granularity at high speed and at low cost.

Next, a second embodiment of the present invention will be described. Here, consider a case where m memory units of 8-bit width and m floating-point arithmetic units of 8-bit width are connected by an m × m crosspoint switch of 8-bit width.

For example, a memory board on which four 8-bit width memory units are mounted, a floating-point arithmetic unit board on which four 8-bit width floating-point arithmetic units are mounted, and a 32 × 32 1-bit width unit Assuming that there are one cross point switch board and one cross point switch board, as shown in FIG.
Connect each board as a cross point switch.
A connection substrate or a connector may be used for the connection between the substrates.

If there are two memory boards, two floating-point arithmetic unit boards, and two cross-point switch boards, as shown in FIG.
Each of the crosspoint switches is used as an 8x8 crosspoint switch with a 4-bit width, and the 8 bits of the input / output of the memory unit or the floating point arithmetic unit are divided into 4 bits, and each of them is a separate crosspoint. Connect to the switch board.

This eliminates the need for wiring between the crosspoint switch boards and facilitates hardware expansion. Next, a third embodiment of the present invention will be described.

In the Jacobian method, in order to handle a symmetric matrix, when handling an n × n matrix, it is sufficient to hold only the upper triangular matrix as shown in FIG. At this time, the number of elements for each memory unit becomes substantially equal by adopting the following matrix storage method, and the elements used in the calculation are not concentrated in a specific memory unit.

Here, a 5 × 5 matrix is used, and the element is a
[0,0], a [0,1], ..., a [0,4], a
[1,0], a [1,1], ..., a [3,4], a
[4, 4]. Further, the number of memory units and floating-point arithmetic units of the parallel computer according to the embodiment is 5, and the number of switches is 5 × 5.

First, each element of the matrix is distributed and stored in the memory unit. Since we only need to store the upper triangular matrix,
As shown in FIG. 9, (1) memory unit (0) a [0,0], a [1,4], a [2,3] (2) memory unit (1) a [0,1], a [2,4], a [3,3] (3) Memory unit (2) a [0,2], a [1,1], a [3,4] (4) Memory unit (3) a [0,3], a [1,2], a [4,4] (5) Memory unit (4) a [0,4], a [1,3], a [2,2] Store. By storing in this way, it is possible to prevent access from being concentrated on the same memory unit.

This storage method will be described with reference to FIG. Here, for an n × n matrix, each element is represented by i rows and j columns (i and j are 0 to n).

First, i in row i and column j is set to 0 (step B1 in FIG. 10). Then, j at i-th row and j-th column is set to i (step B2 in FIG. 10). That is, initially, the element in the 0th row and 0th column becomes the element to be stored.

Next, it is judged whether or not i + j <n + 2 is satisfied (step B3 in FIG. 10). If it is satisfied (Y in step B3 in FIG. 10), this element is (i + j).
The data is stored in the mod mth memory unit (step B4 in FIG. 10). On the other hand, if it does not hold (Fig. 10
Step B3 N), this element is (i + j−n) m
The data is stored in the memory unit number od m (step B5 in FIG. 10).

Here, the value of j is counted up (see FIG. 1).
0, step B6), and as a result, if j does not reach n (N in step B7 in FIG. 10), step B3 is executed again.
Repeat the process from. On the other hand, when j reaches n (Y in step B7 of FIG. 10), i is counted up this time (step B8 of FIG. 10).

As a result, if n is not reached (see FIG.
Step B9 N), the processing from step B2 is repeated again, and when i reaches n (Y of step B9 in FIG. 10), this processing ends.

As a result, only the upper triangular matrix of the matrix elements can be efficiently dispersed and stored in each memory unit. Next, the processing of the parallel computer when this storage method is applied will be described with reference to FIG.

First, in this embodiment, the process of obtaining the maximum value of the matrix element is performed (step C1 in FIG. 11). This processing is performed according to the procedure described in the first embodiment. Now a
If [1,2] is calculated, the controller 5
This a [1,2] is compared with a predetermined value of e (step C2 in FIG. 11), and if a [1,2] is smaller than e, the process ends (Y in step A2 in FIG. 2). ).

First, from the memory unit, a [I, I],
a [J, J] is read out to the controller 5, and the controller 5 calculates th from this a [I, I] and a [J, J].
eta is calculated, and s and c are further calculated (step C3 in FIG. 11). The s and c are sent to the floating point arithmetic units A2a to 2m via the bus 6. Then, the controller 5 sends I and J to each memory controller and switch controller.

Here, the controller 5 uses aa [I,
I] = a [I, I] * c * c + 2 * a [I, J] * s *
c + a [J, J] * s * s and aa [J, J] = a
[I, I] * s * s-2 * a [I, J] * s * c + a
[J, J] * c * c are calculated and aa [I, J] = 0 is set (step C4 in FIG. 11).

In the m × m cross point switch 3,
The input / output terminal l on the side of the memory units 1a to 1m and the input / output terminal (l- | i-j on the side of the floating point arithmetic units A2a to 2m)
|) Mod m is connected (step C in FIG. 11).
5). That is, when I = 1 and J = 2, the switch controller determines that the memory units (0), (1), (2),
(3) and (4) are floating point arithmetic units A (4),
Settings are made so that they are connected to (0), (1), (2), and (3), respectively.

Next, each memory controller obtains an element to be read from I and J. Here, when reading a [i, j], if i> j, a [j, i] is read. As a result, the following data transmission is performed. (1) Memory unit (0) a [1,4] → floating point arithmetic unit A (0): via data transmission path a [2,3] → floating point arithmetic unit A (4): via crosspoint switch (2) ) Memory unit (1) a [0,1] → floating point arithmetic unit A (1): via data transmission line a [2,4] → floating point arithmetic unit A (0): via crosspoint switch (3) memory Unit (2) a [1,1] → floating point arithmetic unit A (2): via data transmission line a [0,2] → floating point arithmetic unit A (1): via crosspoint switch (4) Memory unit ( 3) a [1,2] → floating point arithmetic unit A (3): via data transmission line a [1,2] → floating point arithmetic unit A (2): via crosspoint switch (5) memory unit (4) a [1,3] → floating point arithmetic unit A (4): Via data transmission line a [2,2] → floating-point arithmetic unit A (3): via crosspoint switch Then, the floating-point arithmetic unit which receives these elements, from these elements and s and c, respectively, Calculation is performed (step C6 in FIG. 11). (1) Floating point arithmetic unit A (0) a [1,4] = c * a [1,4] + s * a [2,4] a [2,4] =-s * a [1,4] + C * a [2,4] Of the calculated results, a [1,4] is written back to the memory unit (0), and a [2,4] is written back to the memory unit (1) via the switch. Be done. (2) Floating point arithmetic unit A (1) a [0,1] = c * a [0,1] + s * a [0,2] a [0,2] =-s * a [0,1] + C * a [0,2] Of the calculated results, a [0,1] is written back to the memory unit (1), and a [0,2] is written back to the memory unit (2) via the switch. Be done. (3) Floating point arithmetic unit A (2) a [1,1] = c * a [1,1] + s * a [1,2] a [1,2] =-s * a [1,1] + C * a [1,2] Of the calculated results, a [1,1] is written back to the memory unit (2), and a [1,2] is written back to the memory unit (3) via the switch. Be done. (4) Floating point arithmetic unit A (3) a [1,2] = c * a [1,2] + s * a [2,2] a [2,2] =-s * a [1,2] + C * a [2,2] Of the calculated results, a [1,2] is written back to the memory unit (3), and a [2,2] is written back to the memory unit (4) via the switch. Be done. (5) Floating point arithmetic unit A (4) a [1,3] = c * a [1,3] + s * a [2,3] a [2,3] =-s * a [1,3] + C * a [2,3] Of the calculated results, a [1,3] is written back to the memory unit (4), and a [2,3] is written back to the memory unit (0) via the switch. Be done.

Then, aa [I, I], aa [I, J], aa [J, J] calculated by the controller 5
A [I, I], a [I, J], a [J, J] respectively
And write them back to the memory unit in which they are stored (step C7 in FIG. 11).

When the above process is completed, the process is repeated from the beginning. This makes it possible to execute matrix calculation with a small granularity at high speed and at low cost.

[0046]

As described in detail above, according to the parallel computer and the matrix storage method of the present invention, it is possible to realize matrix calculation with small granularity such as matrix eigenvalue calculation using the Jacobian method at high speed and at low cost. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a parallel computer according to the present invention.

FIG. 2 is a flowchart for explaining eigenvalue calculation of a matrix using the Jacobian method according to the first embodiment.

FIG. 3 is a conceptual diagram showing a matrix processed in the first embodiment.

FIG. 4 is a conceptual diagram showing storage of each matrix element in a memory unit in the first embodiment.

FIG. 5 is a conceptual diagram showing data transmission of each matrix element in the first embodiment.

FIG. 6 is a diagram showing an example in which one memory board, one switch board, and one floating-point arithmetic unit board are connected in the second embodiment.

FIG. 7 is a diagram showing an example in which two memory boards, two switch boards and two floating point arithmetic unit boards are connected in the second embodiment.

FIG. 8 is a conceptual diagram showing a matrix processed in the third embodiment.

FIG. 9 is a conceptual diagram showing storage of each matrix element in a memory unit in the third embodiment.

FIG. 10 is a flowchart illustrating a method of storing a matrix in the third embodiment.

FIG. 11 is a flowchart for explaining eigenvalue calculation of a matrix using the Jacobian method according to the third embodiment.

[Explanation of symbols]

1a to 1m ... Memory unit, 2a to 2m ... Floating point arithmetic unit A, 3 ... Crosspoint switch, 4 ... Floating point arithmetic unit B, 5 ... Controller, 6 ... Bus.

Front page continued (72) Inventor Tatsuo Shimizu 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Within the Corporate Research and Development Center, Toshiba Corporation (72) Hiroyuki Takano 1 Komukai-shiba-cho, Kawasaki-shi, Kanagawa Incorporated company Toshiba Research and Development Center

Claims (3)

[Claims] 1. A parallel computer for calculating eigenvalues of a matrix, wherein the same number of memory units and floating-point arithmetic units are provided, wherein the memory units and the floating-point arithmetic units previously associated with each other are provided. A data transmission line to be connected, a cross point switch for connecting the memory unit and the floating point arithmetic unit in a pair according to a control signal input from the outside, and a control signal for driving and controlling the cross point switch are provided in the matrix. A parallel computer comprising means for generating a predetermined calculation from each element value. 2. A substrate n on which m memory units having a data I / O width of W bit width are mounted and a substrate n on which m floating point arithmetic units having a data I / O width of W bit width are mounted. Wm whose data input / output width is 1 bit
X When connecting with n Wm crosspoint switches,
Connect each crosspoint switch to each of the above memory unit and floating point arithmetic unit by W / n bit width so that all of these crosspoint switches become nm × nm crosspoint switches with W / n bit width. The parallel computer according to claim 1, which is characterized in that. 3. A parallel computer for calculating an eigenvalue of a matrix, wherein the parallel computer is provided with m memory units and floating point arithmetic units, and the matrix of the n × n matrix is calculated when the eigenvalue calculation is performed. When i + j <n + 2 is satisfied when the element in the i-th row and the j-th column of the upper triangular portion is stored in any of the above memory units, the element is stored in the (i + j) mod mth memory unit, and i + j> n + 1. When the above is true, the element is stored in the (i + jn) mod mth memory, and the matrix storage method is characterized.