JPH08255083A - Processor device equipped with software downloading function - Google Patents

Abstract

PURPOSE: To reduce the hardware and lower the cost of the processor device equipped with the software downloading function. CONSTITUTION: This device includes a single CPU 11, 1st and 2nd memories 21 and 22 which store 1st software and 2nd software to be downloaded to the CPU 1, and a switching control unit 31 which selects the memory 21 or 22, and consists of a downloading circuit 30 which downloads the selected software to the CPU 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor device, and more particularly to a processor device having at least a central processing unit (hereinafter, CPU) and a memory for storing software (program) to be downloaded therein. In the processor device as described above, for example, in the main signal system and the control system constructing the electronic exchange system, which is the latter control system, in the processor device which constitutes the latter, the active memory and the standby memory are used as the above memory. When the software version changes, the software of the new version is stored in the memory of the standby system, and then downloaded to the main memory of the CPU as the memory of the active system.

[0002]

2. Description of the Related Art FIG. 13 is a diagram showing an outline of a conventional processor device. In the figure, reference numeral 10 is a processor device, and processor devices 10-1 and 10-2
Is duplicated. When the processor device 10-1 is the active system, the processor device 10-2 is the standby system. The processor device 10-1 includes a first CPU 11 and a first memory 21 (shown as a RAM) paired with the first CPU 11.
In addition, the processor device 10-2 also includes a second CPU 12 and a second memory 22 paired therewith.
(Shown as RAM). The peripheral unit group to be controlled by any one of the active CPUs (11, 12) is not directly related to the present invention, and therefore its description is omitted.

In the figure, if the CPU 11 is currently the active system, software to be downloaded to the main memory (not shown) in the CPU 11 is supplied from the first memory 21. The software to be stored in the first memory 21 is the CPU 11 and the data bus 1
3 via an external software source.
Similarly, software to be stored in the second memory 22 is also transferred from the above software source via the CPU 12 and the data bus 14.

Here, it is assumed that the software source provides a new version of software different from the existing software, and the processor device 10 is required to operate under the new version of the software. In order to meet this demand, assuming that the device that functions as the active system is the processor device 10-1, the device 10- that is the standby system device that does not perform normal processing
2 is started, and the new version of the software already stored in the second memory 22 is downloaded to the corresponding second CPU 12. After that, the active / standby system is switched, and this time, the CPU 12 starts the operation under the new version of the software. The software is usually downloaded at system startup or power-on after power-down.

[0005]

The above-described conventional processor device has the following problems. That is, since the processor device 10 is duplicated (10-1 and 10-
2) The hardware scale of the device becomes large and the cost becomes high. The present invention has been made in view of the above problems, and an object of the present invention is to provide a processor device that can be realized at a low cost with a reduced hardware scale of the device.

[0006]

FIG. 1 is a diagram showing an outline of a processor device according to the present invention. (1) According to the present invention, the processor device 10 of the present invention
Is a single CPU 11, a first memory 21 and a second memory 22 for storing the first software and the second software, respectively, and one of the first memory 21 and the second memory 22. It includes a switching control unit 31 that switches autonomously, and a download circuit 30 that downloads the software stored in the switched memory to the CPU 11.

Further, as will be made clear with reference to the drawings for explaining the embodiments later, the embodiment of the present invention is as follows. (2) The switching control unit 31 decodes the first selector and the second selector respectively corresponding to the first memory 21 and the second memory 22, the address signal and the chip select signal from the CPU 11, and outputs the decoded output. And a decoder that applies the same to both the first selector and the second selector, and the first selector and the second selector are configured to be selectively activated by a switching command from the CPU 11. .

(3) Further in the download circuit 30,
The management data includes a management control unit 32 that manages the switching control by the switching control unit 31, and is at least management data necessary for the management control by the management control unit 32.
A management memory 33 for backing up management data including information indicating which software (21, 22) stored in which memory (21, 22) up to immediately before was downloaded.
To be equipped with.

(4) The management control unit 32 and the management memory 33 are connected by a management data transfer line 34 to serially transfer the management data. (5) The management control unit 32 is configured to automatically rewrite the information in the management memory 33 at the same time as receiving the switching command from the CPU 11 for switching to one of the two memories (21, 22).

(6) When there is an abnormality in the transfer on the management data transfer line 34 in the management control unit 32,
It is configured to include a retry unit that restarts the write or read operation with respect to the management memory 33. (7) The management control unit 32 is provided with a protection means for stopping access to the management memory 33 when the management data itself transferred on the management data transfer line 34 is abnormal.

(8) Wait control means for waiting for writing new management data to the management memory 33 until a predetermined time elapses after the management data has been written to the management memory 33. Unit 3
It is configured so as to be provided in the No. 2.

[0012]

[Action]

(1) According to the basic mode of the above (1), the download circuit 30 is introduced, and the switching control unit 31 is provided in the download circuit 30, so that the conventional dual configuration is provided in the single CPU 11.
Can be made into a single configuration. (2) According to the above aspect (2), as long as the CPU 11 outputs the address signal, the chip select signal, and the switching command, the switching from the active memory to the standby memory is executed.

(3) According to the above aspect (3), the management control unit 32 is further introduced. With the introduction of the switching control unit 31, the memory switching completely depends on the hardware, and the CPU 11 itself is freed from the processing required for the memory switching.

In this case, the CPU 11 determines whether the switching processing is normal / normal.
If it is still involved in the management of abnormalities and normality / abnormality of transfer data, the effect of implementing the above switching control by hardware is diminished. Therefore, the management control unit 32 is introduced. In this case, the management control unit 32 uses the management memory 33.
Preferably in cooperation with. With the introduction of the management memory 33, especially the non-volatile management memory 33, the memory (21 or 22) used immediately before can be recorded (backed up) even after the power is turned off, and the system startup At the time of power-on, the CPU 11 does not need to care which memory (21 or 22) was used immediately before.

(4) According to the above aspect (4), an E ² PROM (Electric) suitable as the management memory 33 is provided.
all Erasable Programmable
Assuming the use of a ROM), a management data transfer line 34 is laid between the management memory 33 and the management control unit 32, and the two are connected by a serial interface function.

(5) According to the above aspect (5), the CPU
If there is a system switching command from 11 to the memory (21, 22), the management data is automatically backed up to the management memory 33. That is, assuming that the memory 22 was the active system until immediately before, immediately in response to the switching command, information indicating that the current memory 21 is the active system is recorded in the management memory 33.

(6) According to the above aspect (6), as one management aspect of the above-mentioned management control, when there is a write failure or a read failure in the exchange with the management memory 33 by the introduction of the retry means, The download circuit 30 autonomously performs the rewriting operation or the rereading operation. (7) According to the above aspect (7), as another aspect of the management control, by introducing a protection means, management data that cannot normally exist in the exchange with the management memory 33. Is checked, and when such management data appears, the data exchange with the management memory 33 is stopped.

(8) According to the above aspect (8), it is possible to guarantee that the management data is stably written in the management memory 33.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram schematically showing the manner of downloading according to the present invention. The upper column of this figure shows “case 1” of the download mode, and the lower column shows that “case 2”. In both columns, the left end is the main memory of the CPU 11 (M
M) represents the address area, the center is a download circuit 30 which is the main part of the present invention, and the right end is a first memory 21 and a second memory 22. The BYTE value indicating the capacity of each memory is the value used in the embodiment.

In the state of Case 1, the currently operating software is stored in the memory 22, and the memory 2
1 stores the old software that was previously operated or the new software that is newly downloaded.
Contrary to case 1, Case 2 stores software that is being operated in the memory 21, and memory 22 stores old software that was being operated before or new software that is newly downloaded.

For example, when operating the software in the state of Case 1 and operation of the upgraded new software is requested, the CPU 11 first stores the new software in the memory 21 of the standby system. After that, switching command is issued to the download circuit 30,
It is instructed to switch the access area to the memory as in case 2. As a result, the software stored in the memory 22 is switched from the active system to the standby system, the software stored in the memory 21 is switched from the standby system to the active system, and the software is downloaded to the CPU 11. It will be operated under the new software.

Contrary to the above case, when the operation in case 2 is switched to the operation in case 1, the same procedure as above is performed. FIG. 3 is a view showing a write (write) sequence to the management memory, and FIG. 4 is a view (No. 2) showing a write (write) sequence to the management memory. Further, FIG. 5 is a diagram showing a read (read) sequence to the management memory (No. 1), and FIG. 6 is a diagram showing a read (read) sequence to the management memory (No. 2).
Is. The management memory 33 (assumed to be an E ² PROM)
The access is shown by an example in which a known 4-byte page read / write method is adopted. The upper part of each figure shows the basic clock of the download circuit 30, and the lower part shows the management data transferred on the management data transfer line 34.

Referring first to FIGS. 3 and 4, the CPU
When a switching command is issued from 11, the download circuit 30 receiving this command outputs a start bit (START) indicating the start of access (write access) to the management memory 33. This bit falls to "L" at the central timing of the relevant clock. This is followed by a 7-bit word address and 1-bit read / write bit (R /
W) is output. This word address is, for example, all ″
It consists of 0 ″ and indicates the start address on the management memory 33. The read / write bit (R / W) in this case is
"L" indicating a light.

When the management memory 33 recognizes the read / write bit (R / W), it immediately acknowledges (AC).
K) is returned to the download circuit 30 side. AC at this time
K is "L". At this time, the data from the circuit 30 side is set to high impedance (HZ) so that the ACK (“L”) does not compete with the output data from the circuit 30 and disappear. is there. This AC
In response to K ("L"), the circuit 30 continuously transmits the 4-byte management data while confirming the return of ACK ("L": indicating successful reception) from the memory 33. These are sequentially written from the above head address.

Finally, when the circuit 30 receives the stop bit (STOP) from the memory 33, rewriting (backup) of the management data in the memory 33 based on the switching command is completed here. In the 4-byte page read / write method, E ² P
Although it is specified that four consecutive data (management data) are sent to the ROM (management memory 33), the sending method can be freely decided by the user, and the sending can be performed to confirm the normality of data transfer. You can also turn to For example,
If the data is represented by D, it may be sent as D1 → D2 → D1 → D2 or as D1 → D1 → D2 → D2. By sending the same data at least twice, it becomes extremely easy to confirm the identity of the data.

Referring to FIGS. 5 and 6, at the time of system start-up or power-on, the download times 30 are immediately backed up to the management data in the management memory 33 (E ² PROM). The software stored in the memory (21 or 22) is CP
(Including information indicating whether it was downloaded to U11)
Read out.

This read procedure (read sequence) is as shown in FIGS. 5 and 6, and the start bit (S
Start with TART) and end with a stop bit (STOP), and transfer 4-byte management data (D1 → D2)
→ D1 → D2 or D1 → D1 → D2 → D2) is the same as in the above write sequence.

However, in the read sequence, the read / write bit (R / W) becomes "H", and while the management data is being read from the memory 33, the download circuit 30 does not erase the read data. Further, keeping the line 34 in the high impedance (HZ) state is different from the case of the write sequence. FIG. 7 is a diagram showing a specific example of the switching control unit 31 shown in FIG. As shown in this figure, the switching control unit 31
Is a first selector 41 and a second selector 4 corresponding to the first memory 21 and the second memory 22, respectively.
2 and the address signal AD and the chip select signal CS from the CPU 11 are decoded and the decoded output Do
and a decoder 43 for commonly applying ut to the first selector 41 and the second selector 42, and the first selector 41 and the second selector 42 are selectively activated by a switching command SW from the CPU 11. . 44 is F
A switching setting unit made of F.

That is, when the CPU 11 outputs the address (AD), the chip select (CS) and the data on the data bus DB to the switching control unit 31, the unit 31 switches between the active system and the standby system. The distinction is made by decoding the address (AD) and the chip select (CS). For example, the address (AD) has 3 bits and the chip select (CS) has 1 bit.
A = "0" only when = "110" and CS = "0"
Further, B = “0” only when AD = “100” and CS = “0”.

The signals (A, B) thus distinguished are:
The switching command S set by the CPU 11 in the switching setting unit 44
Either the memory 21 or the two memories 22 is selected by W via the selectors 41 and 42 and applied to the corresponding memory. It should be noted that if the output of the switching setting unit 44 is "0", it corresponds to the above case 1, and A, B from the decoder 43
The output reaches the corresponding memory through the "0" input of each selector. If the output of the switch setting unit 44 is "1", it corresponds to the above case 2, and the A and B outputs from the decoder 43 reach the corresponding memory through the "1" input of each selector.

FIG. 8 is a schematic block diagram of the management control unit 32 shown in FIG. Of these, the transfer control means 50
Is a part that fulfills an original function of controlling the exchange of management data with the management memory 33.
Other means 60, 70 and 80 are means for further enhancing the functionality of the download circuit 30 of the present invention. That is, the retry means 60 restarts the write or read operation to the management memory 33 when the transfer on the management data transfer line 34 is abnormal, and the protection means 7
0 indicates that when the management data itself transferred on the management data transfer line 34 is abnormal, the access to the management memory 33 is stopped, and the wait means 80 terminates the writing of the management data to the management memory 33. The writing of new management data to the management memory 33 is kept on standby until a predetermined time has elapsed.

FIG. 9 is a diagram showing a specific example of the management control unit 32 shown in FIG. The operation will be described with reference to this figure. In FIG. 8, reference numerals 50, 60,
Circuit parts in FIG. 9 corresponding to the respective means denoted by 70 and 80 are designated by reference numerals in the 50s, 60s ... 80s, respectively. Also, means that do not belong directly to any of these means, or that are utilized by any of these means, are shown with reference numbers in the 90's.

When data is read from the management memory 33, for example, when the system is restarted, the management data is read from the management memory 33. The read management data is
It is immediately set in the management data setting section 91 in the management control unit 32. When the timing generation unit 52 recognizes the change of the power-on reset from L to H, it automatically starts the read time sequence operation. The timing generation unit 52 generates various timing signals necessary to define the time sequences shown in FIGS. 3 to 6, and can be configured by, for example, a combination of a counter and a plurality of FFs. .

The timing generator 52 includes a start / stop bit generator 53 (START and S in FIGS. 3 to 6).
Each BIT of TOP) is triggered to generate these bits (START, STOP) that are 1/2 phase-shifted with respect to the clock ("H") shown in FIGS. First, the start bit is generated and input to the parallel / serial conversion unit 54. The conversion unit 54 uses the 7-bit word address (al
l "0") and read / write bit (R / W = "H")
And are converted into serial data and transmitted. This transmission is performed through the former buffer 55 of the pair of bidirectional buffers 55 and 55 '. In addition, this buffer 55
Under the control of the bus control unit 56, the high impedance (HZ) shown in FIGS. 5 and 6 is also generated.

When the transmission of the start bit, the word address and the read / write bit is completed, the bus control unit 56 sets the buffer 55 to the high impedance (HZ) state, and is ready to receive the acknowledge (ACK) from the management memory 33. Since the management data from the management memory 33 following this acknowledge (ACK) is serially transferred, it is received in the buffer 55 ', converted into parallel data in the serial / parallel conversion unit 57, and then stored in the byte data holding unit 58. Entered and retained. Here, four management data in byte units shown in FIGS. 5 and 6 are held.

The acknowledge (ACK) returned from the management memory 33 is set to "L". If this ACK is "H", it is estimated that some sort of transfer abnormality (including noise) has occurred on the management data transfer line 34. The ACK = “H” is detected by the acknowledge “H” detection unit 61. The detection unit 61 resets the timing generation unit 52 to the initial state by the detection. Then, the generator 52 controls the start / stop bit generator 53 to immediately output the stop bit (STOP), and again outputs the start bit (START). The read operation is retried here.

On the other hand, when each management data is fetched into the byte data holding unit 58, the buffer 55 is put into the output state and the acknowledge (ACK = "L") generated by the parallel / serial conversion unit 54. Management memory 33
Output to. The above-described 8-bit management data fetch and acknowledge (“L”) output are repeated, and finally the start / stop bit generator 53 outputs a stop bit (STOP) to end the access to the management memory 33. To do.

By the way, the above byte data holding unit 58
If the management data itself held in is abnormal, the download circuit 30 cannot function normally. Therefore, an invalid data detector 71 is provided to check the existence of invalid data. The invalid data referred to here is defined from various viewpoints. For example, in FIGS. 5 and 6, D1 → D1
This is a case where the data that is transmitted two times as in the order of D2 → D2 or D1 → D2 → D1 → D2 do not match each other.

If the invalid data detection unit 71 finds that the read data is normal, it is set in the management data setting unit 91 via the line 94. CP
U11 reads this read data. Regarding the above retry, ACK = ″ by the acknowledge “H” detection unit 61.
When the error bit generation unit 62 detects that H ″ has been detected a predetermined number of times, for example, three times in succession, an error bit is generated so as to stop the retry.
This error bit is sent to the timing generator 52, and the read access is completed. On the other hand, an error flag "1" is set in the error bit setting unit 92. This flag is C
It is read by the PU 11 (error notification). At this time, "0" is set in the management data setting unit 91. The content of normal data is set in the management data setting unit 91 via the AND gate 93, and the CPU 11 knows whether the memory 21 or 22 is the memory up to immediately before. Send command SW.

When the CPU 11 requests the operation under the new software at the time of writing to the management memory 33, the management data setting unit 91 from the CPU 11 is used.
In the memory, new management data indicating which memory should be used is set. The comparison unit 51, which holds the setting data until immediately before, knows that the management data has been changed, and drives the timing generation unit 52. The generator 52
Supplies various timing signals to each block as described above. In response to this timing signal, the start / stop bit generation unit 53 first starts with the start bit (ST
Output). Further, this is input to the parallel / serial conversion unit 54. The conversion unit 54 reads / writes the 7-bit word address (all "0") shown in FIG.
The write bit (R / W = "L") is converted into serial data and transmitted. This transmission is a pair of bidirectional buffers 5.
5 and 55 ', the former buffer 55 is used. The buffer 55 also receives the control of the bus control unit 56 to generate the high impedance (HZ) shown in FIGS. 3 and 4.

When the transmission of the start bit, the word address and the read / write bit is completed, the bus control unit 56 sets the buffer 55 to the high impedance (HZ) state, and enters the state of receiving the acknowledge (ACK) from the management memory 33. "L" level acknowledge (ACK)
In response to this, in order to serially transfer the management data to the management memory 33, the buffer 55 is put into an output state by the bus control unit 56, and the data set in the management data setting unit 91 from the parallel / serial conversion unit 54 is changed to the timing. Based on the timing signal from the generation unit 52, it is converted into 8-bit serial data and output.

After that, the buffer 55 is set to a high impedance (HZ) state, and an acknowledge (ACK) from the management memory 33 is received from the buffer 55 '. The transmission of the above 8-bit management data and the acknowledgment ("
L ″) is repeatedly input, and finally, the stop bit (STOP) is output from the start / stop bit generation unit 53 to end the access to the management memory 33.

The acknowledge (ACK) returned from the management memory 33 as described above is set to "L". If this ACK is "H", it is estimated that some sort of transfer abnormality (including noise) has occurred on the management data transfer line 34. This ACK = ″
The H "is detected by the acknowledge" H "detector 61. The detector 61 resets the timing generator 52 to the initial state by the detection. Then, the generator 52 starts / stops the bit. The generation unit 53 is controlled to immediately output a stop bit (STOP), and again the start bit (START) is output.
Is output. The write operation is retried here.

Regarding the above-mentioned retry, acknowledge "H"
When the error bit generation unit 62 detects that the detection unit 61 has detected ACK = “H” for a predetermined number of times, for example, three times in succession, an error bit is generated so as to stop the retry. That is, this error bit is sent to the timing generator 52, and the read access is completed. On the other hand, the error flag ″ is set in the error bit setting unit 92.
1 "is set. This flag is read by the CPU 11 (error notification).

Meanwhile, during the write operation, if the management data itself sent to the management memory 33 is abnormal, the download circuit 30 cannot normally function. Therefore, if the data itself set in the management data setting unit 91 is abnormal, the management data setting unit 91 does not hold the abnormal data but keeps the previous state. As a result, the comparison unit 51 does not perform detection, and the management memory 33 is not accessed.

A block 81 shown in the upper right of the management control unit 32 of FIG. 9 is a specific example of the weight means 80. In this block 81, the stop bit (STOP) shown in FIG.
If a certain period of time has not passed after the output from the CPU 11, the CPU 11
The sending of the switching command that occurs next is not allowed. For example, the block 81 does not permit the transmission of the switching command until, for example, 10 ms has elapsed after receiving the stop bit. This 10 ms is the time required after the data is written in the normal E ² PROM (management memory 33) until the write data becomes stable. A counter is preferably used as the block 81.

FIG. 10 is a view showing another form of the weight means 80 shown in FIG. When the CPU 11 starts up with the new version of the software, the wait means in FIG. 10 makes the start of new processing wait until it confirms that the startup has been successful. When the new version of the software starts up, the start trigger ST is output and the timer 83 is set. The timer time is set in advance. If the new software is assembled so that a specific signal is generated when a certain time is set after the new software starts running, the timer time corresponds to this certain time setting.

With this arrangement, the start trigger S
If the "time setting" signal is not generated and the timer 83 times out after T is output, it can be seen that the startup of the new software has failed. This time-out is displayed by the time-out detection unit 84, the CPU 11 is interrupted, and the startup is stopped. This is effective in preventing hang-up due to defects in new software or runaway.

Finally, the management data setting section 9 in FIG.
1 and a detailed example of the comparison unit 51. FIG. 11 is a diagram showing a detailed example of the management data setting unit 91 and the comparison unit 51 in FIG. 9, and FIG. 12 is a time chart of signals appearing in main parts in FIG. As illustrated, the management data setting unit 91 includes a D-FF 101, and the comparison unit 51 includes a D-FF.
102, an E-OR gate 103, and a differentiating circuit 104. The comparison unit 51 compares the new management data set in the management data setting unit 91 and held in the D-FF 101 with the old management data previously set and held in the D-FF 102. If even one bit is different from the old management data, E ² PROM (management memory 3
A trigger is output to the timing generation unit 52 to start backup access to 3).

Referring also to FIG. 12, the current management data is "00000" as shown in the time chart of FIG.
001 ″ (4). Next, when there is a request from the CPU 11 to change to the new management data “00000010”, the new management data holding unit (D-FF101) changes at the rising edge of the CPU write pulse (2). ″ 0000001
Hold 0 ″ (3).

As a result, the new management data holding unit (D-FF
101) and the data in the old management data holding unit (D-FF 102) differ by 1 bit, and the output of the E-OR gate 103 changes to "H" (5). The differentiating circuit 104 differentiates the rising portion of the output of the E-OR gate 103 (6), and sets the trigger for starting the backup access to the E ² PROM (management memory 33) as the timing generation unit 5.
Output to 2. When the backup access to the E ² PROM is completed, the E ² PROM from the timing generation unit 52 is
At the rising edge of the pulse (7) indicating the end of access to the old management data holding unit (D-FF102), "000" is written.
“00010” is held, the output of the E-OR gate 103 changes to “L”, and the series of operations ends.

[0052]

As described above, according to the present invention, (1) the software by a single CPU is provided by interposing the download circuit 30 by hardware.
A processor device having a download function is realized.

(2) The switching control unit 31 forming the first main part of the download circuit 30 includes selectors 41, 42,
It can be realized by the decoder 43 or the like. (3) The introduction of the management control unit 32, which constitutes the second main part of the download circuit 30, enables autonomous memory switching independent of the CPU 11. (4) Management memory 33, which preferably comprises an E ² PROM
And the download circuit 30 are serially transferred.
This makes it possible to use the well-known serial interface function.

(5) When there is a switching command from the CPU 11, the management memory 3 is changed by the components shown in FIG. 11, for example.
Automatic rewriting to 3 is started. (6) The management control unit 32 performs the switching protection function by itself without the CPU by the retry means 60. (7) The management control unit 32 uses the protection means 70 to C
Demonstrate the switching protection function by itself without PU.

(8) The management control unit 32 uses the weight means 80 to perform the switching protection function by itself without the CPU.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a processor device according to the present invention.

FIG. 2 is a diagram schematically showing how downloading is performed according to the present invention.

FIG. 3 is a diagram (No. 1) showing a write sequence to a management memory.

FIG. 4 is a diagram (No. 2) showing the write (write) sequence to the management memory.

FIG. 5 is a diagram (No. 1) showing a read sequence to a management memory.

FIG. 6 is a diagram (No. 2) showing the read sequence to the management memory.

FIG. 7 is a diagram showing a specific example of the switching control unit shown in FIG.

8 is a schematic block diagram of a management control unit shown in FIG.

9 is a diagram showing a specific example of the management control unit shown in FIG.

10 is a view showing another form of the weight means shown in FIG.

11 is a diagram showing a detailed example of a management data setting unit and a comparison unit in FIG.

FIG. 12 is a time chart of signals appearing in main parts in FIG.

FIG. 13 is a diagram showing an outline of a conventional processor device.

[Explanation of symbols]

 10 ... Processor device 11, 12 ... CPU 13, 14 ... Data bus 21 ... First memory 22 ... Second memory 30 ... Download circuit 31 ... Switching control unit 32 ... Management control unit 33 ... Management memory 34 ... Management data transfer Line 41 ... First selector 42 ... Second selector 43 ... Decoder 44 ... Switching setting unit 50 ... Transfer control means 60 ... Retry means 70 ... Protecting means 80 ... Waiting means

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Daisuke Hirata 2-2-6 Jomi, Chuo-ku, Osaka City, Osaka Prefecture Fujitsu Kansai Digital Technology Stock Company In-house (72) Inventor Takunori Aono, Chuo-ku, Osaka City, Osaka Prefecture 2-6, Jomi Fujitsu Kansai Digital Technology Stock Company In-house (72) Inventor Tomihisa Takasugi 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited

Claims (8)

[Claims] 1. A single CPU (11), a first memory (21) and a second memory (22) for storing first software and second software, respectively, and the first memory ( 21) and a second memory (22)
And a download circuit (30) for downloading the software stored in the switched memory to the CPU (11). A processor device having a software download function to perform. 2. The switching control unit (31) includes a first selector (41) and a second selector (42) corresponding to the first memory (21) and the second memory (22), respectively. A decoder (43) for decoding the address signal and the chip select signal from the CPU (11) and applying the decoded output to the first selector (41) and the second selector (42) in common. The processor device according to claim 1, wherein the first selector (41) and the second selector (42) are selectively activated by a switching command from the CPU (11). 3. The management circuit (32) for managing switching control by the switching control unit (31) is further included in the download circuit (30), and management control by the management control unit (32) is further provided. The management memory (33) for backing up management data, which is necessary management data and includes at least information indicating in which of the memories the software stored up to immediately before has been downloaded. The described processor device. 4. A management data transfer line (3) between the management control unit (32) and the management memory (33).
4. The processor device according to claim 3, wherein the processor data is connected in 4) to serially transfer the management data. 5. The management control unit (32) is configured so that the two memories (21, 22) are connected to the CPU (11).
The processor device according to claim 3, wherein the information in the management memory (33) is automatically rewritten at the same time when a switching command for switching to any one of the above is received. 6. Retry means for restarting a write or read operation to the management memory (33) when there is an abnormality in the transfer on the management data transfer line (34) in the management control unit (32). The processor device according to claim 4, comprising (60). 7. In the management control unit (32), when the management data itself transferred on the management data transfer line (34) is abnormal, data is transferred to and from the management memory (33). Protective measures to stop (70)
The processor device according to claim 4, further comprising: 8. A wait for waiting for the writing of new management data to the management memory (33) until a predetermined time elapses after the writing of the management data to the management memory (33) is completed. Means (80)
The processor device according to claim 4, wherein the processor device is provided in the management control unit (32).