JPH08251443A - Automatic frequency controller - Google Patents

Abstract

PURPOSE: To prevent the distortion or bent of the upper pattern of a screen pattern even when a horizontal period is deviated from a regular state. CONSTITUTION: The phase of a horizontal synchronizing signal subjected to synchronization separation is compared with the phase of a reference pulse from a horizontal system count-down circuit 17 by a phase detection circuit 15 and its error component is fed to a control terminal of an oscillator 16 as a frequency control voltage. The output of the oscillator 16 is fed to the horizontal system count-down circuit 17. A reference bias depending on the combined parallel resistance of resistors R1, R2 is set equal to the frequency control voltage in the regular horizontal synchronization state. A switch SW1 is open for a V mask period to eliminate an equivalent pulse for a vertical blanking period and an offset is provided to the frequency control voltage, and when an input horizontal frequency is offset, a large deviation from the control voltage in the lock state is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control device used in a color television integrated circuit or the like for obtaining a horizontal synchronizing pulse synchronized with a horizontal synchronizing signal, for example.

[0002]

2. Description of the Related Art FIG. 4A shows an example of an automatic frequency control device. The video signal is input to the sync separation circuit 12 via the input terminal 11. The separated composite sync signal is input to the vertical sync separation circuit 13. The vertical sync separation circuit 13 separates the vertical sync signal and supplies the separated output to the reset terminal of the vertical system countdown circuit 14. The vertical system countdown circuit 14 receives a horizontal synchronizing pulse of a horizontal cycle as a clock input, and counts down with this clock to create a V mask pulse for removing an equivalent pulse near the vertical synchronizing period.

The composite sync signal output from the sync separation circuit 12 is subjected to equivalent pulse removal by a V mask pulse to become a horizontal sync signal, which is input to the phase detection circuit 15. The phase detection circuit 15 compares the phase of the reference pulse from the horizontal system countdown circuit 17 that creates the horizontal synchronization pulse (reference pulse) with the horizontal synchronization signal, and supplies the error to the control terminal of the oscillator 16. To do. Oscillator 1
6 is controlled so that its oscillation frequency becomes high or low in accordance with the error component. The output of the oscillator 16 (n times the horizontal frequency) is input to the horizontal system countdown circuit 17 as a clock, and the horizontal system countdown circuit 1 is counted by counting (dividing into 1 / n) this clock.
Reference numeral 7 is a reference pulse and the vertical countdown circuit 14 described above.
Creating a clock for.

Phase detection circuit 15 and oscillator 1 of the above circuits
6. The loop composed of the horizontal countdown circuit 17 operates as a frequency control loop synchronized with the horizontal synchronizing signal. When switching channels, the frequency control voltage when a regular video signal (horizontal synchronizing signal of regular cycle) is input as a means for shortening the time for which the oscillator 16 locks from the free-run state in order to shorten the pull-in time. With a voltage equal to
The signal is supplied to the frequency control terminal via a.
This also serves to prevent the frequency control voltage from becoming unstable because the phase detection is not performed during the V mask period.

[0005]

In the above circuit,
Since the reference bias is set as the frequency control voltage value when a normal video signal is input, if the horizontal cycle of the input signal deviates from the normal one, the actual frequency control voltage value and the reference There is a direct current (DC) offset with the bias.

Since the reference bias is supplied to the frequency control terminal via the resistor Ra, the frequency control voltage other than the phase detection period is controlled so that the DC offset is absorbed. FIGS. 4B and 4C show changes in the frequency control voltage in the case of the normal horizontal period and in the case of the normal horizontal period. Further, FIGS. 5 and 6 also show changes in the frequency control voltage near the vertical synchronization.

FIGS. 4B and 5 show the case where the horizontal synchronizing signal arrives at a regular horizontal period, and the reference bias and the phase detection result (frequency control voltage) match. On the other hand, FIGS. 4C and 6 show the case where the horizontal synchronization signal is deviated from the normal horizontal cycle, and the reference bias and the phase detection result (frequency control voltage) are offset. In the case of FIG. 6, since the free-run state is set during the V mask period, the frequency control voltage gradually approaches the reference bias.
In the picture period, the state shifts to the offset state again.

Although the frequency control voltage changes as described above, there is no particular problem because the DC offset shown in FIG. 4C is small, but in the vicinity of the V mask period shown in FIG. The DC offset becomes a problem because it becomes large. That is, it takes time to reach the normal pull-in state after the elapse of the vertical period. Therefore, it means that the frequency control voltage is still deviated in the several horizontal period period after the V mask, and the frequency of the oscillator is in the control process. As a result, distortion will occur in the upper part of the screen.

Therefore, an object of the present invention is to provide an automatic frequency control device capable of preventing the distortion or bending of the upper portion of the screen even when the horizontal cycle is deviated from the normal state. is there.

[0010]

According to the present invention, the value of the reference bias is switched between the vertical mask period and the other period, so that the reference bias is synchronized with the normal horizontal period and in the free-run state. An offset is given to the oscillation frequency of the oscillator during the vertical mask period. That is, specifically, a sync separation means for separating a composite sync signal from a video signal, a vertical mask pulse output means for separating a vertical sync signal from the composite sync signal to generate a vertical mask pulse, and the vertical mask. A phase for obtaining a horizontal control signal output means for obtaining a horizontal synchronization signal from the composite synchronization signal by using a pulse, a phase comparison between the horizontal synchronization signal and a reference pulse, and an error component corresponding to the phase difference as a frequency control voltage. Comparison means, oscillating means whose oscillation frequency is controlled by the frequency control voltage, reference pulse output means for obtaining the reference pulse using the oscillation output from the oscillating means, and the frequency control voltage for the oscillating means A circuit for applying a reference bias as the above, before the horizontal synchronizing signal is obtained in a regular cycle in a period excluding the vertical mask pulse period. The reference bias having the same value as the frequency control voltage is output, but during the vertical mask pulse period, the second reference bias offset from the reference bias is output, and the frequency control voltage for performing the frequency pulling is largely deviated. And a reference bias switching means for preventing the above.

[0011]

By the above means, the frequency control voltage in the frequency pull-in state synchronized with the signal deviated from the normal horizontal cycle does not largely deviate during the vertical mask period, and the upper portion of the screen does not bend.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 is an embodiment of the present invention, and FIG. 2 is a timing chart shown for explaining the operation of this embodiment.

In FIG. 1, the same parts as those of the circuit shown in FIG. 3 are designated by the same reference numerals. That is, the video signal is input to the sync separation circuit 12 via the input terminal 11. The separated composite sync signal is input to the vertical sync separation circuit 13. The vertical sync separation circuit 13 separates the vertical sync signal and supplies the separated output to the reset terminal of the vertical system countdown circuit 14. The vertical countdown circuit 14
The horizontal sync pulse of the horizontal cycle is used as the clock input,
A countdown is performed by this clock, and a V mask pulse for removing an equivalent pulse near the vertical synchronization period is created.

The composite sync signal output from the sync separation circuit 12 is subjected to equivalent pulse removal by a V mask pulse, becomes a horizontal sync signal, and is input to the phase detection circuit 15. The phase detection circuit 15 compares the phase of the reference pulse from the horizontal system countdown circuit 17 that creates the horizontal synchronization pulse (reference pulse) with the horizontal synchronization signal, and supplies the error to the control terminal of the oscillator 16. To do. Oscillator 1
6 is controlled so that its oscillation frequency becomes high or low in accordance with the error component. The output of the oscillator 16 (n times the horizontal frequency) is input to the horizontal system countdown circuit 17 as a clock, and the horizontal system countdown circuit 1 is counted by counting (dividing into 1 / n) this clock.
Reference numeral 7 is a reference pulse and the vertical countdown circuit 14 described above.
Creating a clock for.

Phase detection circuit 15 and oscillator 1 of the above circuit
6. The loop composed of the horizontal countdown circuit 17 operates as a frequency control loop synchronized with the horizontal synchronizing signal. When switching channels, the frequency control voltage when a regular video signal (horizontal synchronizing signal of regular cycle) is input as a means for shortening the time for which the oscillator 16 locks from the free-run state in order to shorten the pull-in time. With a voltage equal to
It is supplied to the frequency control terminal through the parallel circuit of R1 and R2. This also serves to prevent the frequency control voltage from becoming unstable because the phase detection is not performed during the V mask period.

Here, the switch SW1 is connected in series with the resistor R2.
The switch SW1 is turned off by the V mask pulse. For this reason, the frequency control voltage applied to the oscillator 16 is supplied with the reference bias with a voltage drop due to only the resistor R1 during the period of the V mask pulse, especially for the DC component excluding the phase error component, and during the other periods. The reference bias is supplied with a voltage drop due to the parallel resistance of the resistors R1 and R2 {(R1 · R2) / R1 + R2}.

Here, the parallel resistance value of the resistors R1 and R2,
Resistor R1, so that the value of the conventional resistor Ra becomes the same,
If the value of R2 is determined, the frequency control voltage (reference bias) is applied via the same resistance value as that in the conventional case except the V mask period, so that the same performance as that in the conventional case can be obtained with respect to the pull-in time of the oscillator. On the other hand, in the V mask period, the reference bias is applied through a higher resistance than in the conventional case, so that the amount of the DC offset absorbed in the V mask period is reduced, the deviation of the frequency control voltage after the V mask is reduced, and the oscillator Since the deviation of the oscillation frequency of is also reduced, the bending at the upper part of the screen is reduced.

FIG. 2 shows a case where the horizontal synchronizing signal is deviated from the normal horizontal cycle, and the reference bias and the phase detection result (frequency control voltage) are offset. In the V mask period, the frequency control voltage gradually approaches the reference bias, but in the pattern period, it shifts to the offset state again. However, according to this circuit, since the frequency control voltage is given so as to have an offset from the reference bias, it does not greatly deviate from the value at the time of pulling in. Therefore, when the picture period is entered, the value at the time of drawing is set earlier than in the conventional case, and the upper portion of the screen is not distorted.

The parallel resistance value of the resistors R1 and R2 determines the pull-in time of the oscillator from free run, and the value of the resistor R1 determines the pull-in time of the oscillator after V-mask. Therefore, the pull-in time from the free run and the pull-in time after the V mask can be optimally selected depending on the resistance values of the resistors R1 and R2. The conventional ratio of the pull-in time after the V mask is calculated by {(R1 × R2) / (R1 + R2)} / R1 (times) (where R1 = Ra).

For example, if the resistance Ra is 10 KΩ, the resistance R
If 1 is 30KΩ and resistor R2 is 15KΩ, R1 and R
Since the parallel resistance value of 2 is 10 KΩ, the pull-in time from the free run of the oscillator is the same as the conventional one. Further, during the V mask period, the reference bias is applied only through the resistor R1, so that R1 = 30 and the reference bias is 1/3 as compared with the conventional Ra = 10. Therefore, the absorption of the DC offset is also reduced to 1/3, and the pull-in time after the V mask period of the oscillator is 1/3. Of course, resistors R1 and R
If the parallel resistance values of 2 are the same, the pull-in time after the V mask period of the oscillator can be changed by changing the value of the resistor R1.

The above frequency control loop is more effective when applied to a dual AFC circuit not limited to the above embodiment. Here, the dual AFC circuit will be described.

In FIG. 3, a horizontal synchronizing signal separated from the video signal and having the equivalent pulse removed is supplied to the input terminal 31 and input to the phase comparator 33 of the first synchronizing circuit 32. The phase comparator 33 detects the phase difference between the output of the voltage controlled oscillator 35 and the input horizontal synchronizing signal, and gives the error component to the low pass filter (LPF) 34. LPF
The smoothed output output from 34 is the voltage controlled oscillator 35.
Is supplied to the control terminal of. As a result, the voltage controlled oscillator 3
The pulse of the horizontal cycle output from 5 is synchronized with the input horizontal synchronization signal. Next, the pulse having the horizontal period is supplied to the phase comparator 37 of the second synchronizing circuit 36. In the phase comparator 37, the sawtooth wave of the horizontal period supplied from the delay unit 43 is sampled by the input pulse, and the sampled value is given to the low pass filter (LPF) 38. The smoothed output of the LPF 38 is given to the control terminal of the voltage controlled oscillator 39. The output of the voltage controlled oscillator 39 is input to the shaping circuit 40 and the waveform is shaped. The waveform-shaped pulse having the horizontal period is supplied to the integrator 42 via the amplifier 41. In the integrator 42,
A sawtooth wave is generated in synchronization with the pulse of the horizontal cycle and is supplied to the delay device 43. The above circuit is a horizontal automatic frequency control circuit for obtaining a horizontal pulse (flyback pulse) synchronized with the input horizontal synchronizing signal at the output of the amplifier 41.

Here, in the above circuit, the first and second synchronizing circuits 32 and 36 are used. This is because the first synchronizing circuit 32 having a slow response and the second synchronizing circuit having a fast response. Three
This is because 6 are combined so that no noise is input from the outside in the former stage, while in the latter stage, it is possible to immediately respond to the input phase.

[0024]

As described above, according to the present invention, it is possible to prevent the distortion or bending of the upper portion of the screen even when the horizontal cycle is deviated from the normal state.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is an operation explanatory view shown for explaining the operation of the circuit of FIG.

FIG. 3 is an explanatory diagram of a dual AFC circuit.

FIG. 4 is a diagram shown for explaining a conventional automatic frequency control device and an operation example thereof.

5 is a diagram shown for explaining a further operation example of the automatic frequency control device of FIG. 4;

FIG. 6 is a diagram shown for explaining a further operation example of the automatic frequency control device of FIG. 4;

[Explanation of symbols]

12 ... Sync separation circuit, 13 ... Vertical sync separation circuit, 14 ...
Vertical system countdown circuit, 15 ... Phase detection circuit, 16
... Oscillator, 17 ... Horizontal system countdown circuit, R1, R
2 ... Resistor, SW1 ... Switch.

Claims (2)

[Claims] 1. A sync separation means for separating a composite sync signal from a video signal, a vertical mask pulse output means for separating a vertical sync signal from the composite sync signal to generate a vertical mask pulse, and the vertical mask pulse A horizontal synchronizing signal output means for obtaining a horizontal synchronizing signal from the composite synchronizing signal, and a phase comparing means for phase comparing the horizontal synchronizing signal and a reference pulse and obtaining an error component according to the phase difference as a frequency control voltage. An oscillating unit whose oscillation frequency is controlled by the frequency control voltage, a reference pulse output unit for obtaining the reference pulse by using an oscillation output from the oscillating unit, and a reference as the frequency control voltage for the oscillating unit. A circuit for applying a bias, which is obtained when the horizontal synchronizing signal has a regular cycle in a period other than the vertical mask pulse period. The reference bias having the same value as the wave number control voltage is output, but during the vertical mask pulse period, the second reference bias offset from the reference bias is output, and the frequency control voltage that is performing the frequency pulling shifts greatly. An automatic frequency control device, comprising: 2. The automatic frequency control device according to claim 1, wherein the reference bias switching means is switching-controlled by the vertical mask pulse.