JPH08250000A - Latching relay switching circuit - Google Patents

Abstract

PURPOSE: To suppress heat generation caused by consuming electric power of a latching relay by installing a delay circuit for delaying a status signal and a switching condition input circuit, and driving the latching relay with a one-shot pulse signal. CONSTITUTION: A step-like operation controller switching signal is inputted into a switching condition input circuit 21 from switching signal lines 7, 8 of operation lines A, B. Latching relay coils 10, 12 are excited by driving of driving circuits 27, 28 based on an output signal from the circuit 21 to operate a contact 14. A status signal 15 is outputted according to this relay state and delay time is added to the status signal 15 in a delay circuit 26 constituted with a resistance and a capacitor. An output signal of the circuit 26 is inputted into the other terminal of an NAND circuit, and a step-like operation controller switching signal is converted into a one-shot pulse signal, and it is outputted from the circuit 21. In the circuit 26, a delay program executed with a CPU may be used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latching relay switching circuit for controlling a latching relay for switching the operation of multiplexed controllers.

[0002]

2. Description of the Related Art FIG. 10 is an external view of a switching operation unit of a monitor panel 100 using a switch circuit which is a conventional latching relay switching circuit used in an instrumentation system, for example. In the figure, 1 is an operation system changeover switch for changing over the operation system by the controller of the instrumentation system to the operation system A, and 2 is an operation system changeover switch for changing the operation system to the operation system B. That is, in this instrumentation system, the controller and its operating system are duplicated in the operating system A and the operating system B.

FIG. 11 is a functional block diagram of a monitor panel 100 using a conventional latching relay switching circuit. In the figure, 3 is a switch circuit which is a conventional latching relay switching circuit, 4 is a display circuit, and 5 is an LV card for detecting an abnormality of a power supply device (not shown) and an abnormality of each card in the CPU unit. It is an LV card interface which is an interface of a circuit device.

FIG. 12 is a circuit diagram showing a circuit configuration of the switch circuit 3. In the figure, 7 is a driving system A switching signal line to which a stepwise operation controller switching signal for switching to the driving system A is sent, and 8 is a stepwise operation controller switching signal for switching to the driving system B. An incoming operation system B switching signal line, 9 is a drive device for exciting the set side latching relay coil 10, and 11 is a drive device for driving the reset side latching relay coil 12. 13 is a pull-up resistor for pulling up the status signal line 15 to the power supply voltage, 1
Reference numeral 4 is a contact for generating a status signal. The contact 14 is a contact that is opened and closed depending on the excited states of the set-side latching relay coil 10 and the reset-side latching relay coil 12, and the movable contact 14a when the set-side latching relay coil 10 is in the excited state. And the fixed contact 14b are connected, and when the latching relay coil 12 on the reset side is excited, the movable contact 14a and the fixed contact 14
and c are connected.

A monitor panel 100 equipped with a conventional latching relay switching circuit used in this instrumentation system.
Then, by pressing the operation system changeover switch 1 or the operation system changeover switch 2 of the monitor panel 100, a failure occurs in the manual system for switching the operation system to the operation system A or the operation system B and the operation system currently operating. It is possible to perform two types of operation system switching, which is an automatic method in which the operation system is automatically switched to another operation system when doing so. In addition, even when the power supply of the controller is down, a latching relay with a latch function is used to maintain the operating condition of the operating system that is currently operating. It can be restarted by the operating system that was performing.

When the operation system is switched by the manual method, the operation system changeover switch 1 of the monitor panel 100 is used.
When is pressed, the operation controller switching signal for switching to the operating system A becomes valid, the driving device 9 operates to excite the latching relay coil 10, and the operating system switches to the operating system A. Further, after the operating system is switched to the operating system A, the operating system A remains valid unless the operating system changeover switch 2 is pressed.

[0007]

Since the conventional latching relay switching circuit is constructed as described above, the respective latching relay coils 10 and 12 are driven by the driving device 9 or the driving device 11 by the stepwise operation controller switching signal. Since it is driven via the latching relay, the latching relay coil 10 on the set side or the latching relay coil 12 on the reset side is still energized and consumes unnecessary current even after the switching of the operating system by the latching relay is completed. However, there was a problem that the latching relay generated heat.

The present invention has been made to solve the above problems, and by driving the latching relay by the original one-shot pulse signal, the consumption current of the latching relay and the heat generation of the latching relay are suppressed. It is an object of the present invention to obtain a latching relay switching circuit that can be used.

Another object of the present invention is to provide a latching relay switching circuit which can easily cope with latching relays having different characteristics.

[0010]

According to a first aspect of the present invention, there is provided a latching relay switching circuit for driving a coil of a latching relay based on a stepwise operation controller switching signal for switching a controller, and the latching circuit. A delay circuit for delaying a status signal output according to the state of the relay, and controlling the supply of the operation controller switching signal based on the output of the delay circuit to excite the coil of the latching relay by the drive circuit. And a switching condition input circuit for stopping.

A latching relay switching circuit according to a second aspect of the present invention includes a delay circuit including a combination of a capacitor and a resistor.

A latching relay switching circuit according to a third aspect of the present invention includes a delay circuit for delaying a status signal by a delay program executed by a CPU.

A latching relay switching circuit according to a fourth aspect of the present invention sequentially shifts a status signal based on a clock signal having a predetermined repetition frequency and delays the status signal according to the number of clock signals supplied. The register is used as a delay circuit.

[0014]

In the latching relay switching circuit according to the present invention, the status signal output according to the state of the latching relay is delayed, and the stepwise operation controller switching signal is one-shot based on the delayed status signal. The latching relay is converted into a pulse signal, and the latching relay can be driven by the original one-shot pulse signal to suppress current consumption and heat generation of the latching relay.

In the latching relay switching circuit according to the second aspect of the present invention, the status signal output according to the state of the latching relay is delayed by a delay circuit composed of a combination of a capacitor and a resistor, and the delayed status signal is output. Based on the above, the stepwise operation controller switching signal is converted into a one-shot pulse signal, and the latching relay can be driven by the original one-shot pulse signal to suppress current consumption and heat generation of the latching relay.

According to another aspect of the present invention, a latching relay switching circuit delays a status signal output according to the state of the latching relay by a delay program executed by the CPU, and based on the delayed status signal, the step The above operation controller switching signal is converted into a one-shot pulse signal, and the latching relay can be driven by the original one-shot pulse signal to suppress current consumption and heat generation of the latching relay.

In the latching relay switching circuit according to the invention of claim 4, the status signal output according to the state of the latching relay is delayed according to the internal state when the shift register performs the shift operation, and the delayed status signal is delayed. The stepwise operation controller switching signal is converted to a one-shot pulse signal based on a status signal, and the latching relay can be driven by the original one-shot pulse signal to suppress current consumption and heat generation of the latching relay. To do.

[0018]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of the latching relay switching circuit of the first embodiment. In FIG. 1, the same parts as those in FIG. 12 are designated by the same reference numerals and the description thereof is omitted.
In the figure, reference numeral 21 is a switching condition input circuit for converting a stepwise operation controller switching signal into a one-shot pulse signal, and its circuit configuration is shown in FIG. As shown in the figure, the switching condition input circuit 21 has an input terminal to which an operation system A switching signal line 7 to which a step-like operation controller switching signal for performing operation switching to the operation system A is sent is connected. , A first NAND circuit 23 having the other inverting input terminal to which the status signal line 22 for outputting a delayed status signal is connected, and a step-like operation controller switching signal for switching the operation to the operation system B. A second NAND circuit 24 having an input terminal connected to the operation system B switching signal line 8 sent thereto and another input terminal connected to the status signal line 22 outputting the delayed status signal is provided. ing.

The output terminal of the first NAND circuit 23 is connected to the input side of the driving device (driving circuit) 27, and the second NA
The output terminal of the ND circuit 24 is connected to the input side of a driving device (driving circuit) 28. Reference numeral 25 is an inverter circuit for inverting the status signal. The drive device 27 and the drive device 28 excite and drive the latching relay coil 10 and the latching relay coil 12 by the L-active output signal of the switching condition input circuit 21.

Reference numeral 26 is a delay circuit, which is composed of a resistor 26a and a capacitor 26b as shown in FIG. 3, and is inputted with a delay time corresponding to a time constant determined by the values of the resistor 26a and the capacitor 26b. It is added to the status signal.

Next, the operation will be described. It is assumed that the controller of the instrumentation system is duplicated and the controller of the driving system B is operating now. Also contact point 14
Indicates that the movable contact 14a and the fixed contact 14c are connected to each other because the latching relay coil 12 on the reset side is excited.

FIG. 4 is a timing chart when the switching operation from the operation system B to the operation system A is performed by the latching relay switching circuit, and the operation is switched from the operation system B controller to the operation system A controller. Then, as shown in FIG. 4A, the stepwise H-active operation controller switching signal is changed to the operation system A switching signal line 7
Output to At the same time, the operation controller switching signal of the driving system B switching signal line 8 is turned off as shown in FIG. The step-like operation controller switching signal output to the driving system A switching signal line 7 is the first NAND
It is supplied to one input terminal of the circuit 23. At this time the first
The other inverting input terminal of the NAND circuit 23 is in a state where the status signal of the “L” level which is the output of the delay circuit 26 is supplied, and the output of the inverting input terminal is the “H” level. .

Therefore, when the operation controller switching signal is output to the driving system A switching signal line 7, the switching condition input circuit 21
The output of the first NAND circuit 23 drops to the'L 'level as shown in FIG. 7E, and the drive device 27 excites the latching relay coil 10. Further, at this time, the output of the second NAND circuit 24 of the switching condition input circuit 21 is because the operation controller switching signal output to the operation system B switching signal line 8 is turned off as shown in FIG. It becomes "H" level and the excitation of the latching relay coil 12 is released.

Further, since the latching relay coil 10 is excited by the driving device 27, the contact 14 is the movable contact 1.
4a and the fixed contact 14b are connected, the input of the inverter circuit 25 changes to the “L” level, the input of the delay circuit 26 changes to the “H” level, and the delay circuit 26
Output is'H 'according to the time constant determined by the values of the resistor 26a and the capacitor 26b as shown in FIG.
Ascend to level. And this delay circuit 2
When the output level of 6 exceeds the threshold value (VDD / 2), the input from the inverting input terminal of the first NAND circuit 23 of the switching condition input circuit 21 falls to the'L 'level as shown in FIG. The output of the first NAND circuit 23 is changed from the previous state of'L 'level to'H' level.

As a result, the stepwise H-active operation controller switching signal shown in FIG. 4A output to the operation system A switching signal line 7 is L as shown in FIG.
It is converted into an active one-shot pulse signal, and the drive device 27 excites the latching relay coil 10 and switches the latching relay during this “L” level period. Therefore, the coil of the latching relay is excited by the original one-shot pulse, so that current consumption and heat generation are suppressed. The L-active one-shot pulse width in this case is equal to the resistance 26 of the delay circuit 26.
Since this value is a value according to the time constant determined by the values of a and the capacitor 26b, this time constant is determined to a value that satisfies the latching characteristics of the latching relay used.

FIG. 5 is a timing chart showing the operation when switching from the driving system B to the driving system A. Similar to when switching from the driving system A to the driving system B, the output to the driving system B switching signal line 8 is performed. The stepwise H-active operation controller switching signal shown in (b) of FIG. 5 is converted into an L-active one-shot pulse signal as shown in (d) of FIG. The drive device 28 excites the latching relay coil 12 to switch the latching relay.

Example 2. Embodiment 2 of the present invention will be described below with reference to the drawings. FIG. 6 is a circuit diagram showing the configuration of the delay circuit 31 of the latching relay switching circuit of the second embodiment. In the first embodiment, the status signal is delayed by using the time constant determined by the values of the resistor and the capacitor, but in this embodiment, the CPU 31c is delayed.
Using a microprocessor unit having an input port 31b and an output port 31a, the CPU 31c executes a delay program when switching the operating system to delay and delay the status signal input to the input port 31b. Output status signal from the output port 31a.

FIG. 7 is a flow chart showing a delay program executed by the CPU 31c. When the operating system is switched, the change in the status signal is read from the input port 31b (steps ST1 and ST2).
After performing the delay process, the output port 31a outputs the change in the status signal fetched from the input port 31b (step ST3).

In this embodiment, since the delay time of the status signal is determined by the delay program, the delay program is configured to determine the delay time based on the set value of the digital switch or the like. The delay time can be easily changed according to the characteristics of the latching relay.

Example 3. The third embodiment of the present invention will be described below with reference to the drawings. In the first embodiment, the status signal is delayed by using the time constant determined by the values of the resistor and the capacitor, but in the third embodiment, the status signal is delayed according to the internal state of the shift register. . FIG. 8 is a block diagram showing the configuration of the delay circuit 41 of the latching relay switching circuit of the third embodiment. In the figure, 41a is a shift register, 41b
Is a clock signal line to which a clock signal is supplied, and 41c is a short-circuit pin for short-circuiting the jumper pins 41d. FIG. 9 is a timing chart showing the process of generating the delay status signal by the shift register 41a.

In this embodiment, in consideration of the case where the latching relay needs to be replaced, the delay time corresponding to each output stage of the shift register is selected by selecting between the jumper pins 41d short-circuited by the short-circuit pin 41c. It is possible to take out the applied delay status signals A, B, C and D.

[0032]

As described above, according to the first aspect of the invention, the delay circuit for delaying the status signal output according to the state of the latching relay, and the operation controller based on the output of the delay circuit Since it is configured to include a switching condition input circuit that controls and turns off the supply of the switching signal and stops the excitation of the coil of the latching relay by the drive circuit, the latching relay can be driven by the original one-shot pulse. Therefore, there is an effect that a latching relay switching circuit that can suppress current consumption and heat generation can be obtained.

According to the invention of claim 2, a delay circuit comprising a combination of a capacitor and a resistor for delaying the status signal output according to the state of the latching relay, and the delay circuit based on the output of the delay circuit. Since the configuration is provided with a switching condition input circuit for controlling the supply of the operation controller switching signal to be turned off and stopping the excitation of the coil of the latching relay by the drive circuit, the latching relay is driven by the original one-shot pulse. Therefore, there is an effect that a latching relay switching circuit that can suppress current consumption and heat generation can be obtained.

According to the third aspect of the present invention, the CPU executes the delay program to delay the status signal output according to the state of the latching relay, and the delay circuit based on the output of the delay circuit. Since the configuration is provided with a switching condition input circuit for controlling the supply of the operation controller switching signal to be turned off and stopping the excitation of the coil of the latching relay by the drive circuit, the latching relay is driven by the original one-shot pulse. Therefore, there is an effect that a latching relay switching circuit can be obtained in which the consumption current and heat generation can be suppressed, and the width of the one-shot pulse for driving the latching relay can be easily changed with respect to the latching relay having different characteristics.

According to the invention of claim 4, a delay circuit, which is a shift register for delaying the status signal output according to the state of the latching relay, and the operation controller switching signal based on the output of the delay circuit. Since it is configured to include a switching condition input circuit for controlling the supply of the power supply to turn off and stopping the excitation of the coil of the latching relay by the drive circuit, the latching relay can be driven by the original one-shot pulse, There is an effect that a latching relay switching circuit can be obtained which can suppress current consumption and heat generation and can easily change the width of the one-shot pulse for driving the latching relay by selecting the output of the shift register.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a latching relay switching circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a switching condition input circuit of the latching relay switching circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a delay circuit of the latching relay switching circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the latching relay switching circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the latching relay switching circuit according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a delay circuit of a latching relay switching circuit according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing the operation of the delay circuit of the latching relay switching circuit according to the second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a delay circuit of a latching relay switching circuit according to a third embodiment of the present invention.

FIG. 9 is a timing chart showing the operation of the delay circuit of the latching relay switching circuit according to the third embodiment of the present invention.

FIG. 10 is an external view of a switching operation unit of a monitor panel of a conventional latching relay switching circuit.

FIG. 11 is a functional block diagram of a monitor panel using a conventional latching relay switching circuit.

FIG. 12 is a circuit diagram showing a configuration of a conventional latching relay switching circuit.

[Explanation of symbols]

10, 12 latching relay coil, 21 switching condition input circuit, 26, 31 delay circuit, 26a resistor, 2
6b capacitor, 27, 28 drive device (drive circuit), 31c CPU, 41a shift register.

Claims (4)

[Claims] 1. A stepping operation controller switch for switching the controller in a latching relay switching circuit of a multiplexed controller for switching the operation from the controller that has been operating until then to another controller by switching the latching relay. A drive circuit for exciting the coil of the latching relay based on a signal, a delay circuit for delaying a status signal output according to the state of the latching relay, and switching of the operation controller based on the output of the delay circuit A latching relay switching circuit, comprising: a switching condition input circuit that controls signal supply and stops excitation of the coil of the latching relay by the drive circuit. 2. The latching relay switching circuit according to claim 1, wherein the delay circuit comprises a combination of a capacitor and a resistor. 3. The latching relay switching circuit according to claim 1, wherein the delay circuit delays the status signal by a delay program executed by a CPU. 4. The delay circuit is a shift register that sequentially shifts the status signal based on a clock signal having a predetermined repetition frequency and delays the status signal according to the number of the clock signals input. The latching relay switching circuit according to claim 1, wherein the switching circuit is a latching relay switching circuit.