JPH08249894A - Read-out circuit for data from read only memory, write-in circuit for data to read only memory and write-in method for data to read only memory - Google Patents

Abstract

PURPOSE: To make data read-out speed compatible with data transmission speed by providing plural read only memories in a read-out circuit and reading out alternately divided and written data. CONSTITUTION: An address counter is set to 16 bits and one word of a ROM is set to 8 bits, and four ROMs 103a-103d are provided. When Q0 and Q1 of an address counter 101 are both 'H', the ROM 103 is accessed making an output signal of an output enable generation section 102a as active. Therefore, an enable repeating frequency is made one fourth of a clock, data read out from each ROM are taken in a D-FF 104 by the clock, and data converted to parallel to series by loading respectively to a shift register 105 by the same enable signal is outputted from an output terminal SD0. On the other hand, in writing data, transferring data of plural buffer RAMs is controlled by setting of SW, s RAM address switching section, and a RAMCS separating section, and the order of writing data in a ROM is automatically set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data read circuit for a read only memory (hereinafter abbreviated as ROM), RO.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data writing circuit for M and a method for writing data to a ROM, and in particular, a data reading circuit from a ROM in consideration of matching between a data reading speed and a data speed on a transmission line, and a data writing circuit matching the reading circuit. And a data writing method.

For example, when testing a transmission system,
A large amount of test data can be easily generated by writing the data in the ROM in advance and reading the written data and using it as the test data.
Further, when a test is performed by changing the content or format of the data, the test for arbitrary data can be easily realized by rewriting the data stored in the ROM or exchanging the ROM. Therefore, in the above test, RO
The method of transmitting the data written in M to the transmission system is widely used.

By the way, the transmission speed in the transmission system is remarkably increased, and although the operating speed of the ROM is also improved, there is a mismatch with the transmission speed. In order to eliminate this inconsistency by speeding up the ROM, it is necessary to devote excessive efforts to its development.
Even if a ROM having an operating speed that can match the transmission speed is realized by this effort, it will be very expensive, and it is impossible to economically realize the test apparatus.

Therefore, the RO provided at an acceptable price
It is desirable to employ M and resolve the above inconsistencies by the way the data is read from it. Further, if the above-mentioned inconsistency is to be solved by the data read circuit from the ROM, there is a restriction on the read method, which causes R
There are restrictions on how to write data to the OM. This restriction in writing increases the burden on the creator of test data, so that it is necessary to develop a data writing circuit for ROM and a method therefor together with the development of a reading circuit.

[0005]

2. Description of the Related Art FIG. 51 shows an example of a conventional read circuit from a ROM. In FIG. 51, 101 is an address counter, 103 is a ROM storing data, and 105
Is a D-type flip-flop (hereinafter abbreviated as D-FF). Here, the address counter is illustrated as 16 bits, and one word in the ROM is illustrated as 8 bits.

FIG. 52 is a time chart of a conventional data read circuit from a ROM. Hereinafter, FIG. 51 and FIG.
The operation of the conventional data reading circuit from the ROM will be described with reference to FIGS.

The outputs Q0 to Q15 of the address counter are used as the addresses of the ROM, and the output of the ROM is taken into the D-FF at the rising edge of the clock (hereinafter abbreviated as CK).
Send 8 bits in parallel. Therefore, if one test data is formed by the same bit of each word, 8
It can output different types of test data at the same time.

FIG. 53 shows the structure of a conventional ROM writer. In FIG. 53, 201 is a personal computer for controlling data writing, 301 is an RS-232C port, 302 is a level conversion unit from 12 volt system to 5 volt system, 303
Is an asynchronous interface receiver (hereinafter abbreviated as SIO receiver), 304 is an oscillator, 305 is a logical sum (hereinafter abbreviated as OR) circuit, 306 is a central control unit (hereinafter abbreviated as CPU), 307 Is the edge detector,
308 is a switch (hereinafter abbreviated as SW), and 309 is a pull-up resistor. Reference numeral 310a is a first decoder (hereinafter abbreviated as decoder 1. The nth decoder described later is also abbreviated as decoder n), 310b is a decoder 2, 310c is a decoder 3, and 310a to 310c are input / output spaces. Used as an address decoder. 311 is a read register (hereinafter abbreviated as R register), 312 is a write register (hereinafter abbreviated as W register), and 313 is a read / write register (hereinafter R).
/ W register). Also, 314a is a decoder 4, 314b is a decoder 5, and 314a and 314 are decoders.
b is used as an address decoder in the memory space. Reference numeral 317 is a program ROM storing a write program, 318 is a random access memory (hereinafter abbreviated as buffer RAM) for temporarily storing write data, and 401 is a target R to which data is written.
OM. Incidentally, the ROM writer is constituted by the elements denoted by reference numerals in the 300s in FIG. Also, RO
The functions of the M writer include a data transfer function from the personal computer to the ROM writer, a write function to the target ROM, a verify function, a checksum function, and a load function from the target ROM to the personal computer. Data transfer function, target ROM
Since it is related to the write function to, the configuration for realizing the function following the verify function is omitted in the drawing.

FIG. 54 is a flowchart for data transfer in a conventional ROM writer, and FIG. 55 is a flowchart for data writing in a conventional ROM writer. The operation of the conventional ROM writer will be described below with reference to FIGS. 54 and 55 with reference to FIG.

First, when data is transferred from the personal computer to the ROM writer, SW in FIG. 53 is opened and "H" is supplied to the edge detector and the R register. C1. Every time data is sent from the personal computer through the RS-232C port, an interrupt request is sent to the CPU.
After enabling the interrupt, the CPU reads the interrupt status register of the R register and determines whether or not the SIO reception interrupt is generated. If it is not the SIO reception interrupt (No), it returns to the original state and waits for the next interrupt request. C2. If the SIO reception interrupt is determined in step C1 (Yes), the SIO reception buffer of the R register is read. C3. It is determined whether the information read in step C2 is address information. C4. If it is determined in step C3 that the information is address information (Yes), the information is written in the address buffer of the R / W register and waits until the next SIO reception interrupt occurs.

The subsequent SIO reception information is the data to be written in the ROM and the checksum information, but the amount of these information is determined by the format existing as the industry standard. For example, in the case of the HEX format of Intel, the address information is followed by 32 bytes of data information and 1 byte of checksum information. These judgments are made by the program stored in the program ROM. C5. In step C3, if the SIO reception information is not address information (No), it is determined whether or not it is data. C6. When it is determined that the data is data in step C5 (Y
In es), the value written in the address buffer of the R / W register is read. C7. The received data is stored in the buffer R using the value read in step C6 as an address for accessing the buffer RAM.
Write to AM. C8. It is determined whether the address read in step C6 is the final address. If it is determined that the address is the final address (Yes), the data transfer ends. C9. If it is determined in step C8 that it is not the final address (No), the address of the address buffer of the R / W register is updated and the next reception information is waited for. C10. If it is determined in step C5 that the received information is not data (No), the received information is the checksum information, so the checksum is performed and the next received information is waited for. Since the next information is address information, the above operation is started again. Then, the above operation is repeated until the final address is judged at C8.

Next, writing of data to the target ROM is performed as follows. In this case, close the SW and supply "L" to the edge detector and R register
Interrupt U. D1. The CPU reads the interrupt status register of the R register and determines the occurrence of the SW interrupt. If the SW interrupt has not occurred (No), it returns to the original state and waits for the occurrence of the SW interrupt. D2. When it is determined in step D1 that the SW interrupt has occurred (Yes), the CPU reads the SW status register of the R register and determines whether SW is "L". When SW is not "L" (No), the process returns to D1 and waits for the generation of the SW interrupt.

When it is determined that the SW interrupt has occurred (Yes), the write operation is started because it is the write mode to the target ROM. D3. Access address to buffer RAM 0 in RAMAD
Set address 000 (hexadecimal expression). D4. The contents of the RAMAD address of the buffer RAM are read out and stored in the CPU register or the like. D5. "H" is written in the DX bit of the I / O space of the W register to enable writing to the target ROM. D6. The output of the decoder 5 disables the chip select (hereinafter abbreviated as CS) of the buffer RAM, and the data temporarily stored in step 4 is stored in the target ROM at the same address as the buffer RAM read in step D4. Write. D7. "L" is written to the DX bit of the I / O space of the W register to enable writing to the buffer RAM. D8. It is determined whether the data has been written up to the final address.
If it is the final address (Yes), the write operation is ended. D9. When not writing to the final address (No)
, The access address to the buffer RAM is advanced by 1 and updated, and the process returns to step D4.

[0014]

In the conventional data reading circuit from the ROM, the data read from the ROM is output as it is. If is not higher than the transmission speed of the transmission system, the data expected from the transmission system side cannot be transmitted. By the way, comparing the speed of reading data from the ROM with the speed of the transmission system, the speed of the transmission system is significantly higher. Therefore, there is a problem that the conventional data reading circuit from the ROM cannot be adapted to the transmission of the test data of the transmission system.

Further, in the conventional ROM writer, the data sequentially written in the buffer RAM is sequentially written in the target ROM. By the way, when trying to solve the problem in the data read circuit from the ROM as described above, it is not difficult to imagine that the way of writing to the ROM is restricted and the burden on the designer is increased in writing the data.

In order to cope with such a problem, the present invention provides a data read circuit from a ROM, a data write circuit matched with the read circuit, and a method therefor in consideration of matching between the data read speed and the data speed on the transmission path. The purpose is to provide.

[0017]

FIG. 1 is a first embodiment of the first invention of the present invention. In FIG. 1, 101 is an address counter, and 102a is an output enable generation unit that controls data output from the ROM. Reference numeral 103a denotes a first ROM (hereinafter, abbreviated as ROM0 according to a convention), and 103b denotes a second ROM (hereinafter, R0 according to a convention).
It is abbreviated as OM1. In addition, the (m + 1) th ROM (m is 0
And a positive integer) are abbreviated as ROMn), and 103c is R.
OM2 and 103d are ROM3. Similarly, 104-
n (n is 0 and a positive integer) is D-FFn, 105-n
(N is 0 and a positive integer) is the shift register n.

The structure of FIG. 1 is characterized by including four ROMs,
The last two digits of the count value of the address counter, "0",
Addresses that can access each ROM are divided by a combination of "1", the repetition frequency of output enable of each ROM is reduced to 1/4 of the configuration of FIG. 51, and the read data from each ROM is D- by a clock. FF
In the D-FF, and the data taken in the D-FF are converted into parallel / serial data by a shift register and transmitted.

FIG. 19 shows a first embodiment of the second invention of the present invention. In FIG. 19, 201 is a personal computer for controlling data writing, 301 is an RS-232C port,
302 is a level conversion unit from 12 volt system to 5 volt system, 303 is an oscillator, 304 is an OR circuit (hereinafter abbreviated as OR), 306 is a CPU, 307 is an edge detection unit, and 308a to 308- 3 is SW1, respectively
SW2, SW3, 309a through 309-3 are each pulled
An up resistor 1, a pull up resistor 2 and a pull up resistor 3. Reference numeral 310a is a decoder 1, 310b is a decoder 2, 310c is a decoder 3, and 310a to 310c are used as address decoders in the input / output space. 311 is a read register (hereinafter abbreviated as R register), 312 is a write register (hereinafter abbreviated as W register), and 313 is a read / write register (hereinafter R).
/ W register). Also, 314a is a decoder 4, 314b is a decoder 5, and 314a and 314 are decoders.
b is used as an address decoder in the memory space. 315 is a RAM provided with a plurality (4 in the case of FIG. 1)
The address switching unit 316 for switching the address of R is for separating CS of RAM provided with a plurality (4 in the case of FIG. 1) R
AMCS separation unit, 317 is a program ROM storing a write program, and 318a to 318d are buffer RAM0, buffer RAM1 and buffer RAM, respectively.
2. The buffer RAMs 3 and 401 are target ROMs for writing data. In addition, in FIG.
A ROM writer is configured by the elements with reference numerals of the series. Also, the ROM writer's function is
Although there is a data transfer function to the M writer, a write function to the target ROM, a verify function, a checksum function, and a load function from the target ROM to the personal computer, the present invention has a data transfer function from the personal computer to the ROM writer and the target ROM. Since it is related to the write function of, the configuration for realizing the function following the verify function is omitted in the drawing.

The feature of the configuration shown in FIG. 19 is applied to the configuration shown in FIG. The point is that data can be written in the ROM without the designer having to be aware of the order of writing data in the ROM.

[0021]

FIG. 2 is a time chart of the first embodiment of the first invention. In FIG. 1, the address counter is 16 bits and one word in the ROM is 8 bits. Therefore, the count output of the address counter is 16 bits from Q0 to Q15. this house,
Q0 and Q1 are supplied to the output enable generation unit to generate Q0
When both Q1 and Q1 are "H", the "H" output is supplied to the ROM to deactivate the output enable signal of the ROM. This is the ROMXOE of FIG. Therefore, ROM
The repetition frequency of XOE is 1 / the repetition frequency of CK.
4.

On the other hand, the address of each ROM is 16 bits from A0 to A15, but A0 and A1 are each RO.
A value unique to M, that is, "A0, A1 in ROM0
“=“ 0,0 ”,“ 0,1 ”in ROM1, RO
M1, "1, 0", ROM3, "1,
It is fixed to 1 ". Therefore, ROMm (m is 0 to 3)
In, only the address (4i + m) (i is 0 and a positive integer) can be accessed. Specifically, in the case of ROM0, only the addresses 0, 4, 8, ... Can be accessed, in the case of ROM1, only the addresses 1, 5, 9, ... Can be accessed, and in the ROM2. In case of 2, 6, 10, ...
.. can be accessed only, and in the case of the ROM 3, only addresses 3, 7, 11, ... Can be accessed. This is indicated by RO from the ROM0 address in FIG.
It is an M3 address. However, in the ROMm address (m = 0 to 3) of FIG. 2, the address is displayed in hexadecimal representation. Then, the L of the data read from each ROM
The SB is sequentially taken into the D-FF0 and the MSB is taken into the D-FF7 sequentially. Thereafter, by the same signal as XOE generated by the output enable generation unit, the data captured in D-FF0 is stored in the shift register 0, the data captured in D-FF1 is stored in the shift register 1, ..., D- F
The data fetched by F7 is loaded into the shift register 7, and so on, is shifted by the clock, and is output from the serial data output terminal (hereinafter abbreviated as SDO). Therefore, from the output of shift register 0
Address, No. 1 of ROM1, No. 2 of ROM2, ROM3
No. 3 address, No. 4 address of ROM0, ... LSB of data
Are sequentially output. Generally speaking, from the output of the shift register n (n = 0 to 7),
No. 1 of ROM1, No. 2 of ROM2, No. 3 of ROM3, No. 4 of ROM0, ...
Bits are sequentially output. This is D0 to D in FIG.
7 However, in Dn of FIG. 2, the address is shown in hexadecimal.

Therefore, reading from each ROM can be performed at a speed of 1/4 as compared with the case of the configuration of FIG. 51, and the maximum read speed of the ROM itself is 1/4 of the transmission speed.
If it is above, the reading speed from ROM and the transmission speed can be matched.

FIG. 20 shows an example of SW setting contents in the first embodiment of the second invention. There are three SWs, but SW
3 and SW1 and SW2 have different roles. That is, when "H" is set in SW3, the buffer R is sent from the personal computer.
Data transfer mode to AM, (in this case SW1 and S
W2 setting is ignored (Don't Care)) S
When W3 is set to "L", the RAMCS separation unit controls which of the four buffer RAMs to write data to the ROM by the setting of SW1 and SW2, as shown in the table of FIG. Buffer RAM
A0 and A1 of the address information A output by the CPU
0 and A1 are given.

On the other hand, in the data transfer mode to the four buffer RAMs, the address information A output from the CPU is A
Which buffer R depending on the value of 0, A1, A14, A15
The RAMCS separation unit controls whether or not to activate the CS of AM, and the CPU is used for A0 and A1 of each buffer RAM.
Gives A14 and A15 of the address information output by.

As a result, the data to be written in the target ROM is transferred from the respective buffer RAM0 to the buffer R.
The target RO is stored only in the buffer RAM that is sequentially stored in AM3 and is determined by the combination of the settings of SW1 and SW2.
Data is written to M. Therefore, the target ROM
Corresponding to the buffer RAM0 to the buffer RAM3, and replace each buffer RAM with the target ROM.
All the data can be written to the four target ROMs by writing the data to the target ROM. If the four ROMs with the written data are connected to the read circuit having the configuration of FIG. 1, the data can be read according to the time chart of FIG. Can be sent out. The address of the data to be written to the four target ROMs may be controlled by the RAM address switching unit and the RAM address separating unit, so that the designer does not need to be aware of the address, and the load on the designer is reduced. Can be reduced, and at the same time, address errors due to human error can be eliminated.

[0027]

FIG. 3 is an example of an output enable generator in the first embodiment of the first aspect of the present invention. FIG. 3 (a) is a circuit configuration and FIG. 3 (b) is a time chart.

In FIG. 3A, 102a-1 is an AND circuit (hereinafter abbreviated as a NAND circuit) having logical inversion, and 102a-2 is a D-FF. The input terminal of the NAND circuit has the LSB of the count value of the address counter.
The two bits on the side, Q0 and Q1, are input.
The NANDs of 0 and Q1 are supplied to the data terminal D of the D-FF, and the inverted CK is supplied to the CK terminal of the D-FF.

The time chart is shown in the range of count values 0 to 9 of the address counter. However, since it has the above-mentioned configuration, when both Q0 and Q1 are "H", the D-FF
"L" is taken in and the inverted output terminal XQ of the D-FF
Outputs "H" at this time. This output XOE is ROM
0 is supplied to the XOE of the ROM 3 to control reading from the ROM. As shown in FIG. 3, a pulse appears in the XOE at a rate of 1 in 4 of the count value of the address counter, so the number of times of reading from each ROM is as shown in FIG.
It becomes 1/4 of the case of 1. Also, as already explained, R
The last two digits A0 and A1 of the address from OM0 to ROM3 are fixed to values unique to each ROM. For this reason, the address to be written in each ROM is also 1/4 of that in the case of FIG. Therefore, if the ROM0 to ROM3 in FIG. 1 can operate at a speed 1/4 that of the ROM in FIG. 51, it becomes possible to match the transmission speed.

In FIG. 1, four ROMs are provided, the last two digits A0 and A1 of the address of each ROM are set to a unique value, and read out by a combination of the LSB2 bits Q0 and Q1 of the count value of the address counter. However, the p-digit on the LSB side (p is a positive integer) of the address of each ROM is set to a unique value, and the reading is performed by the combination of the p-digit on the LSB side of the count value of the address counter. If the circuit similar to that shown in FIG. 1 is configured to include the 2 ^p ROM so as to be controlled, the read speed of the ROM can be reduced to 1/2 ^p of the transmission speed.

FIG. 4 shows a second embodiment of the first invention of the present invention. In FIG. 4, 101 is an address counter, and 102b is an output enable generation unit that controls data output from the ROM. 103a is ROM0, 103
b is ROM1, 103c is ROM2, and 103-7 is RO
It is M7. Similarly, 104-n (n is an integer of 0 and 7 or less in FIG. 4) is D-FFn, and 105-n (n is an integer of 0 and 7 or less in FIG. 4) is a shift register n. Further, 106a and 106b are SW1 and SW2 for setting the number of ROMs to be used, 107a is a pull-up resistor 1 and 107b is a pull-up resistor 2, 108.
a, 108b, 108c, ..., 108e are ROMs depending on the last three digits of the count value of the address counter.
Is an address switching unit that determines an address to access the.

The feature of the configuration of FIG. 4 is that, like the configuration of FIG. 1, the output enable generation unit has a function of controlling reading from the ROM by 3 bits of the LSB side of the count value of the address counter, and the address switching unit. In, the address which can access each ROM is arbitrarily set by the LSB3 bit of the address counter, and SW
It is to provide a function of designating the number of ROMs to be used by setting 1 and SW2.

FIG. 5 shows an example of the output enable generator in the second embodiment of the first aspect of the present invention. FIG. 5 (a) is a circuit configuration and FIG. 5 (b) is a time chart. Figure 5
In (a), 102b-1 and 102b-2 are NAND circuits, 102b-1 to 102b-3 are D-FFs, 102b-6 is a 2to4 decoder (hereinafter abbreviated as 2: 4DEC), and 102b-7. Through 10
2b-10 is an AND circuit, 102b-11 is O
It is an R circuit. Here, the 2: 4DEC is a circuit that outputs “H” to one of the four output terminals depending on the combination of the levels of the two inputs.
In (b) 102b-6, the output terminals described as "00" have both SW1 and SW2 set to "L".
At the time of, "H" is output.

In FIG. 5A, the AND circuit 102b.
The output of 2: 4DEC is given to one input terminal of the AND circuit 102b-10 and the AND circuit 102b-10.
-7 to the other input terminal of the AND circuit 102b-10, CK and Q0 are respectively D-FF by inverting CK.
Inversion output (XQ1 in FIG. 5B) when taken into 102b-3, NAND of Q0 and Q1 (X0.
Inversion output when 1) is taken into D-FF102b-4 by CK inversion (XQ2 in FIG. 5B), Q0, Q1 and Q
An inverted output (XQ3 of FIG. 5B) when the NAND of 2 (X0.1.2 of FIG. 5B) is taken into the D-FF 102b-5 by CK inversion is given. Therefore, O
From the R circuit 102b-11, CK is set when SW1 and SW2 are set to "00", and XQ1 is set to "1" when set to "01".
XQ2 is output when it is "0" and XQ3 is output when it is "11" to control the output from the ROM. Here, if the frequency of CK is 1, the frequencies of XQ1, XQ2, and XQ3 are 1/2, respectively. It becomes 1/4 and 1/8. This is one R
If equipped with OM, set SW1 and SW2 to "00"
If two ROMs are provided, set SW1 and SW2 to "01", and if four ROMs are provided, SW1
It means that the setting of SW2 and SW2 should be set to "10", and the setting of SW1 and SW2 should be set to "11" when eight ROMs are provided. FIG. 6 shows the correspondence between the settings of SW1 and SW2 in the second embodiment of the first invention and the number of ROMs used.

FIGS. 7 to 14 show an example (part 1) of the address switching unit in the second embodiment of the first invention of the present invention to the address switching in the second embodiment of the first invention of the present invention. In the example of the part (8), the configuration of FIG.
A circuit for determining 0, A1, A2, a circuit for determining A0, A1, A2 of the ROM 1 ..., A circuit for determining A0, A1, A2 of the ROM 7 is shown in FIG.

Since FIGS. 7 to 14 have similar configurations,
Referring only to FIG. 7, 108a-1 to 108a
a-13 is an AND circuit, 108a-13 is 2: 4 DE
C, 108a-14 to 108a-16 are OR circuits. The twelve AND circuits are arranged in groups of four, and the output of 2: 4DEC is applied to one input terminal of the four AND circuits in all groups without duplication. In the first group, Q0 of the address counter is supplied to the other input terminal of the one AND circuit, and "L" is supplied to the other input terminals of the remaining three AND circuits. In the group, Q1 is the second AN
It is supplied to the other input terminal of the D circuit and "L" is given to the other input terminal of the remaining two AND circuits. In the third group, Q2 is the other input of the three AND circuit. It is supplied to the terminal and "L" is applied to the other input terminal of the other AND circuit. In the configurations of FIGS. 8 to 14, the remaining three ANs of the first group
The levels given to the other input terminals of the D circuit, the remaining two AND circuits of the second group, and the remaining one AND circuit of the third group are all given in different combinations.

FIG. 15 is a table showing the operation of the address switching unit in the second embodiment of the first invention, and FIGS.
This is a summary of the operation of the address switching unit shown in FIG.
Now, when the setting of SW2 and SW1 is "00", which R
The last three digits of OM address A0, A1, A2 are also addresses.
It becomes equal to the LSB three digits Q0, Q1, Q2 of the count value of the counter. This means that all ROMs are accessed simultaneously, and in this case, for example, RO
If only M0 is mounted, all data can be read from ROM0. Then, as described above, the read speed at this time becomes equal to the CK speed.

Next, when the setting of SW2 and SW1 is "01", the address A0 of the even-numbered ROM is "0",
A0 of odd-numbered ROM is fixed to "1", which RO
Also in M, the addresses A1 and A2 are equal to the count values Q1 and Q2 of the address counter. This means that even-numbered ROMs can be accessed only when the LSB of the address is "0", and odd-numbered ROMs can be accessed only when the LSB of the address is "1". For example, if only ROM0 and ROM1 are mounted, all data can be read from these two ROMs. Then, as described above, the read speed at this time is 1/2 of CK.

When the setting of SW2 and SW1 is "10", the LSB2 bit of the addresses of ROM0 and ROM4 is fixed to "00", the LSB2 bit of the addresses of ROM1 and ROM5 is fixed to "01", and ROM2 is set. And R
The LSB2 bit of the address of OM6 is fixed to "10", the LSB2 bit of ROM3 and ROM7 is fixed to "11", and the address A2 becomes equal to the count value Q2 of the address counter. This means that ROM0 and ROM4 can be accessed only when the LSB2 bit of the address is "00", ROM1 and ROM5 can be accessed only when the LSB2 bit of the address is "01", and ROM2 and ROM6.
Can be accessed only when the LSB2 bit of the address is "10", and ROM3 and ROM7 have the LSB2 bit set to "1".
1 "means that access is possible only. That is, in this case, exactly the same operation as the configuration of FIG. 1 is realized. For example, if ROM0 to ROM3 are mounted,
All data can be read from these four ROMs. Then, as described above, the reading speed at this time is 1/4 of CK.

Finally, the setting of SW2 and SW1 is "11".
In case of, the LSB3 bit of the address of ROM0 is "0".
00 ", the LSB 3 bits of the address of ROM1 are" 00 "
1 ", the LSB 3 bit of the address of ROM2 is" 01 "
0 ", ..., The LSB3 bit of the address of the ROM7 is fixed to" 111 ". Therefore, each ROM is accessed only when the LSB3 bit of the count value of the address counter is equal to the fixed value. be able to.
That is, in this case, the ROM0 to the ROM7 are alternately accessed, so that by mounting the ROM0 to the ROM7, all the data can be read from these eight ROMs.

That is, according to the configuration of FIG. 4, the number of ROMs from which data is to be read can be specified by setting the SW, so that the ROM read speed is fixed and flexible even when there are various transmission speeds. It becomes possible to respond.

Here, in order to make the description more concrete, the maximum number of ROMs to be used is designated as one of 1, 2, 4, and 8 by the combination of the settings of the two SWs, and the respective addresses are switched by the address switching unit. Although the example in which the 3 bits on the LSB side of the ROM address are designated to different values has been described, the SW is not limited to two, and the maximum number of ROMs used is not limited to eight. For example, the maximum number of ROMs used is 16 when setting with three SWs, and in this case, the LSB side of each ROM address is 4
The bits may be specified as different values. Generally, when setting with SW of p (p is a positive integer),
The maximum number of ROMs that can be used is 2 ^{p + 1. In} this case, the LSB side (p + 1) bit of each ROM address may be designated to a different value.

FIG. 16 shows a third embodiment of the first invention of the present invention. In FIG. 16, reference numeral 101 is an address counter, and 102a is an output enable generation unit that controls data output from the ROM. 103a is ROM0, 10
3b is ROM1, 103c is ROM2, and 103d is RO
It is M3. Similarly, 104a, 104b, 104c,
.., 104e are D-FFs, 105a, 105b, 10
Reference numerals 5c, ..., 105e are shift registers. Also, 1
09a is + 1ADDER for adding 1 to the MSB2 bit of the address counter, 109b is + 2ADDER for adding 2 to the MSB2 bit of the address counter, 10
9c is +3 ADDER that adds 3 to the MSB2 bit of the address counter, and 110 is a 4: 4 DEC which outputs "H" to one of the four output terminals depending on the combination of the MSB2 bit of the count value of the address counter.
11a, 111b, 111c, ..., 111e are data rearrangement circuits.

The feature of the configuration of FIG. 16 is that the values obtained by adding 0 or 1 or 2 or 3 to the MSB2 bit of the count value of the address counter are ROM0, ROM1 and ROM respectively.
2. By setting the LSB 2 bits of the address of the ROM 3, when reading data from a plurality of ROMs, an area that is not accessed in each ROM is not left, and the combination of the level of the MSB 2 bits of the address counter in the data rearrangement circuit By changing the order of serial conversion of the data read from the ROM, the order of the data to be sent out is kept the same as in the case of the configuration of FIG.

FIG. 17 is a diagram for explaining the method of determining the ROM access address in the third embodiment of the first aspect of the present invention, which is the MSB of the count value of the address counter.
It specifically shows how 0, 1, 2, 3 is added to 2 bits to be converted into 2 bits of LSB of the address of the ROM to access the 4 ROMs. For this reason, addresses are usually displayed in hexadecimal notation, but here, they are displayed in binary notation, and for the sake of intuitive understanding, they are displayed at intervals of 4 bits.

The leftmost column of the table of FIG. 17 shows the count value of the address counter of 16 bits, the left is the MSB side, and the right is L.
It is the SB side. Therefore, the rightmost two bits are Q15 and Q
14 and the leftmost two bits are Q1 and Q0.
In the middle column of the table, the converted address is 14 bits, the leftmost is A13, and the rightmost 2 bits are A1 and A0. And in the right column, the R
Corresponding R to specify whether it is the address of OM
OM.

The address counter is 00 in hex representation.
Counting from 00 to FFFF is performed (hereinafter, in the text, for example, when displayed as 0000h, it is regarded as hexadecimal expression. That is 00000 in binary expression.
Corresponding to 0000000000).

During this period, Q15 and Q14 are "00" from 0000h to 3FFFh (0011111111111111 in binary representation). During this period, R
A1 and A0 of OM0 are determined by adding 0 to "00" of Q15 and Q14, so they are fixed to "00" and ROM1
A1 and A0 are fixed to "01" because 1 ("01") is added to "00", and A1 and A0 of ROM2 are "0".
Since 2 (“10”) is added to 0 ”, it is fixed to“ 10 ”, and A1 and A0 of the ROM 3 are 3 (“ 1 ”to“ 00 ”).
1)) is added and fixed to "11". Therefore, among the converted addresses, the addresses where A1 and A0 are "00" are the addresses for accessing ROM0, and A1 and A0 are "01". The address is the address to access ROM1, and the address where A1 and A0 are "10" is R
Address for accessing OM2, A1 and A0 are "11"
Is the address for accessing the ROM3. Since the combination of 0 and 1 is repeated in sequence for each count value of 4, the ROMs of 4 are evenly accessed.

Next, when the count value of the address counter is 4000h (010000000000000000) to 7FFFh (0111111111111111), Q15 and Q14 are "01". During this period, R
A1 and A0 of OM0 are determined by adding 0 to "01" of Q15 and Q14, so they are fixed to "01", and ROM1
A1 and A0 of "2" are fixed to "10" because 1 ("01") is added to "01", and A1 and A0 of ROM2 are "0".
Since 2 (“10”) is added to 1 ”, it is fixed to“ 11 ”, and A1 and A0 of the ROM 3 are 3 (“ 1 ”to“ 01 ”).
1)) is added and fixed to "00". Therefore, among the converted addresses, the addresses where A1 and A0 are "00" are the addresses for accessing the ROM3, and A1 and A0 are "01". The address is the address to access ROM0, and the address where A1 and A0 are "10" is R
Address for accessing OM1, A1 and A0 are "11"
Is the address for accessing the ROM2. Since the combination of 0 and 1 is repeated in sequence for each count value of 4, the ROMs of 4 are evenly accessed. What is important is that the ROM corresponding to the combination of 0 and 1 of A1 and A0 is different from the ROM up to 3FFFh. What kind of effect this brings will be understood by further analyzing the table of FIG.

Next, when the count value of the address counter is 8000h (1000000000000000) to BFFFh (10111111111111111), Q15 and Q14 are "10". During this period, similarly, A1 and A0 of ROM0 are set to "10", and ROM1
A1 and A0 of ROM2 are fixed to "11", A1 and A0 of ROM2 are fixed to "00", and A1 and A0 of ROM3 are fixed to "01". Therefore, A1 and A0 of the converted addresses are "00".
Is the address to access ROM2, A
Addresses where 1 and A0 are "01" are addresses that access ROM3, addresses where A1 and A0 are "10" are addresses that access ROM0, and A1 and A0 are "1".
The address that becomes "1" is the address that accesses ROM 1. Since the combination of 0 and 1 is repeated in sequence for each count value of 4, the four ROMs are accessed evenly. Again, 0 of A1 and A0 The ROMs corresponding to the combinations 1 and 3 are different from both 3FFFh and 7FFFh.

Similarly, the count value of the address counter is C000 (1100000000000000).
To FFFFh (1111111111111111)
Up to, A1 and A0 of the converted address are "00"
Is the address to access ROM1, A
Addresses where 1 and A0 are "01" are addresses that access ROM2, addresses where A1 and A0 are "10" are addresses that access ROM3, and A1 and A0 are "1".
The address that becomes "1" is the address that accesses ROM0. Again, the ROM corresponding to the combination of 0 and 1 of A1 and A0 is different from any of 3FFFh, 7FFFh, and BFFFh.

This completes the count of the address counter, but each time the count value passes 1/4 of the total count value, the correspondence between the combination of 0 and 1 of A1 and A0 and the accessible ROM is circular. It can be seen that the order has changed.

If all the count values of the address counter are LSB2 of the access address of the ROM
Bits are, for example, "00" in ROM0, "01" in ROM1, "10" in ROM2, "11" in ROM
When fixed to 3, only 1/4 of the address of each ROM can be accessed. This is because each of the four ROMs has four consecutive addresses
This means that all the data that needs to be read cannot be read unless the data is written to the address determined in correspondence with M. That is, four ROMs
Each has to have an address corresponding to four times the amount of information to be stored, which is not economical even though it matches the transmission speed.

However, according to the configuration of FIG. 16, the ROM corresponding to the pattern of 0 and 1 of the LSB 2 bits of the access address of the ROM changes depending on the count value of the address counter. ROM
There will be no inaccessible addresses even in. Therefore, in the case of FIG. 16, the use efficiency of the ROM address is quadrupled all at once.

In this way, while the efficiency of use of the addresses of the ROM is improved, the order of access to the ROM changes as the count of the address counter progresses. , Data will not be sent in the expected order. The data rearranging circuits 111a to 111e in FIG. 16 solve this problem. These eight data rearrangement circuits all have the same configuration.

FIG. 18 shows an example of the data rearrangement circuit in the third embodiment of the first invention of the present invention. In FIG. 18, 111-1 to 111-16 are AND circuits, 1
11-17 to 111-20 are OR circuits. The output of the 2: 4 DEC in FIG. 16 is supplied to the first input terminal of the AND circuit in groups of four in a fixed order, and the second input of the AND circuit in groups of four is provided. The data read from the ROM0 to the ROM3 are supplied to the input terminal in the order of the ring. All four output terminals of the four AND circuits are connected to the input terminals of the OR circuit, and the output of the OR circuit is led to the DD, DC, DB and DA terminals of the D-FF. Get burned. here,
The output of 2: 4DEC is supplied to a set of four AND circuits in a fixed order, but the output data of ROM0 to ROM3 is supplied to a set of four AND circuits in a fixed order. In this case, the output of the 2: 4 DEC may be supplied to the AND circuit in groups of four in the ring order.

Since the input of the 2: 4 DEC is Q15 and Q14, which are the MSB2 bits of the address counter, four ANDs are formed by combining them.
The output of ROM0 to ROM3 is DD to D in the circuit
It is led to the output of A. When the circuit of FIG. 18 is analyzed, the MSB2 bit of the count value of the address counter is “0”.
When it is 0 ", ROM0 is in DD, ROM1 and D are in DC.
The output of ROM2 is led to B and the output of ROM3 to DA, and the MSB2 bit of the count value of the address counter is "0".
When it is 1 ", ROM is 3 for DD, ROM0, D for DC
The output of ROM1 is led to B and the output of ROM2 is led to DA, and the MSB2 bit of the count value of the address counter is "1".
When it is 0 ", the ROM is DD2 and the DC is ROM3 and D.
The output of ROM0 is led to B and the output of ROM1 to DA, and the MSB2 bit of the count value of the address counter is "1".
When 1 ”, the ROM is DD1 and the DC is ROM2 and D
The result that the output of ROM3 is led to B and the output of ROM0 is led to DA can be easily obtained.

Therefore, while the MSB2 bit of the address counter is "00", the bits of the output data of the ROM0 are configured in the DD of each shift register, and the output data of the ROM1 is configured in the DC of each shift register. The bits that make up the output data of the ROM 2 in the DB of each shift register, and the D of each shift register.
Since bits constituting the output data of ROM3 are loaded into A, if the loaded bits are output from SDO, the output of shift register n (n is an integer of 0 and 7 or less) is output from ROM0 to R0M3. The Dn bits of data are sent out in order.

MSB of count value of address counter
While the 2 bits are “01”, the output data of ROM3 corresponds to DD, ROM0 corresponds to DC, ROM1 corresponds to DB, and ROM2 corresponds to DA. Therefore, the output of shift register n corresponds to ROM3, ROM0, ROM1, Dn bits of output data are sent out in the order of ROM2.

Similarly, while the MSB2 bit of the count value of the address counter is "01", the ROM is in the DD.
2, ROM3 for DC, ROM0 for DB, R for DA
Since the output data of OM1 corresponds, the shift register n
From the output of, ROM2, ROM3, ROM0, ROM1
The Dn bits of the output data are transmitted in this order, and while the MSB2 bit of the count value of the address counter is "11", ROM1 is in DD, ROM2 is in DC, and R is in DB.
Since the output data of ROM0 corresponds to OM3 and DA, the output of shift register n shows ROM1 and ROM.
2, Dn bits of output data are sent out in the order of ROM3, ROM0.

The above-mentioned transmission order is exactly the same as the relationship between the count value of the address counter and the corresponding ROM shown in FIG. That is, the shift register n outputs Dn bits of the output data of the ROM in the order of the count value of the address counter, and the transmitted data is the same as that in the case of the configuration of FIG.

In FIG. 16, since the MSB2 bit of the count value of the address counter is added and the LSB2 bit of the access address of the ROM is generated, the RO of 4 is obtained.
Is provided with the M, MSBq bit (q is a positive integer) ROM access by add operations from 0 to (2 ^q -1)
If the LSBq bits of the address are generated, 2
Data can be read from the ROM of ^q . At this time, the data rearrangement circuit rearranges the order of the 2 ^q data in the ring order, and it is necessary to provide the rearrangement circuit with 2 ^q . Therefore, in FIG. 16, 2: 4D
EC was applied to rearrange the rings in order, but in this case, it is necessary to apply q: 2 ^q DEC.

Up to now, the technique for realizing the matching between the reading speed of the ROM and the transmission speed in reading the data from the ROM has been described. The basis of this technology is to read data stored in multiple ROMs,
The read time allowed for one ROM is longer than the transmission cycle. However, when data is divided and stored in multiple ROMs, if the order of the stored addresses does not correspond to the order of the addresses to be accessed for reading, the transmitted data will differ from the expected data. The problem arises that

A second method of the present invention, which solves this problem, is a writing method and a writing circuit. Already in the section of action, for the first embodiment of the second invention of the present invention,
With reference to FIGS. 19 to 23, the ROM writer is provided with four buffer RAMs, and the RAM address switching unit and the RAMCS separating unit automatically divides the data to be written in the four ROMs and transfers the data to the four buffer RAMs. The outline of writing the data of the designated buffer RAM to the ROM has been explained. Here, a more detailed description will be given.

FIG. 21 shows an example of the decoder 5 in the first embodiment of the second invention of the present invention. In FIG. 21,
314b-1 is enabled by the memory request XMREQ that becomes active “L” when accessing the memory section, and the address 00 of the CPU outputs
The address decoder 314b-2 has a function of decoding 00h to FFFFh and outputting "H", and decoding 0000h to 3FFFh of the address and outputting "H". 23 is selected and the latter output of the address decoder is selected when SW3 is 0.
It is a selector that activates a signal to the AMCS separation unit.

That is, in the configuration of FIG. 21, the CPU is operated when SW3 is 1 and data is transferred from the personal computer to the RAM.
Outputs a signal that can activate the CS of the RAM over all the addresses output by the
When writing data to the OM, it has a function of activating the CS of the RAM for only 1/4 of all the addresses output by the CPU.

FIG. 22 shows an example of the RAM address switching unit in the first embodiment of the second invention of the present invention. FIG.
, 315-1 and 315-2 are AND circuits, one of which is an inverting input, 315-3 and 315-4 are AND circuits, and 3155 and 315-6 are OQ circuits. Then, L of the addresses output from the CPU is input to the non-inverted input terminals of the AND circuits 315-1 and 315-2.
The two bits of SB, A0 and A1, are supplied to the AN.
SW is connected to the inverting input terminal of the D circuits 315-1 and 315-2.
The level signal set by 3 is supplied. Further, a CPU is connected to one of the input terminals of the AND circuits 315-3 and 315-4.
A14 which is 2 bits of MSB of the address output by
And A15 are supplied to the AND circuits 315-3 and 31.
A level signal set by SW3 is supplied to the other input terminal of 5-4. Also, AND circuits 315-1 and 31
The output of 5-3 is ORed to be A0 of each RAM,
The outputs of the AND circuits 315-2 and 315-4 are ORed to be A1 of each RAM. Therefore, when SW3 is "H" in the transfer mode, the CPU
A14 output by RAM becomes A0 of RAM, A15 output by CPU becomes A1 of RAM, and SW in write mode
When 3 is "L", A0 output from the CPU is RA
It becomes A0 of M, and A1 output by CPU is A1 of RAM.
become. What this means will be described after the description of the RAMCS separator.

FIG. 23 shows an example of the RAMCS separating section in the first embodiment of the second invention of the present invention. In FIG. 23, one of 316a-1 has an inverted input AN
D circuit, 316a-2 is 4:16 DEC, 316a-3
To 316a-6 are OR circuits, 316a-7 are 2: 4D
ECs 316a-8 to 316a-11 are OR circuits, 3
16a-12 to 316a-15 are AND circuits.
Then, the 4:16 DEC is enabled when SW3 is "H", and A0, A out of the addresses output by the CPU
"H" is output to one of the 16 output terminals by the combination of 1, A14 and A15. Further, the 2: 4 DEC is enabled when SW3 is "L", and SW1 and SW
"H" is output to one of the output terminals of 4 according to the combination of the level signals set by 2.

First, when SW3 is "H", "1" is supplied from the decoder 5 to all the addresses output by the CPU. Therefore, when the W register is "L", that is, access to the RAM is designated. OR circuit 316a-8
To outputs 316a-11 to AND circuits 316a-12.
Through 316a-15. SW3 is "H"
4:16 DEC is enabled and CPU
"H" is output to the output terminal determined by the 0, 1 pattern of A0, A1, A14, A15 of the addresses output by the OR circuits 316a3 to 316a.
-6 and any of the OR circuits 316a-8 to 316a-
It is led to any one of the AND circuits 316a-12 to 316a-15 via any one of 11. For example, "000
When 0, “0101”, “1010”, and “1111”, the AND circuit 316a-12 outputs CS to RAM 0. At this time, the RAM address switching unit outputs CP.
A14 of the addresses output by U is supplied to RAM as A0, and A15 of the addresses output by the CPU is RA.
Supplied as A1 of M. That is, when "0000", the data is transferred to the address where A1 and A0 of RAM0 are "00", and when "0101", the A of RAM0 is A.
Data is transferred to an address where 1 and A0 are "01", and when "1010", A1 and A0 of RAM0 are "1".
Data is transferred to the address that becomes 0 "and" 1111 "
At this time, data is transferred to the address where A1 and A0 of RAM0 are "11". Specifically, the data at the address 0000h is stored in the address 0 of RAM0 at 4001h.
Data in RAM0 at address 1, 8002h data in RAM0 at address 2, C003h data in RAM0 at address 3, 0004 data in RAM0 at address 4
The data of 005 is at address 5 of RAM0, the data of BFFE is at address 6 of RAM0, and the data of C007 is RAM0.
No. 7 of ..., the data of FFFh is 3 of RAM0
It is transferred to FFFh. The address of the data thus transferred to the RAM0 is "corresponding RO" in FIG.
It matches the address described as ROM0 in the “M column”. That is, the data read from the ROM0 in the configuration of FIG. 16 is transferred to the RAM0.

On the other hand, when SW3 is set to "L", 4:16
DEC is disabled and 2: 4 DEC is enabled. At this time, if SW1 and SW2 are set to "00", the CS output by the 2: 4 DEC output is limited to the RAM0. Moreover, the output of the decoder 5 outputs CS to the RAM0 only during access to the RAM (W register is "L") between 0000h and 3FFFh of all addresses. At this time, from the RAM address switching unit, A0 of the addresses output by the CPU is RA
It is supplied as A0 of M, and A1 of the addresses output by the CPU is supplied as A1 of RAM. That is, at this time, data is written from RAM0 to the target ROM in the order of younger addresses. It can be easily confirmed that this relationship is the same for the RAM 1 and thereafter. That is, the data to be read from the ROM0 in the configuration of FIG. 16 is read by the RAM address switching unit of FIG. 22 and the RAMCS separation unit of FIG.
Is written to.

Similarly, in the configuration of FIG. 19, if SW1 and S2 are set to "01", the data transferred to RAM1 is written to the target ROM, and the data of RAM2 is written to the target ROM by setting "10". And
When set to "11", the data in RAM3 is the target ROM
Is written to. The relationship between the addresses of RAM1 to RAM3 and the address of the target ROM at this time is the same as the relationship between the address of RAM0 and the address of the target ROM. That is, the RAM address switching unit of FIG. 22 and the RAMCS separating unit of FIG. 23 can write data to the four target ROMs in the order in which they should be read from the four ROMs in the configuration of FIG.

Therefore, the four ROs used in the configuration of FIG.
When writing data to M, in which ROM the designer
There is no need to be aware of the order in which data is written. This not only reduces the burden on the designer, but also avoids an error in the write address due to a human error.

Although the number of buffer RAMs has been previously set to four for the sake of specific description, the technique of the present invention does not limit the number of buffer RAMs to four. Generally, when a 2 ^p buffer RAM is used, the following may be done. First, in the RAM address switching section, the MSB side p bit of the address designated by the CPU is given as the LSB side p bit of the RAM in the transfer mode, and the LSB side p bit of the address designated by the CPU is written in the RAM in the write mode. It is given as p bits on the LSB side. Next, in the RAMCS separation unit, in the transfer mode, the MSB side p bit of the address designated by the CPU and the LSB side p bit of "L",
Access to the 2 ^p buffer RAM is enabled alternately by the combination of "H", and in the write mode, the 2 ^p buffer RAM is combined by the combination of the p SW settings.
Only one of the buffer RAMs is accessible. For this, 4 in Figure 23: 16DEC instead of (2p): 2 applying the ^2p DEC, 2: p instead of 4DEC: applying a 2 ^p DEC. Also, the decoder 5 is 000
A terminal for decoding and outputting FFFFh from 0h;
A terminal for decoding and outputting 1/2 ^{p of} 000h to FFFFh is provided.

However, in the configuration of FIG. 19, the data stored in the designated buffer RAM is converted into one RO.
Since the data is written in M, it is necessary to repeat the same work four times while changing the setting of SW in order to write data in all four ROMs.

FIG. 24 is a second embodiment of the second invention of the present invention, which provides a technique for solving the above problems and writing data in four ROMs at a time. In FIG. 24, 201 is a personal computer for controlling data writing, 3
01 is an RS-232C port, 302 is a level converting unit from 12 volt system to 5 volt system, 303 is an oscillator, 304 is an oscillator, 305 is an OR circuit, 306 is a CPU, 307 is an edge detecting unit, 308 is SW, 309 is It is a pull-up resistor 1. Reference numeral 310a is a decoder 1, 310b is a decoder 2, 310c is a decoder 3, and 310a to 310c are used as address decoders in the input / output space. 311 is an R register, 312 is a W register, 313
Is an R / W register. Also, 314a is the decoder 4,
314b is a decoder 5 and 314a and 314b are used as address decoders in the memory space. Three
Reference numeral 15 is an address switching unit that switches the addresses of a plurality (4 in this case) of RAMs, 316b is a RAMCS separation unit that separates CSs of a plurality (4 in this case) of RAMs, and 317 stores a write program. The program ROMs 318a to 318d are buffer RAs, respectively.
M0, buffer RAM1, buffer RAM2, and buffer RAM3, 401a are target ROM0, and 401d is target ROM3. Incidentally, in FIG.
A ROM writer is configured by the elements with reference numerals of the series. Also, the ROM writer's function is
Although there is a data transfer function to the M writer, a write function to the target ROM, a verify function, a checksum function, and a load function from the target ROM to the personal computer, the present invention has a data transfer function from the personal computer to the ROM writer and the target ROM. Since it is related to the write function of, the configuration for realizing the function following the verify function is omitted in the drawing.

The feature of the configuration of FIG. 24 is that it has four buffer RAs.
After distributing the data to M and storing it, each buffer R
The point is that AM data is written to four separate ROMs.
Therefore, in the configuration of FIG. 24, the RAM address switching unit (FIG. 2) having the same configuration as that applied to the configuration of FIG.
2), the decoder 5 (FIG. 21), and a RAMCS separation unit different from that applied in FIG.
An S separation unit is provided.

FIG. 25 shows an example of the RAMCS separating section in the second embodiment of the second invention of the present invention. In FIG. 25, one of 316b-1 is an inverting input AN
The D circuit 316b-2 is a 4:16 DEC 316a-2 surrounded by a thin ruled line in FIG.
6a-3, 316a-4, 316a-5, 316a-6
316b-3 to 316b-12
Is D-FF, 316b-13 to 316b-25 is AN
The D circuit 316b-26 is a decoder 316b-2 for decoding the count value 3FFFh of the address counter.
7 is an AND circuit, one of which is an inverting input, 316b
-28 to 316b-31 are JK-flip-flops (hereinafter abbreviated as JK-FF), 316b-32 to 316b-35 are OR circuits, 316b-36 to 316.
b-39 is an AND circuit. Then, the AND circuit 31
6b-22 to 316b-25 to 4 puffer RAM
Is output, and the AND circuits 316b-36 to 316b-39 output signals P0CS, P1CS, P2CS, and P3CS to the ROMCS separation unit described later.

FIG. 26 shows an example of the ROMCS separation section in the second embodiment of the second invention of the present invention. In FIG. 26, 319-1 to 319-4 are AND circuits and 319.
-5 is an AND circuit, one of which is an inverting input.
The P0CS, P1CS, P2CS, and P3C are connected to one input terminals of the AND circuits 319-1 to 319-4.
S is supplied to the AND circuits 319-1 to 319-4.
AND of the inverted signal of the SW state and the signal indicating the state of the W register is supplied to the other input terminal of the
CS for selecting four target ROMs is output from the ND circuit.

First, when SW is "H", the circuit 316
When b-2 is enabled, the patterns of A0, A1, A14, A15 1, 0 of the address output by the CPU are "0000", "0101", "1010", "111".
When it is "1", "1" is output to the OR circuit 316b-32, and "0001", "0110", "1011", "1" are output.
When it is 100, "1" is output to the OR circuit 316b-33, and "0010", "0111", "1000",
When "1101", "1" is output to the OR circuit 316b-34, and "0011", "0100", "100" is output.
When it is "1" or "1110", "1" is output to the OR circuit 316b-35. On the other hand, when SW is "H", CP
Decoder 5 outputs "1" for all addresses output by U
Is supplied, when the W register is "L", that is, R
OR circuit 316 when access to AM is specified
The outputs of b-32 to 316b-35 are AND circuits 316.
b-22 to 316b-25 can be passed. That is, the operation of the configuration of FIG. 25 at this time is the same as that of the configuration of FIG.
The operation is exactly the same as when 3 is "1". Therefore, "0" and "1" of A0, A1, A14, A15 of the address
The pattern according to the combination of "0000" and "010"
In the case of 1 ”,“ 1010 ”,“ 1111 ”, CS is output from the AND circuit 316b-22 to RAM0.At this time, the RAM address switching unit supplies A14 to the RAM as A0 of the addresses output by the CPU. And CP
Of the addresses output by U, A15 is supplied as A1 of RAM. That is, when "0000", the data is transferred to the address where A1 and A0 of RAM0 are "00", and when "0101", A1 and A0 of RAM0 are "0".
Data is transferred to the address that becomes 1 "and" 1010 "
In the case of, data is transferred to the address where A1 and A0 of RAM0 are "10", and in the case of "1111", RAM0 is
The data is transferred to the address where A1 and A0 of "11". Specifically, the data at address 0000h is at address 0 of RAM0, and the data at address 4001h is in RAM.
0 at address 1, 8002h data at RAM0 address 2, C003h data at RAM0 address 3, 000
The data of 4 is in the address 4 of RAM0, the data of 4005 is the address 5 of RAM0, and the data of BFFE is 6 in the RAM0.
Address, the data of C007 is at address 7 of RAM0, ...
The data of FFFh is transferred to the address 3FFFh of RAM0. The address of the data thus transferred to the RAM0 is R in the "corresponding ROM column" in FIG.
It matches the address described as OM0. That is, the data to be read from the ROM0 in the configuration of FIG. 16 is transferred to the RAM0 in the configuration of FIG. Similarly, the pattern of the combination of the addresses A15, A14, A1, and A0 of "0" and "1" is "000".
In the case of 1 ”,“ 0110 ”,“ 1011 ”, and“ 1100 ”, the data to be read from the ROM1 in the configuration of FIG. 16 is transferred to the RAM1 in the configuration of FIG. 24, and the addresses A15, A14, A1, and A0 are“ 0 ”. "," 1 "
The pattern by the combination of "0010" and "011
In the case of 1 ”,“ 1000 ”, and“ 1101 ”, the data to be read from the ROM 2 in the configuration of FIG.
Is transferred to RAM2 and the address A1
5, the patterns of combinations of "0" and "1" of A14, A1, and A0 are "0011", "0100", and "100".
When 1 ”and“ 1110 ”, R in the configuration of FIG.
The data to be read from the OM3 is transferred to the RAM3 in the configuration of FIG.

Then, while SW is "1", D-FF
316b-3 and D-FF 316b-4 and AND circuit 3
Differentiating circuit composed of 16b-13, D-FF316b-5
And D-FF 316b-6 and AND circuit 316b-18
Differentiating circuit consisting of D-FF316b-7 and D-FF3
16b-8 and a differential circuit composed of an AND circuit 316b-19, D-FF316b-9 and D-FF316b-10.
And a differentiation circuit composed of an AND circuit 316b-20, D-
FF316b-11, D-FF316b-12 and AN
The output of the differentiation circuit composed of the D circuit 316b-21 is "L".
Since it is maintained at JK-FF316b-28 to 3
Q output of 16b-31 is kept at "L", P0C
S to P3CS are also fixed to "L". As shown in FIG. 26, the target ROM CS is P0CS to P3C.
It is output when S is "H", so while SW is "1" and data is being transferred to the buffer RAM, the target RO
CS is not output to M.

Here, when SW is set to "0", the configuration of FIG. 24 becomes a data write mode to the target ROM. At this time, the circuit 316b-2 in FIG.
Is disabled and the address from the decoder 5
"1" obtained by decoding the range of 0000h to 3FFFh of the output of the counter is supplied. Therefore,
CS is issued to the RAM when the address is up to 3FFFh and the W register is "L". At this time, it is the portion excluding the AND circuit 316b-1 and the circuit 316b-2 of FIG. 25 that determines which RAM the CS is output to, and which ROM the CS is output is determined. Figure 25
26 and the ROMCS separation unit of FIG. 26.

FIG. 27 is a time chart of the configuration of FIG. 25, showing the procedure for writing data from the buffer RAM to the target ROM. When SW is set to "L", the falling edge of D-FF316b-3 and D-FF
The differential circuit composed of 316b-4 and the AND circuit 316b-13 detects and the AND circuit 316b-13 is detected in FIG.
The pulse shown in “316b-13 output” of is output. Therefore, the Q output of the JK-FF316b-28 is fixed at "H". At this time, since the AND circuits 316b-27 keep "L" until the count value of the address counter reaches 3FFFh, the Q outputs of the JK-FFs 316b-29 to 316b-31 are fixed at "L". Up to That is, during this period, only RAM0 can be accessed, and RAM1 to RAM3 cannot be accessed. On the other hand, in the meantime, the AND of the XMREQ (active “L”) which permits access to the memory space from the decoder 5 and the “H” which is obtained by decoding 3FFFh from the addresses 000h.
Is output, the output becomes like "decoder 5 output" in FIG. The AND of the output of the decoder 5 and the inverted signal of the state of the W register and the output of the OR circuit 316b-32 are used as CS of RAM0, "RAM0 of FIG.
A signal such as "CS" is provided. During this period, the other buffer RAMs cannot be accessed, so CS is not output from RAM1 to RAM3 (in FIG. 27,
Only RAM0CS and RAM1CS are shown). Since the address counters A1 and A0 of the RAM0 are supplied to the address counters A1 and A0, the data at the address 0000h of the RAM0 is first read by the "L" pulse of XRD. On the other hand, JK-FF
By ANDing the Q output of 316b-28 and the output of the decoder 5, P0CS is output as shown in FIG. 27, and JK-FF3
Q outputs 16b-29 to 316b-31 and decoder 5
AND with the output of P1CS to P3
CS is fixed to "L". The CS of ROM0 is generated by the P0CS and the AND of the inverted signal of the SW state and the signal of the W register state. At this time, the pulse of XWR "L" is sent to the address 000h of ROM0 and RA
The data read from the address 0000h of M0 is written. Similarly, the operation of sequentially accessing the addresses of the RAM0 to read the data and writing the data to the same address of the ROM0 that the data is read is repeated, and the operations up to the address 3FFFh are completed. With this, RAM
Writing of all the data transferred to 0 to ROM0 is completed.

When the address is 3FFFh, 3FFF
"H" is output from the decoder 316b-26 that decodes h, and an "H" pulse such as "316b-27" in FIG. 27 is generated by ANDing this with the "L" pulse of XWR. To be done. At this time, JK-FF
Since the Q output of 316b-28 and ROM0CS are both "H", the NAND circuit 316b-14 becomes "L" only when the output of the AND circuit 316b-27 is "H". This fall is caused by D-FF316b-5 and D-FF316.
The differential circuit configured by b-6 and the AND circuit 316b-18 detects and generates the "H" pulse indicated by "316b-18" in FIG. This is JK-FF31
Since it is supplied to the K terminal of 6b-28, the JK-FF3
The Q output of 16b-28 is fixed at "L" and is fixed, and at the same time, the "H" pulse shown in "316b-18" of FIG. 27 is supplied to the J terminal of JK-FF316b-29. The Q output of -FF316b-29 is fixed to "H". Therefore, access to RAM0 and ROM0 is prohibited, and instead, access to RAM1 and ROM1 becomes possible. At this time, RAM2, RAM3, RO
Since access to M2 and ROM3 is still prohibited, only RAM1 and ROM1 can be accessed. Then, the output of the AND circuit 316b-1 and the JK-FF31
6b-29 is ANDed to generate CS of RAM1, and the output of the decoder 5 is ANDed with JK-FF316b-29.
P1CS is generated at. This P1CS and AND of the inverted signal of the SW state and the state of the W register R
ROM1CS which is CS for OM1 is generated.
At this time, the operation of reading from the RAM1 and writing to the ROM1 is the same as the above-described operation of writing from the RAM0 to the ROM0. In this way, 0000 of RAM1
Data from addresses h to 3FFF are written in the ROM 1.

In FIG. 27, signals corresponding to the following description are not displayed, but similarly to the above, the 3FFF of the ROM 1 is used.
When the data is written in the address h, the NAND circuit 31
6b-15 outputs "L" pulse, resulting in JK
-JK-when FF316b-29 is reset
FF316b-30 is set, RAM2 and ROM2
Only RAM can be accessed and RAM2
Data is written to OM2. And 3 of ROM2
When the data is written in the address FFFh, the NAND circuit 316b-16 outputs the "L" pulse, so that the JK-FF316b-30 is reset and the JK-FF316b-31 is set, and the RAM3 and the ROM3 are set. Only the RAM can be accessed.
Data is written from 3 to ROM3. Furthermore, ROM
When data is written to the 3rd 3FFFh address, NA
As a result of the "L" pulse being output from the ND circuit 316b-17, the JK-FF 316b-31 is reset,
Access to all RAMs and ROMs is prohibited, and writing of data from all four RAMs to all four ROMs is completed.

Therefore, with the configuration of FIG. 24 to which the RAM address switching unit of FIG. 22, the RAMCS separating unit of FIG. 25, and the ROMCS separating unit of FIG. 26 are applied, the order of reading from the four ROMs in the configuration of FIG. 16 matches. Data can be transferred to the four RAMs in order, and data can be written from the four RAMs to four different ROMs.

Thus, in addition to the advantage that the designer does not need to be aware of the order of writing the data to the target ROM, the work of performing the write operation while replacing the target ROM is not required, and it is possible to perform four operations at a time. Data can be written to the target ROM.

Here, for the sake of concrete description,
The number of target RAMs and the number of target ROMs are
However, the technique of the present invention is not limited to the buffer.
Limit the number of RAM and target ROM to four each
Not a thing. Generally two ^pBuffer RAM
Transfer the data^pFrom the buffer RAM of 2^pThe target
To write data to the ROM, please follow the steps below.
I just need. First, in the RAM address switching unit, transfer
In the mode, the MSB side p of the address specified by the CPU
Write the bit as p-bit on the LSB side of RAM
In the mode, the LSB side p of the address specified by the CPU
Give bits as p bits in LSB side of RAM
I do. Next, in the RAMCS separation unit, the transfer mode
In case of, the MSB side p bit of the address specified by the CPU
And the combination of p-bit "L" and "H" on the LSB side
2^pIt is possible to alternately access the buffer RAM of
2 in write mode^pOne of the buffer RAMs
Only the buffer RAM of is accessible. For this reason
Instead of the circuit 316b-2 in FIG.
MSB side p bit and LSB side p of the address specified by U
2 from the combination of bit "L" and "H"^pOn the street
A circuit for outputting "H" is applied, and (2²+
Differentiation circuit of 1) and 2²When writing by applying JK-FF
Circuit that selects the buffer RAM that enables access to the memory
To (2^p+1) differentiator and 2^pJK-FF of Figure 2
In the same manner as in the configuration of No. 5, connecting in a chain,
Instead of 316b-26, 1 / 2p of FFFFh
Apply a decoder to decode. Also, the decoder 5 is 0
A terminal that decodes and outputs FFFFh from 000h
And 0000h to 1/2 of FFFFh^pDecode
Be equipped with a terminal to output.

In the above, R is read in the same order as the desired read order.
The circuit for writing data to the OM has been described. However, these circuits can be realized only after a considerable modification of the standard ROM writer.

A technique for realizing the same function by a small-scale modification will be described below. It has the same function as a ROM writer that has been modified in terms of hardware
This is realized by changing the program stored in M.

FIG. 28 shows the third embodiment of the second invention of the present invention. In FIG. 28, 201 is a personal computer for controlling data writing, 301 is an RS-232C port,
302 is a level conversion unit from 12 volt system to 5 volt system, 303 is an SIO receiving unit, 304 is an oscillator, 305 is an OR circuit, 306 is a CPU, 307 is an edge detection unit, 3
08a to 308c are SW1, SW2, and SW, respectively
3, 309a to 309c are a pull-up resistor 1, a pull-up resistor 2 and a pull-up resistor 3, respectively.
310a is the decoder 1, 310b is the decoder 2, 310
Reference numeral c is a decoder 3, and 310a to 310c are used as address decoders of the input / output space. 311 is an R register, 312 is a W register, and 313 is an R / W register. Further, 314a is used as a decoder 4, 314b is used as a decoder 5, and 314a and 314b are used as address decoders in a memory space. Reference numeral 317 is a program ROM that stores a write program, 318 is a buffer RAM that temporarily stores write data, and 401 is a target ROM to which data is written. still,
In FIG. 28, the ROM writer is configured by the elements with the numbers in the 300s. The functions of the ROM writer include a data transfer function from the personal computer to the ROM writer, a write function to the target ROM, a verify function, a checksum function, and a load function from the target ROM to the personal computer. Since it relates to the data transfer function to the ROM writer and the write function to the target ROM, the configuration for realizing the function below the verify function is omitted.

The configuration of FIG. 28 is characterized in that the conventional ROM writer has one SW (controls an interrupt to the CPU to select a transfer mode and a write mode), but has three SWs. The transfer mode and the write mode (performed by SW3) and the address of the data to be written in the target ROM among the data stored in the buffer RAM (performed by SW1 and SW2). The point is that the program stored in the ROM is changed to realize the same function as the configuration of FIG.

29 to 40 are ROM writing flowcharts in the third embodiment of the second invention of the present invention. Hereinafter, the write operation to the ROM will be described in the order of reference numerals in FIGS. A1. The CPU confirms the occurrence of the SW interrupt. If the SW interrupt has not occurred (No), it returns to the original state and waits for the occurrence of the SW interrupt. A2. When it is determined in step A1 that the SW interrupt has occurred (Yes), it is determined whether SW3 is "L". If SW3 is not "L" (No), the mode is not the write mode, and therefore the process returns to A1 to wait for the SW interrupt. A3. When it is determined that SW3 is "L" in step A2 (Yes), the states of SW1 and SW2 are read. A4. It is determined whether the states of SW1 and SW2 are "00". A5. If it is determined to be “00” (YES),
0000h is set in the RAM address RAMAD. A6. RAMAD address of buffer RAM (currently 0000
Read the data stored in address h). A7. “H” in DX bit of I / O space of WR register
To enable the ROM. A8. Address RA set in buffer RAM
Read the status of A15 and A14 of MAD (0000h now). A9. It is determined whether or not the RAM addresses A15 and A14 are "00". A10. RAM address A1 in step A9
When it is determined that 5 and A14 are "00" (Yes)
The target ROM with the data read in step A6.
Write in. Since the address of the ROM in this case is the first line of the "converted address" in FIG.
It is 0h. That is, the data is written in the RAMAD address. A11. "L" is written in the DX bit of the I / O space of the WR register to enable the RAM. A12. It is determined whether or not the RAM address RAMAD reaches 3FFCh. A13. RAMAD is 3 FFC in step A12
If it is determined that the number has not reached h (No), the RAM
The value obtained by adding 4 to AD is substituted, and the process returns to step A6.

What is done in steps A6 to A13 is that the address in the table of FIG. 17 where the data to be written in the ROM0 between the addresses 0000h and 3FFFh is stored (here, the address 0000h is the 4th address). The data of every address is written in the ROM0. A14. RAMAD is 3 FFC in step A12
If it is determined that the value has reached h (Yes), RAMAD
The value obtained by adding 5 to is substituted, and the process returns to step A6.

This corresponds to that in FIG. 17, the address storing the data to be written in the ROM0 is the address 4001h next to the address 3FFCh. Then, when it reaches A9, the RAM address A1
5 and A14 are judged not to be "00", so A1
Jump to 5. A15. RAM addresses A15 and A14 are "01"
Or not. A16. If it is determined to be "01" in step A15 (Yes), the data stored in the RAMAD address is written in the ROM0. In this case, the ROM address to be written is 000000000000.
Since it is the address 01, that is, the address (0001h-4000h), the data is written in (RAMAD-4000h). A17. "L" is written in the DX bit of the I / O space of the WR register to enable the RAM. A18. It is determined whether RAMAD has reached 7FFDh. A19. RAMAD is 7 FFD in step A18
If it is determined that the number has not reached h (No), the RAM
The value obtained by adding 4 to AD is substituted, and the process returns to step A6.

What has been done in steps A6 to A9 and steps A15 to A19 is that R from address 4001h to address 7FFDh in FIG.
The data to be written in OM0 is written in ROM0. A20. RAMAD is 7 FFD in step A18
If it is determined that the address has been reached at address h (Yes), RAM
The value obtained by adding 5 to AD is substituted, and the process returns to step A6.

This is because the data to be written in the ROM0 is stored in the address 8002h next to the address 7FFDh. In this case, since the RAM addresses A15 and A14 are "10", the process jumps from step A9 to step A15, and then step A1.
Jump from step 5 to step A21. A21. RAM addresses A15 and A14 are "10"
Or not. A22. If it is determined to be "01" in step A15 (Yes), the data stored in the RAMAD address is written in the ROM0. In the present case, RO
The address to write to M is 0000000000001
0, that is, (80002h-8000h),
Write to address (RAMAD-8000h). A23. "L" is written in the DX bit of the I / O space of the WR register to enable the RAM. A24. It is determined whether RAMAD has reached BFFEh. A25. RAMAD is BFFE in step A18
If it is determined that the number has not reached h (No), the RAM
The value obtained by adding 4 to AD is substituted, and the process returns to step A6.

The steps A6 to A9 and the step A15J, the steps A21 to A25, are the same as those from the address 8002h to BFFEh in FIG.
The data to be written in ROM0 up to the address is stored in ROM
Write to 0. A26. RAMAD is BFFE in step A24
If it is determined that the address has been reached at address h (Yes), RAM
The value obtained by adding 5 to AD is substituted, and the process returns to step A6.

This is because the data to be written in the ROM0 is stored in the address C003h next to the address BFFEh. In this case, since the RAM addresses A15 and A14 are "11", the process jumps from step A9 to step A15, and then step A15.
To step A21, and from step 21 to step A27. Here, since it is obvious that the RAM addresses A15 and A14 are "11", the "11" test is not performed. A27. The data stored in the RAMAD address is RO
Write to M0. In the present case, the address to be written in the ROM is 00000000000011, that is, (C
003h-C000h), so (RAMAD
-Write at address C000h). A28. "L" is written in the DX bit of the I / O space of the WR register to enable the RAM. A29. It is determined whether RAMAD has reached FFFFh. A30. RAMAD is FFFF in step A18
If it is determined that the number has not reached h (No), the RAM
The value obtained by adding 4 to AD is substituted, and the process returns to step A6.

What is done in steps A6 to A9, step A15, step A21 and steps A27 to A30 is to write the data to be written in the ROM0 at the address C003h and thereafter in FIG. Then, in step A29, R
When it is determined that AMAD has reached FFFFh (Y
In es), all the data to be written in the ROM0 has been written, so the writing in the ROM0 is completed.

Now, in step A4, SW1 and SW
When it is determined that the state of 2 is not "00" (No), the process jumps to step A31. After that, ROM1
Since this is a routine for writing data from the ROM to the ROM 3 and is similar to the above routine, the explanation for each step will be omitted and only the outline will be described. A31. It is determined whether the states of SW1 and SW2 are "01".

When it is determined in step A31 that the states of SW1 and SW2 are "01", writing to ROM1 is performed. In the case of ROM1, 0001
Since the first data is stored in address h, RAMA
0001h is set in D and writing is started. Then, in the range where the RAM addresses A15 and A14 are “00”, the address is 0001h at the head and every 4th address is 3FFD.
Write to address, and if RAM addresses A15 and A14 are in the range of "01", write every 4th address up to 7FFEh beginning with address 4002h, and RAM address A15
And in the range of A14 is "10", 4 at the address 8003h
Write up to BFFFh every other address, and C000h when RAM addresses A15 and A14 are "11".
Writing up to the address FFFCh every 4th address starting from the address, the writing to the ROM 1 is completed. Up to this point, steps A31 to A57 are performed. During this time, the count value of the address counter and the ROM
The address conversion is performed according to the same rules as the conversion in ROM0. A58. It is determined whether the states of SW1 and SW2 are "10".

When it is determined in step A58 that the states of SW1 and SW2 are "10", writing to ROM2 is performed. In the case of ROM2, 0002
Since the first data is stored in address h, RAMA
0002h is set in D and writing is started. Then, in the range where the RAM addresses A15 and A14 are “00”, the address is 0002h, and every 4th address is 3FFE.
Write to the address, and if the RAM addresses A15 and A14 are in the range of "01", write to the address 4003h at every fourth address up to the address 7FFFh and write to the RAM address A15.
And A14 is in the range of "10", 4 at the address 8000h
Write up to BFFCh every other address, and if the RAM addresses A15 and A14 are "11", C001h
Writing to the FFFDh address every 4th address starting from the address, the writing to the ROM 2 is completed. Up to this point, steps A58 to A84 are performed. During this time, the count value of the address counter and the ROM
The address conversion is performed according to the same rules as the conversion in ROM0. A85. It is determined whether the states of SW1 and SW2 are "11".

When it is determined in step A84 that the states of SW1 and SW2 are "11", writing to the ROM3 is performed. In the case of ROM3, 0003
Since the first data is stored in address h, RAMA
0003h is set in D and writing is started. Then, in the range where the RAM addresses A15 and A14 are "00", the address is 0003h and the third address is 3FFF.
Write to the address, and if the RAM addresses A15 and A14 are in the range of "01", write 4000h address to every 4th address up to 7FFCh address, and RAM address A15.
And when A14 is in the range of "10", 4 at the address 8001h
Write up to BFFDh every other address, and if the RAM addresses A15 and A14 are "11", C002h
Writing up to FFFEh every 4th address starting from the address, the writing to the ROM 3 is completed. Up to this point, steps A85 to A110 are performed. During this time, the count value of the address counter and the ROM
The address conversion is performed according to the same rules as the conversion in ROM0.

Now, all the data is written from ROM0 to ROM3. That is, in the configuration of FIG. 27, by writing the program described in FIGS. 29 to 40 in the program ROM, it is possible to write data separately from ROM0 to ROM3 while changing the settings of SW1 and SW2. . As a result, the burden on the designer can be reduced, human error can be avoided, and the hardware modification of the standard ROM writer can be made small.

To summarize the above operation, "in the transfer mode, data is stored in the address of the random access memory designated by the address output by the CPU, and in the write mode, the second and third setting states are set. First, the address of the random access memory corresponding to is specified, the data stored at the specified address of the random access memory is read, and the read data is written to the specified address of the read-only memory. , Read from the random access memory and write to the read-only memory while advancing the address by 4 addresses until the specified address reaches the specified value. When the specified address reaches the specified value, the start point address is 5 addresses. Proceed,
Random access while reading data from the specified address of the random access memory, writing the read data to the specified address of the read-only memory, and advancing the specified address by 4 addresses until the specified address reaches the next predetermined value.・ Reading from the memory and writing to the read-only memory, advance the specified address by 5 when the specified address reaches the next specified value, and read the data from the specified address of the random access memory and read only The operation of writing the read data to the specified address of the memory is performed until the specified address reaches the final address, and when the specified address reaches the final address, the read-only memory that is the write target is replaced, and Change the three setting states to different states,
The address of the random access memory corresponding to the set state is first set, and the above is repeated thereafter. "

In the above, the buffer RAM
The specific example in which the data transferred to the target RAM are alternately written to four different target ROMs depending on the combination of the two setting states has been described. However, in general, the data transferred to the buffer RAM can be written as follows. The target ROM of ^p can be written alternately. That is, in the transfer mode, the data is stored in the address of the random access memory specified by the address output by the CPU, and in the write mode, the data of the random access memory corresponding to one of the combinations of the setting states of p is stored. By first designating an address, the data stored at the designated address of the random access memory is read and the read data is written at the designated address of the read-only memory, and the designated address reaches a predetermined value. While advancing the address by 2 ^p each, reading from the random access memory and writing to the read-only memory are performed, and when the specified address reaches a predetermined value, the specified address is set to (2 ^p +1) Advanced address advances the random access memory the data read by reading the data at the specified address of the read-only memory from the designated address of the write, the designated address is by 2 ^p address specified address until a next predetermined value However, reading from the random access memory and writing to the read-only memory are performed, and when the specified address reaches the next predetermined value, the specified address is advanced to the address (2 ^p +1) and the random access
The operation of reading the data from the specified address of the memory and writing the read data to the specified address of the read-only memory is performed until the specified address reaches the final address, and when the specified address reaches the final address, it becomes the write target. Replace the read-only memory, change the combination of the setting states of p to a different combination, set the address of the random access memory corresponding to the combination of the setting states first, and repeat the above. Good.

FIG. 41 shows the fourth embodiment of the second invention of the present invention. In FIG. 41, 201 is a personal computer for controlling data writing, 301 is an RS-232C port,
302 is a level conversion unit from 12 volt system to 5 volt system, 303 is an SIO receiving unit, 304 is an oscillator, 305 is an OR circuit, 306 is a CPU, 307 is an edge detection unit, 3
Reference numeral 08 is SW and 309 is a pull-up resistor. 310
a is a decoder 1, 310b is a decoder 2, 310c is a decoder 3, and 310a to 310c are used as address decoders of an input / output space. 311 is an R register, 312 is a W register, and 313 is an R / W register. Further, 314a is a decoder 4, 314b is a decoder 5, 314a and 314b are addresses of a memory space.
It is used as a decoder. Reference numeral 317 is a program ROM that stores a write program, 318 is a buffer RAM that temporarily stores write data, 320 is an OR circuit, and 401a and 401d are target ROM1 and target ROM3 to which data is to be written, respectively.
Note that, in FIG. 40, the ROM writer is configured by the elements with reference numerals in the 300s. The functions of the ROM writer include a data transfer function from the personal computer to the ROM writer, a write function to the target ROM, a verify function, a checksum function, and a load function from the target ROM to the personal computer. ROM
Since it relates to the data transfer function to the writer and the write function to the target ROM, the configuration for realizing the function below the verify function is omitted in the figure.

The feature of the configuration of FIG. 41 is that the configuration of FIG.
Data is stored in the buffer RAM according to the combination of the RAM addresses A15, A14, A1, and A0, while one SW is provided to select the transfer mode and the write mode, while three W are provided. Among them, the address of the data to be written in the target ROM can be specified, and the program stored in the program ROM is changed to realize the same function as the configuration of FIG. For this purpose, the output of the W register is set to 4 bits so that the CSs of the four ROMs can be specified, and the buffer RA
O of the four outputs of the W register to specify the CS of M
It is configured to take R.

42 to 50 are flow charts of ROM writing in the third embodiment of the second invention of the present invention. 42 to 50 are pure ROMs
The write operation to the memory will be described. B1. Determine whether a SW interrupt has occurred. When it is determined that the SW interrupt has not occurred (No), the process returns to the original state and waits for the SW interrupt. B2. When it is determined in step 1 that the SW interrupt has occurred (Yes), 00 is set in the address RAMAD of the RAM.
Set 00h. B3. Read the data stored in the RAMAD address of the buffer RAM. B4. RAM addresses A15, A14, A1, A0
Read the state of. B5. RAM addresses A15, A14, A1, A0
Is "0000" or not. B6. RAM addresses A15, A14, A1, A0
When it is determined that is “0000” (Yes),
As described in the second embodiment of the second invention of the present invention, since the writing to the ROM0 is designated, "H" is written to the D0 bit of the I / O space of the WR register, and the ROM is written.
Enable 0. B7. The data stored in the RAMAD address is stored in the ROM
Write to 0. The address to be written is the address converted according to FIG. 17, which is RAMAD in this case. B8. "L" in D0 bit of I / O space of WR register
To enable the RAM. B9. The value obtained by adding 1 to RAMAD is substituted, and the process returns to step B3.

Then, the process proceeds to step B3, step B4 and step B5. At this time, A15, A14, A1,
Since the state of A0 is "0001", B5 to B1
Jump to B26 via 0, B15, B20, B
In step 26, it is determined that the value is "0001", and the process proceeds to B27. B27. RAM addresses A15, A14, A1, A
When it is determined that 0 is “0001” (Yes), since the writing to the ROM 1 is designated as described in the second embodiment of the second aspect of the invention, the I / O space of the WR register is Write "H" to D1 bit
Enable OM1. B28. The data stored in the RAMAD address is RO
Write to M1. In this case, the ROM address is RAM
It is AD. B29. "L" is written in the D1 bit of the I / O space of the WR register to enable the RAM. B30. The value obtained by adding 1 to RAMAD is substituted, and the process returns to step B3.

Then, the process proceeds to step B3, step B4 and step B5. At this time, A15, A14, A1,
Since the state of A0 is "0010", B5 to B1
0, B15, B20, B26, B31, B36, B41
Jump to B46 via B, and at B46 "0010"
Then, the process proceeds to B47. B47. RAM addresses A15, A14, A1, A
When it is determined that 0 is “0010” (Yes), since the writing to the ROM 2 is designated as described in the second embodiment of the second invention of the present invention, the I / O space of the WR register is Write "H" to D2 bit and
Enable OM2. B48. The data stored in the RAMAD address is RO
Write to RAMAD address of M2. B49. "L" is written in the D2 bit of the I / O space of the WR register to enable the RAM. B50. The value obtained by adding 1 to RAMAD is substituted, and the process returns to step B3.

Then, the process proceeds to step B3, step B4 and step B5. At this time, A15, A14, A1,
Since the state of A0 is "0011", B5 to B1
0, B15, B20, B26, B31, B36, B4
1, B46, B51, B56, B61 to B66
Jump to B66, and at B66, it is judged to be "0011", and the process proceeds to B66. B66. RAM addresses A15, A14, A1, A
When it is determined that 0 is “0011” (Yes), since the writing to the ROM 3 is designated as described in the second embodiment of the second aspect of the invention, the I / O space of the WR register is Write "H" to D3 bit, and
Enable OM3. B67. "H" is written in the D3 bit of the I / O space of the WR register to enable the ROM3. B68. The data stored in the RAMAD address is RO
Write to RAMAD address of M3. B69. "L" is written in the D3 bit of the I / O space of the WR register to enable the RAM. B70. The value 0004h obtained by adding 1 to RAMAD is substituted, and the process returns to step B3.

Then, the process proceeds to step B3, step B4 and step B5. At this time, A15, A14, A1,
Since the state of A0 is "0000", after the determination of B5, the process proceeds to B7 via step B6. B7. The data stored in the RAM at address 0004h is written to the RAMAD address of the ROM1.

Then, the process proceeds to step B8 and step B9, and in step B9, the value 00 obtained by adding 1 to RAMAD is set.
Substitute 05h and return to step B3. At this time A1
Since the states of 5, A14, A1 and A0 are "0001", the process jumps to step B26 and 00 of RAM
The data at address 05h is written in ROM1.

Similarly, the data at the address 0006h in the RAM is stored in the ROM 2, and the data at the address 0007h in the ROM 3 is stored.
The operation of writing to is performed. That is, according to the flowcharts of FIGS. 42 to 50, data is written from the RAM to the target ROM0 to the target ROM3 in the order of the count values of the address counters in the table of FIG.

All data is now written from ROM0 to ROM3. That is, with the configuration of FIG. 41, by writing the program described in FIGS. 42 to 50 in the program ROM, data can be written separately in each of ROM0 to ROM3. As a result, the burden on the designer can be reduced, human error can be avoided, and it is not necessary to operate the SW or replace the ROM during the writing to the ROM, and the standard ROM writer can be used. You can make small-scale hardware modifications.

To summarize the above, "in the transfer mode, the data to be transferred is stored at the address of the random access memory specified by the address output by the CPU, and in the write mode, the random access specified by the CPU is stored.・ Set the memory address to the first address,
The data stored at the address of the random access memory is read, the combination of MSB2 bit and LSB2 bit of "L" and "H" of the designated address is tested, and the read corresponding to the tested combination. The read data is written to the dedicated memory, the address of the designated random access memory is advanced to the first address, the data stored at that address of the random access memory is read, and the MSB2 bit and LS of the designated address are read.
B2 bit "L", "H" combination is tested, the read data is written to the read-only memory corresponding to the tested combination, and specified until the final address of the random access memory is reached. The address of the access memory is advanced to the first address, the data stored in the address of the random access memory is read, and the combination of MSB2 bit and LSB2 bit of "L" and "H" of the specified address is tested. The read data is written in the read-only memory corresponding to the verified combination. "

Therefore, generally, in order to continuously write the data transferred to the buffer RAM to the 2 ^p target ROM without duplication, in the transfer mode, the random access memory specified by the address output by the CPU is used. The data transferred to the address is stored, and in the write mode, the address of the random access memory designated by the CPU is set to the first address, and the data stored at the address of the random access memory is set. Random access for reading and testing the combination of MSBp bit and LSBp bit “L” and “H” of the designated address, writing the read data to the read-only memory corresponding to the tested combination, and designating The memory address is advanced to the first address and the address of the random access memory is updated. It reads the data that is, of MSBp bit and LSBp bit of the designated address "L",
The combination of "H" is verified, the read data is written in the read-only memory corresponding to the verified combination, and the address of the random access memory which is specified until the final address of the random access memory is reached is set to 1 The address is advanced, the data stored in the address of the random access memory is read, and the MSBp bit and the LSBp bit of the designated address are “L” and “H”.
The above combination may be tested and the read data may be written in the read-only memory corresponding to the tested combination.

[0119]

As described in detail above, according to the present invention, it is possible to match the read speed of the ROM with the transmission speed even if a ROM having a lower speed than the transmission speed is used.
Further, it becomes possible to solve the problem that the order of writing to the ROM is restricted in order to achieve the above matching by modifying the ROM writer in terms of hardware or software.

The former contributes to the economicization of the test system of the transmission system, for example, and the latter contributes to the economicization of the test system and at the same time, to reduce the load on the designer in preparing the test data and avoid human error.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the first invention.

FIG. 2 is a time chart of the first embodiment of the first invention.

FIG. 3 is an example of an output enable generation unit in the first embodiment of the first invention.

FIG. 4 is a second embodiment of the first invention.

FIG. 5 is an example of an output enable generation unit in the second embodiment of the first invention.

FIG. 6 shows SW1 in the second embodiment of the first invention,
Correspondence between SW2 settings and the number of ROMs used

FIG. 7 is an example (1) of an address switching unit in the second embodiment of the first invention.

FIG. 8 is an example (No. 2) of the address switching unit in the second embodiment of the first invention.

FIG. 9 is an example (3) of the address switching unit in the second embodiment of the first invention.

FIG. 10 is an example (No. 4) of the address switching unit in the second embodiment of the first invention.

FIG. 11 is an example (5) of the address switching unit in the second embodiment of the first invention.

FIG. 12 is an example (6) of the address switching unit in the second embodiment of the first invention.

FIG. 13 is an example (No. 7) of the address switching unit in the second embodiment of the first invention.

FIG. 14 is an example (No. 8) of the address switching unit in the second embodiment of the first invention.

FIG. 15 is a table for explaining the operation of the address switching unit in the second embodiment of the first invention.

FIG. 16 shows a third embodiment of the first invention.

FIG. 17 is a ROM in the third embodiment of the first invention.
The figure explaining the determination method of an access address.

FIG. 18 is an example of a data rearrangement circuit in the third embodiment of the first invention.

FIG. 19 shows a first embodiment of the second invention.

FIG. 20 shows an example of SW setting contents in the first embodiment of the second invention.

FIG. 21 shows an example of the decoder 5 in the first embodiment of the second invention.

FIG. 22 is a RAM according to the first embodiment of the second invention.
Example of address switching unit.

FIG. 23 is a RAM according to the first embodiment of the second invention.
Example of CS separation unit.

FIG. 24 is a second embodiment of the second invention.

FIG. 25 is a RAM according to a second embodiment of the second invention.
Example of CS separation unit.

FIG. 26 is a ROM in the second embodiment of the second invention.
Example of CS separation unit.

FIG. 27 is a time chart when writing data from the buffer RAM to the target ROM in the second embodiment of the second invention.

FIG. 28 shows a third embodiment of the second invention.

FIG. 29 is a ROM in the third embodiment of the second invention.
Writing flowchart (1).

FIG. 30. ROM in the third embodiment of the second invention
Writing flowchart (2).

FIG. 31 is a ROM in the third embodiment of the second invention.
Writing flowchart (3).

FIG. 32 is a ROM in the third embodiment of the second invention.
Writing flowchart (4).

FIG. 33 is a ROM in the third embodiment of the second invention.
Writing flowchart (5).

FIG. 34 is a ROM in the third embodiment of the second invention.
Writing flowchart (6).

FIG. 35 is a ROM in the third embodiment of the second invention.
Writing flowchart (7).

FIG. 36 is a ROM in the third embodiment of the second invention.
Writing flowchart (part 8).

FIG. 37 is a ROM in the third embodiment of the second invention.
Writing flowchart (9).

FIG. 38 is a ROM in the third embodiment of the second invention.
Writing flowchart (10).

FIG. 39 is a ROM in the third embodiment of the second invention.
Write flowchart (11).

FIG. 40 is a ROM in the third embodiment of the second invention.
Writing flowchart (12).

FIG. 41 shows a fourth embodiment of the second invention.

FIG. 42 is a ROM in the fourth embodiment of the second invention.
Writing flowchart (1).

FIG. 43 is a ROM in the fourth embodiment of the second invention.
Writing flowchart (2).

FIG. 44 is a ROM in the fourth embodiment of the second invention.
Writing flowchart (3).

FIG. 45 is a ROM of the fourth embodiment of the second invention.
Writing flowchart (4).

FIG. 46 is a ROM of the fourth embodiment of the second invention.
Writing flowchart (5).

FIG. 47 is a ROM of the fourth embodiment of the second invention.
Writing flowchart (6).

FIG. 48 is a ROM in the fourth embodiment of the second invention.
Writing flowchart (7).

FIG. 49 is a ROM in the fourth embodiment of the second invention.
Writing flowchart (part 8).

FIG. 50 is a ROM in the fourth embodiment of the second invention.
Writing flowchart (9).

FIG. 51 shows an example of a conventional data read circuit from a ROM.

FIG. 52 is a time chart of a conventional data read circuit from a ROM.

FIG. 53 is a configuration of a conventional ROM writer.

FIG. 54 is a flowchart for data transfer in a conventional ROM writer.

FIG. 55 is a flowchart of data writing in a conventional ROM writer.

[Explanation of symbols]

101 Address Counter 102a Output Enable Generation Unit 103a First ROM (ROM0) 103b Second ROM (ROM1) 103c Third ROM (ROM2) 103d Fourth ROM (ROM3) 104a First D flip-flop (D-FF
0) 104b Second D-type flip-flop (D-FF)
1) 104c Third D-type flip-flop (D-FF)
2) 104d Fourth D-type flip-flop (D-FF)
3) 104e Eighth D-type flip-flop (D-FF)
7) 105a first shift register (shift register 0) 105b second shift register (shift register 1) 105c third shift register (shift register 2) 105d fourth shift register (shift register 3) 105e eighth Shift register (shift register 7)

Claims (8)

[Claims] 1. An LSB-side p-bit (p is a positive integer) logical product signal of an address counter is flipped by a clock.
The output enable generator that supplies the signal read into the flop to the 2 ^p read-only memories as an output control signal and the LSB side p bit of the address are fixed so that the combination of “L” and “H” does not overlap. Data from the read-only memory, which is set to 2 ^p read-only memories to which bits corresponding to the address counter are supplied to bits other than the LSB side p bits of the address. Readout circuit. 2. A 2 p signal having a specific output level corresponding to each combination of “L” and “H” of the setting signal of ^p is changed from a frequency equal to the clock of the address counter to 1 / clock of the clock. until 2 p ^{+ 1} of the frequency by selecting one of the frequency of the signal of the 2 ^{p + 1} frequency, 2 p ^{+ 1} of the ROM
An output enable generation section for supplying an output enable signal to the address counter, and a 2 ^p signal which becomes a specific level corresponding to each combination of “L” and “H” of the setting signal of ^p . The signal selected from each bit of the LSB side (p + 1) bits and "L" and "H" is added to the ^{2p + 1}
2 ^{p + 1} address switching unit to be supplied as the LSB side (p + 1) bits of the ROM address, and the LSB side p bits of the address are set by the output of the address switching unit, and other than the above LSB side p bits of the address. A read-only memory of 2 ^{p + 1} to which the corresponding bit of the address counter is supplied. 3. An output enable generation unit for supplying a signal obtained by reading a logical product signal of p bits on the LSB side of an address counter to a flip-flop with a clock as an output control signal to 2 ^p read-only memories, 0 to (p
-1) is added as the LSB side p bits of the p read-only memory address so as not to overlap, and the LSB side p bits of the address are supplied from the four addition circuits. In the bits other than the above-mentioned LSB-side p-bit, the LSB-side p-bit of the address counter and the MSB
A read-only memory of p supplied with bits excluding the side p bits. 4. The data read circuit from the read-only memory according to claim 3, wherein the MSB side p bit of the address counter is “L”,
A data rearrangement circuit that rearranges the data read from the p read-only memory in the ring order by the 2 ^p signal having a specific output level corresponding to the combination of “H” forms the data. A data read circuit from a read-only memory, which is provided for each number of bits. 5. The first setting specifies a data transfer mode from a personal computer to a random access memory and a data write mode from the random access memory to a target read-only memory, In the transfer mode, the transferred data is stored in the address of the random access memory designated by the central processing unit, and in the write mode, it is stored in the address of the random access memory designated by the central processing unit. In the data write circuit for writing the read data to the corresponding address of the read only memory, in the transfer mode, the MSB side p bit of the address output by the central processing unit is stored in the 2 ^p random access memory. Supplied as p-bit on LSB side of address ,
A RAM address switching unit that supplies the LSB side p bits output by the central processing unit as the LSB side p bits of the 2 ^p random access memory in the write mode, and the central processing unit outputs in the transfer mode. Access to the random access memory of 2 ^p by a 2 ^2p signal that becomes a specific level corresponding to each combination of the MSB side p bit and the LSB side p bit of “L” and “H”. Random access of one of the 2 ^p random access memories by the signal of one of the 2 ^p signals, which enables alternately and becomes a specific level corresponding to the combination of the setting states of the p in the write mode. -A RAMCS separation unit that enables access to the memory and the RAMCS separation unit that is random among the count values of the address counter A data write circuit for a read-only memory, comprising a decoder for determining a range of count values capable of outputting a chip select signal to the access memory. 6. The first setting specifies a data transfer mode from a personal computer to a random access memory and a data write mode from the random access memory to a target read-only memory, In the transfer mode, the data to be transferred is stored in the address of the random access memory designated by the address output by the central processing unit, and in the write mode, the random access memory designated by the address output by the central processing unit is stored. In a data write circuit to a read-only memory that writes the data stored in the memory address to the corresponding address of the read-only memory, in the transfer mode, the MSB side p bit of the address output by the central processing unit is set to 2 ^p Random access memory Is supplied as the LSB side p bit less,
A RAM address switching unit that supplies the LSB side p bits output from the central processing unit as the LSB side p bits of the 2 ^p random access memory in the write mode, and the count value of the address counter in the transfer mode. MSB side p-bit and LSB side p-bit "L",
It becomes a specific level corresponding to the combination of "H" 2 ^2p
Signal enables alternate access to the 2 ^p random access memory, and 2 in the write mode.
A RAMCS separation unit for supplying a signal for generating a chip select signal to a ROMCS separation unit, which will be described later, while alternately enabling access to one random access memory of ^p , and an address counter. A decoder that determines the count value range in which the RAMCS separation unit can output the chip select signal to the random access memory among the count values of the above, and a chip that the RAMCS separation unit outputs during the write mode. A ROMCS separation unit that receives a signal for generating a select signal and outputs the signal for generating the chip select signal as a chip select signal of a read-only memory depending on the state of the write register. Data read circuit from read-only memory. 7. The first setting specifies a data transfer mode from a personal computer to a random access memory and a data write mode from the random access memory to a target read-only memory, In the transfer mode, the data to be transferred is stored in the address of the random access memory designated by the address output by the central processing unit, and in the write mode, the random access memory designated by the address output by the central processing unit is stored. In the method of writing data to the read-only memory, which writes the data stored in the memory address to the corresponding address of the read-only memory, in the transfer mode, the random access memory of the random access memory specified by the address output by the central processing unit is specified. Forwarded to the address Data is stored, and in the write mode, the address of the random access memory corresponding to one combination of the setting states of p is designated first, and stored in the specified address of the random access memory. Stored data is read and the read data is written to a specified address of the read-only memory, and the specified address is set to 2
Reading from the random access memory and writing to the read-only memory are performed while advancing by ^p addresses, and when the specified address reaches a predetermined value, the specified address is advanced by (2 ^p +1) address and the random access memory Read data from the specified address, write the read data to the specified address of the read-only memory, and read from the random access memory while advancing the specified address by 2 ^p until the specified address reaches the next specified value. When the designated address reaches the next predetermined value, the designated address is advanced to the address (2 ^p +1) and the data is read from the designated address of the random access memory to read-only memory. Operation to write the read data to the specified address The process is performed until the designated address reaches the final predetermined value, and when the designated address reaches the final predetermined value, the read-only memory as the write target is exchanged, and the combination of the setting states of p is changed to a different combination. A method for writing data to a read-only memory, which comprises first setting an address of a corresponding random access memory and then repeating the above. 8. The first setting specifies a data transfer mode from a personal computer to a random access memory and a data write mode from the random access memory to a target read-only memory, In the transfer mode, the data to be transferred is stored in the address of the random access memory designated by the address output by the central processing unit, and in the write mode, the random access memory designated by the address output by the central processing unit is stored. In the method of writing data to the read-only memory, which writes the data stored in the memory address to the corresponding address of the read-only memory, in the transfer mode, the random access memory of the random access memory specified by the address output by the central processing unit is specified. Forwarded to the address When data is stored and in write mode, the address of the specified random access memory is set to the first address, the data stored at that address of the random access memory is read, and the MSB of the specified address is read. “L” of p-side bit and LSB-side p-bit,
The combination of “H” is verified, the read data is written to the read-only memory corresponding to the verified combination, the address of the designated random access memory is advanced by 1, and the address of the random access memory is advanced. Read the data stored in the
The combination of "L" and "H" of the B-side p-bit and the LSB-side p-bit is tested, the read data is written to the read-only memory corresponding to the tested combination, and the final address of the random access memory Address of random access memory to specify until
The address is advanced, the data stored at the address of the random access memory is read, and M of the designated address is read.
To a read-only memory characterized by testing a combination of "L" and "H" of the p-bit on the SB side and the p-bit on the LSB, and writing the read data to a read-only memory corresponding to the tested combination Data writing method.