JPH08249041A - Numerical controller - Google Patents

Abstract

PURPOSE: To provide a numerical controller which can fast carry out a program by retrieving a block address of the highest access frequency out of those access frequency of all block addresses and then allocating a fast memory in the retrieved block address of the highest access frequency. CONSTITUTION: An access frequency measurement means 4 measures the access frequency of a central arithmetic processing unit 1 to an ordinary memory 22 included in a block address that is shown by the block selection signal received during reception of a processing selection signal. A fast memory allocation decision means 5 sends successively all block addresses of the memory 22 to the means 4 as the block selection signals and records every access frequency to retrieve a block address of the highest access frequency. Then the unit 1 can have accesses to only plural blocks of the memory 22 before the retrieval of the block address ends, and a fast memory 21 is allocated in the block address of the highest access frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a numerical control device. In particular, when a part of the memory of the numerical control device is replaced with a high-speed memory from a normal memory to speed up a specific process,
It relates to an improvement that makes it possible to determine the placement of the fast memory so that it is most effective.

[0002]

2. Description of the Related Art In a device that uses a central processing unit and executes a target process by software, it is an effective means to use a high-speed memory instead of a normal memory in order to speed up the process. However, because high speed memory is expensive, making all of the memory high speed memory is unacceptable as it reduces the price to performance ratio. The cache method is effective and often used in a device such as a personal computer that executes various kinds of software, but it utilizes the locality of the software to be executed. Numerical control software has no locality, so it does not make much sense to use the cache method.

Therefore, in the numerical controller, a high-speed memory is fixedly arranged in a memory area, which is likely to be frequently accessed by a program for executing a high-speed process in a program to be executed.

[0004]

By the way, in the numerical control device, depending on the machine to be attached, the configuration of the option, the macro program created by the user, etc.,
The memory area that is frequently accessed changes, and further, the processing to be speeded up is added or changed. For this reason, it is hard to say that the processing to be speeded up is always executed at high speed.

An object of the present invention is to solve this problem. A numerical controller capable of allocating a high speed memory to an optimum memory area at that time and executing a program having a process to be speeded up at high speed. To provide.

[0006]

The above-mentioned object is to provide a central processing unit (1), a high-speed memory (21), and a plurality of blocks of normal memory (blocks each having a capacity less than the capacity of the high-speed memory (21). 22), which is connected to the central processing unit (1) via the bus and stores a program, and a high-speed execution selected from the program. A process selection signal generating means (3) for generating a process selection signal during a period during which the process is being executed, and a block selection signal are inputted, and while the process selection signal generated by the process selection signal generating means (3) is being received. The central processing unit (1) has the normal memory (2) located at the block address indicated by the block selection signal.
2) Access frequency measuring means (4) for counting the number of times of access, and all block addresses of the normal memory (22) are sequentially issued to the access frequency measuring means (4) as block selection signals, each time. The access frequency issued by the access frequency measuring means (4) is stored, the block address with the highest access frequency is searched from the access frequencies of all the block addresses, and the central processing unit is operated until the search is completed. A memory accessible by (1) is a plurality of blocks of the normal memory (22), and a high-speed memory allocation determining unit (5) for allocating the high-speed memory (21) to a block having the highest access frequency after the search is completed. Is achieved by a numerical controller having

The access frequency measuring means (4) is supplied with a block selection circuit (41) for latching a block selection signal and a signal corresponding to the chip selection signal to the normal memory (22). A selector (42) that outputs when the block address of this signal and the block address latched by the block selection circuit (41) match, the output of this selector (42), and the central processing unit (1) ) A ready (RDY) signal and a first gate (43) for outputting a logical product, and a process in which the output of the first gate (43) is issued to the clock terminal by the process selection signal generating means (3). When the counter (44) is provided with the selection signal input to the enable terminal, the block address indicated by the block selection signal is accessed to the normal memory 22. It is convenient because the easily can be counted.

The high-speed memory layout fixing FF (51) to which the high-speed memory layout fixing means (5) receives the high-speed memory locking signal, and the output of the high-speed memory layout fixing FF (51) Second gate (52) for outputting a logical product of the output of the selector (42) of the second gate (52) and the output of the second gate (52) and the normal memory. A signal corresponding to the chip select signal to (22) is input, and a third gate (53) for outputting a logical product of the inverted signal of the former and the latter to the chip select terminal of the normal memory (22). It is convenient to have it because the normal memory 22 and the high-speed memory 21 can be easily switched.

[0009]

The numerical controller according to the present invention has the processing selection signal generating means 3, the access frequency measuring means 4 and the high speed memory allocation determining means 5, and when a person selects a processing to be executed at high speed, the processing selection is performed. The signal generating means 3 generates a process selection signal only during a period in which a process desired to be executed at high speed is executed while executing a program including various processes recorded in a plurality of blocks of the normal memory 22. Then, the access frequency measuring means 4 is issued. Access frequency measuring means 4
Counts how many times the central processing unit 1 has accessed the normal memory 22 at the block address indicated by the input block selection signal while receiving the processing selection signal.
The high-speed memory placement determining means 5 sequentially issues all block addresses of the normal memory 22 as block selection signals to the access frequency measuring means 4, records the access frequency emitted by the access frequency measuring means 4 each time, and has the highest access frequency. Search block address. Until the end of the search, the memory that can be accessed by the central processing unit 1 is a plurality of blocks of the normal memory 22, and after the end of the search, the high-speed memory 21 is arranged at the block address with the highest access frequency.

Therefore, even if the machine to be attached, the configuration of options, or the macro program created by the user is changed, if the process desired to be accelerated is selected at the time of change, the block with the highest access frequency will be Since the high-speed memory 21 is arranged in place of the normal memory 22, the numerical control device can execute the processing desired to be executed at high speed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A numerical controller according to an embodiment of the present invention will be described in more detail below with reference to the drawings.

Referring to FIG. 1, FIG. 1 is a diagram corresponding to claims of a numerical control device according to an embodiment of the present invention. In FIG. 1, 1 is a central processing unit, 2 is a memory means connected to the central processing unit 1 via a bus, 3 is a processing selection signal generating means, and 4 is a processing selection signal generation. Access frequency measuring means for counting the frequency of accessing the normal memory 22 of the block address corresponding to the block selection signal while the processing selection signal issued by the means 3 is being output, and 5 is the access frequency measuring means for the block selection signal. 4 is a high-speed memory allocation determining means for determining the allocation of the high-speed memory based on the access frequency counted by the access frequency measuring means 4. Hereinafter, each of them will be described in terms of both hardware and software.

FIG. 2 is a block diagram showing the essential parts of the hardware of the numerical controller according to one embodiment of the present invention. In FIG. 2, reference numeral 2 is a memory means having a high speed memory 21 and a normal memory 22, and the normal memory 22 is divided into blocks each having a capacity less than or equal to the capacity of the high speed memory 21. In Figure 2, the block numbers are 1, 2,
The case of being divided into three, four and four is shown. The memory means 2 is connected to the central processing unit 1 via a bus (address bus and data bus) and stores programs and data. The central processing unit 1 sequentially executes the stored programs. Perform processing.

Reference numeral 6 is a decoder. Central processing unit 1
Issues a block address of the memory means 2 corresponding to the content to be executed to the decoder 6 via the address bus, and the decoder 6 decodes the address. Decoder 6
Issues a chip select signal to the normal memory 22 at the block address via the third gate 53. The decoder 6 was used in the numerical control device according to the prior art together with the central processing unit 1 and the memory means 2. However, conventionally, the output of the decoder 6 was directly connected to the chip select terminal of each block of the memory means 2 without passing through the third gate 53 as shown in FIG.

Reference numeral 3 is a processing selection signal generating means, and reference numeral 31 is a processing selection FF. When a process to be executed at high speed in the program, such as data reading or data analysis, is determined, a person selects a process to be executed at high speed from various processes displayed on the display means (not shown). Input from input means (not shown). Then, the high-speed memory placement process is activated by the input means. As a result, the software of the process selection signal generation means 3 described later sets the process selection FF to 1 only during the period when the process desired to be executed at high speed is executed, and the process selection FF 31 generates the process selection signal.

FIG. 3 is a time chart showing the operation of the processing selection FF 31 for the processing executed by the central processing unit 1. In FIG. 3, processing signals such as processing A, processing B, and processing C indicate the passage of time of a series of processing executed by the central processing unit 1. Process B is a process to be executed at high speed in a series of processes, and when the process B is executed, the process selection FF
31 is set (arrow), and when the process B is completed, the process selection FF 31 is reset (arrow).

Referring again to FIG. 2, reference numeral 4 is access frequency measuring means. A block selection circuit 41 receives a block selection signal indicating a block address of the memory means 2 and latches the block address. In FIG. 2, since the number of blocks of the memory means 2 is four, 2-bit latch is performed. A selector 42 outputs 1 when the block address output from the decoder 6 and the block address latched by the block selection circuit 41 match. Reference numeral 43 is a first gate to which the output of the selector 42 and the ready signal (RDY) of the central processing unit 1 are input. 44 is a counter, and the output of the first gate 43 is supplied to the clock terminal of the counter.
The output of the process selection FF 31 is connected to the enable terminal. The output of the counter 44 is output to the data bus.

When the block selection signal 00 is input to the block selection circuit 41, the block selection circuit 41 outputs 00.
When the decoder 6 issues the chip select signal of block 1, the selector 42 outputs 1. The counter 44 executes the central processing unit when the central processing unit 1 is executing a process to be executed at high speed and the block address input to the decoder 6 matches the latched block address. When the ready signal of the device 1 becomes 1, it counts each time. In other words, the number of times the normal memory 22 at the block address latched during the execution of the process desired to be executed at high speed is accessed is cumulatively recorded in the counter 44.

When a process to be executed at high speed and a process not to be executed run in parallel (process B and process A in FIG. 3), access is made to execute a process not selected in the parallel running period. This is because the number of times of execution is integrated, but in order to execute the selected process at high speed, it is necessary to execute the non-selected process at high speed only during a period in which the processes run in parallel.

Reference numeral 5 is a high speed memory arrangement determining means. 51
Is a high-speed memory arrangement fixed FF, 52 is a second gate, and 53 is a third gate. The output of the second gate is connected to the chip select terminal of the high-speed memory 21, and the output of the third gate 53 is connected to the chip select terminal of the normal memory 22.

When 0 is set to the input of the high speed memory arrangement fixing FF 51 by the software of the high speed memory arrangement determining means 5 which will be described later, the output of the second gate 52 becomes 0 and the high speed memory 21 is not activated. , Third gate 5
As for the output of the decoder 3, the output of the decoder 6 is 1 and only the output of the third gate 53 is 1.
Is activated. When 1 is set to the input of the high-speed memory arrangement fixing FF 51, the output of the second gate 52 becomes 1 when the selector 42 outputs 1. That is,
When the block address input to the decoder 6 and the block address latched in the block selection circuit 41 match, the second gate 52 outputs 1 and activates the high speed memory 21. On the other hand, since the output of the third gate 53 corresponding to this block address remains 0,
The corresponding normal memory 22 remains unactivated.
In other words, only the normal memory 22 of the block address latched by the block selection circuit 41 is the high-speed memory 2
Normal memory 22 of another block address
Is used as is.

The signal output to the block selection circuit 41 is a block selection signal, and is generated by the software of the high speed memory layout determining means 5 which will be described later.

4 and 5 are flow charts (No. 1 and No. 2) showing the software of the numerical control device according to one embodiment of the present invention. It has been incorporated. In this flowchart, steps a to i are software that defines the operation of the process selection signal generation means 3 except steps b and c, and steps j to q are the high-speed memory allocation determining means 5. It is software that defines the operation. The procedure will be described below.

First, a person uses the input means to select a process to be speeded up and activates the high speed memory placement process.

In step a, the block address data area for writing the block address of the memory means 2 and the access frequency data area for writing the access frequency prepared for the number N of block addresses are reset to 0 respectively.

In step b, the high-speed memory placement fixed FF5
Reset to 0 on 1 input. The hardware of the high-speed memory arrangement determining means 5 allows only the normal memory 22 to be used. Then, the program is written in the memory means 2.

In step c, the value written in the block address data area is output to the block selection circuit 41 as a block selection signal.

In step d, the number of times a predetermined periodic signal (see FIG. 3) has elapsed is set.

In step e, the execution of the program written in the memory means 2 is started.

In step f, it is monitored whether or not the first process to be speeded up has started, and the process waits until it starts. If it starts, the process proceeds to the next step.

In step f ', it is monitored whether or not the second process to be speeded up has started, and the process waits until it starts. If it starts, the process proceeds to the next step.

In step g, 1 is set in the process selection FF 31.

In step h, it is monitored whether or not the first process to be speeded up has started and has ended, and the process waits until it ends. If the first processing to be speeded up has not started, or has started, and has ended, the procedure proceeds to the next step.

In step h ', it is monitored whether or not the second process to be speeded up has started and has been completed, and the process waits until it is completed. If the second process to be speeded up has not started, or has started, and has ended, the process proceeds to the next step.

The access frequency measuring means 4 counts the number of times the normal memory 22 at the block address output in the procedure c is accessed until the procedure h is entered and the procedure i is advanced.

In step i, the process selection FF 31 is reset to 0.

In step j, the counter value of the counter 44 is fetched, and the integrated value of the difference from the value fetched last time is stored together with the block address which is the block selection signal output in step c.

In step k, it is monitored whether or not the number of times of the periodic signal set in step d has ended. If not, the procedure returns to step f, steps f to j are repeated, and the second integrated value is stored. To do. If so, proceed to the next step.

In step l, execution of the program started in step e is stopped.

In step m, the average value is calculated from the integrated values obtained in a plurality of times in step j, and the average value is calculated as the access frequency to the normal memory 22 at the block address output in step c, which corresponds to this block address. Write to the access frequency data area.

In step n, 1 is added to the value in the block address data area.

In step o, it is monitored whether the value in the block address data area exceeds the number N of blocks in the memory means 2, and if it does not exceed, the procedure returns to step c and steps c to n are repeated until the next step. The access frequency to the normal memory 22 at the block address is written in the access frequency data area corresponding to the next block address. If the value in the block address data area exceeds N, proceed to the next step.

In step p, the access frequencies written in the N access frequency data areas are compared, and the block address having the maximum access frequency is searched. Then, the block address is output as a block selection signal.

In the procedure q, the high-speed memory placement fixed FF5
The input of 1 is set to 1, and the hardware of the high-speed memory placement determining means 5 places the high-speed memory 21 in place of the normal memory 22 at the block address searched in step p.
Then, the program is written in the memory means 2 in which the high speed memory 21 is arranged.

With the above, the procedure of the flowchart is completed. Note that the flowchart of FIG. 4 shows a case where there are two processes to be speeded up, but when there are more processes, the process selection FF is set to 1 during the period when each process to be speeded up is executed. You can do this.

Finally, the high speed memory 21 does not have to be one block, and may be divided into a plurality of blocks having the same capacity. In this case, the capacity of one block of the normal memory 22 is not more than the same capacity as the high-speed memory 21 divided into blocks. Then, the normal memory 22 is accessed in descending order of access frequency.
May be sequentially replaced with a plurality of high-speed memories 21. In this way, the speed can be further increased without increasing the capacity of the high speed memory 21.

[0047]

As described above, according to the numerical control device of the present invention, if the process to be speeded up is selected, the speed can be increased by the process selection signal generating means and the access frequency measuring means. The number of accesses by the central processing unit when executing a desired process is counted, and the high-speed memory placement determining unit searches the memory block having the highest access frequency among the plurality of memory blocks in the memory unit. Change the memory from normal memory to high-speed memory. Even if the machine to be installed, the configuration of options, or the macro program created by the user is changed, the memory of the block that is frequently accessed can be relocated from normal memory to high-speed memory at that time, so speed up. The desired processing is executed at high speed.

[Brief description of drawings]

FIG. 1 is a diagram corresponding to claims of a numerical control device according to an embodiment of the present invention.

FIG. 2 is a hardware configuration diagram of a numerical control device according to an embodiment of the present invention.

FIG. 3 is a time chart of processing and a processing selection signal of the central processing unit according to the embodiment of the present invention.

FIG. 4 is a flowchart (No. 1) of the numerical control device according to the embodiment of the present invention.

FIG. 5 is a flowchart (No. 2) of the numerical control device according to the embodiment of the present invention.

[Explanation of symbols]

 1 central processing unit 2 memory means 3 processing selection signal generating means 4 access frequency measuring means 5 high speed memory arrangement determining means 6 decoder 21 high speed memory 22 normal memory 31 processing selection FF 41 block selection circuit 42 selector 43 first gate 44 counter 51 High-speed memory placement fixed FF 52 Second gate 53 Third gate

Claims (3)

[Claims] 1. A central processing unit (1), a high speed memory (21), and a plurality of blocks of normal memory (2) divided into blocks each having a capacity less than or equal to the capacity of the high speed memory (21).
2), which is connected to the central processing unit (1) via a bus and stores a program, and a memory means (2) for storing a program, and a process selected from the program that is to be executed at high speed. The processing selection signal generating means (3) for generating a processing selection signal during the period being executed and the block selection signal are input, and the central operation is performed while receiving the processing selection signal issued by the processing selection signal generating means (3). An access frequency measuring means (4) for counting the number of times the processing device (1) has accessed the normal memory (22) at the block address indicated by the block selection signal, and all block addresses of the normal memory (22). It is sequentially issued to the access frequency measuring means (4) as a block selection signal, and each time, the access frequency emitted by the access frequency measuring means (4) is stored, The block address having the highest access frequency is searched from the access frequencies of all the block addresses, and the memory that can be accessed by the central processing unit (1) is a plurality of blocks of the normal memory (22) until the search is completed. The numerical control device further comprises a high-speed memory arrangement determining means (5) for arranging the high-speed memory (21) in a block having the highest access frequency after completion of the search. 2. The access frequency measuring means (4) is a block selection circuit (41) for latching a block selection signal.
And a signal corresponding to the chip select signal to the normal memory (22) is input, and a selector (outputs when the block address of the signal matches the block address latched by the block selection circuit (41) ( 42)
And a first gate (43) for outputting a logical product of the output of the selector (42) and the ready (RDY) signal of the central processing unit (1), and the output of the first gate (43) 2. The numerical controller according to claim 1, further comprising a counter (44) having a clock terminal to which a processing selection signal generated by said processing selection signal generating means (3) is inputted to an enable terminal. 3. The high-speed memory placement determining means (5) comprises:
A high-speed memory arrangement fixing FF (51) to which a high-speed memory fixing signal is input, and a high-speed memory arrangement fixing FF (5
A second gate (52) for outputting a logical product of the output of 1) and the output of the selector (42) to the chip select terminal of the high speed memory (21); and the output of the second gate (52). A third gate (53) which receives a signal corresponding to the chip select signal to the normal memory (22) and outputs a logical product of the inverted signal of the former and the latter to the chip select terminal of the normal memory (22). The numerical controller according to claim 1 or 2, further comprising: