JPH08249019A - Arithmetic unit and programmable controller using the arithmetic unit - Google Patents

Abstract

PURPOSE: To increase the arithmetic processing speed for a slave processor by omitting a process where an unexected instruction is read again out of a memory and then interpreted. CONSTITUTION: When a master processor 2 reads an instruction out of an instruction memory 1, an instruction interpretation part 21 interprets the read instruction. If this instruction is not executed, the number of this instruction is stored in an interface register 22. Then the processor 2 applies an interruption to a slave processor 3 and interrupts its processing. The processor 3 takes the number out of the register 22 for the instruction that could not be executed by the processor 2 and instructs an executing module specifying part 32 to specify the head address of an executing module which is stored in an execution instruction table 31 in response to the instruction number that is taken out of the register 22. Then the processor 3 carries out the specified executing module.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a master processor,
The present invention relates to an arithmetic device including a slave processor, in which a slave processor executes instructions that a master processor does not execute, and a programmable controller using the arithmetic device.

[0002]

2. Description of the Related Art Conventionally, as a built-in arithmetic unit, there is a programmable controller (hereinafter referred to as PLC) having a multi-CPU configuration having a master processor and a slave processor.

A PL having such a multi-CPU configuration
In C, when the instruction read from the memory is not executed by the master processor, the slave processor executes the instruction in place of the master processor.

More specifically, as shown in FIG. 4, when the instruction read from the memory is not executed by the master processor (unlike the contact instruction used for PLC, a more complicated instruction is executed). For example, in the case of an instruction for calculating the day of the week), an interrupt (interruption) is sent to the slave processor (step 401) and an execution request for this instruction is output to the slave processor.

Then, the slave processor, which has received the execution request, reads the program counter of the master processor (step 402), accesses the memory for the instruction not executed by the master processor, reads it (step 403), and interprets it (step 404). ), Retrieves the instruction number assigned to this instruction (step 4
05). Then, the slave processor refers to the fetched instruction number, accesses the built-in instruction table (step 406), fetches the execution module of this instruction number from the instruction table, and the master processor does not execute the instruction. (Step 40)
7).

[0006]

However, in the PLC having the conventional multi-CPU configuration as described above, the slave processor reads the program counter of the master processor, and based on this value, the instruction not executed by the master processor from the memory address. Is read again, and the procedure of interpreting this instruction is necessary.
There has been a problem that the arithmetic processing generally takes time.

In view of the above problems, the present invention speeds up the arithmetic processing by omitting the step of the slave processor reading again the instruction that the master processor could not execute from the memory and interpreting it. An object of the present invention is to provide an arithmetic unit and a program controller using the arithmetic unit.

[0008]

To achieve the above object, the invention according to claim 1 is provided with a master processor and a slave processor, and in the case where the master processor does not execute an instruction read from a memory. Is an arithmetic unit that causes the slave processor to execute this instruction, wherein the master processor outputs to the slave processor an execution request of an instruction that it does not execute, and the master processor outputs information specifying the execution module of the instruction. The slave processor supplies the slave processor with the slave processor, and the slave processor specifies the execution module of the instruction not executed by the master processor from the information specifying the execution module from the master processor.

According to a second aspect of the present invention, a master processor and a slave processor are provided, and when the master processor does not execute the instruction read from the memory,
An arithmetic unit for causing the slave processor to execute the instruction, wherein the master processor interprets the instruction, and an instruction interpreting means, and when the instruction read by the instruction interpreting means is determined not to be executed, , An instruction number storage means for storing a unique instruction number of the instruction, while the slave processor stores execution module storage means for storing an execution module for an instruction not executed by the master processor, and the instruction number storage And an execution module specifying means for specifying the module stored in the execution module storage means based on the instruction number stored in the means.

According to a third aspect of the present invention, in the second aspect of the present invention, the instruction number storage means has a unique instruction number of an instruction not executed by the master processor and an execution condition when the instruction is executed. Is stored.

According to a fourth aspect of the present invention, the invention of the arithmetic unit according to the first, second or third aspect is applied to a programmable controller.

[0012]

According to the present invention, in the master processor,
The execution request of the instruction that is not executed is output to the slave processor, and the information specifying the execution module of this instruction is supplied to the slave processor. Then, in the slave processor, the execution module of the instruction that the master processor does not execute is specified, and this instruction is executed in place of the master processor.

[0013]

Embodiments of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of an arithmetic unit used in a PLC according to the present invention.

The arithmetic unit of this embodiment comprises an instruction memory 1
And a master processor 2 and a slave processor 3.

The instruction memory 1 is a ROM (Read Onky Memo).
ry), a RAM (Randam Access Memory), and the like, and stores a processing program including a ladder instruction for executing a PLC, for example.

The master processor 2 includes an instruction interpretation unit 21,
The interface register 22 is mainly configured.

Here, the instruction interpreting section 21 uses the instruction memory 1
If the read instruction is an instruction that cannot be processed by itself (master processor 2), the instruction number of this read instruction and this read instruction are interpreted. The interface register 22 stores processing conditions, such as an operand indicating a storage location of data required during execution processing.

The interface register 22 is adapted to store the instruction number, the processing condition and the like of the above-mentioned instruction which is not executed.

The slave processor 3 is mainly composed of an instruction execution table 31 and an execution module specifying unit 32.

Here, the instruction execution table 31 stores an execution module for an instruction that the master processor 2 does not execute.

The execution module specifying unit 32 is the slave 3
Is received from the master processor 2, the interface register 22
By referring to the instruction number of the instruction which the master processor 2 does not execute read from, the corresponding execution module stored in the instruction execution table 31 is specified.

Explaining the above identification method, the execution module identification unit 32 identifies the start address of the execution module stored in the instruction execution table 31 by performing a predetermined operation on the instruction number from the interface register 22. are doing. For example, as shown in FIG.
The value obtained by adding the offset to the instruction number of is used as the start address of the execution module of the instruction 1.

When the execution of the execution module is completed, the slave processor 3 having the above-mentioned configuration is configured to return a notification to that effect to the master processor 2.

Next, the operation of this embodiment will be described with reference to FIG.

When the master processor 2 makes an access to the instruction memory 1 from a built-in program counter (not shown) using the count value indicated by the program counter as an access address, the instruction memory 1 stores the instruction memory 1 at this access address. Instruction is read.

Then, the instruction interpreter 21 determines that the instruction memory 1
The instruction read from is interpreted, and as a result, when the read instruction is an instruction that is not executed, the instruction number and processing condition of the read instruction are stored in the interface register 22. After that, the master processor 2 interrupts the slave processor 3 (step 301) and then interrupts the processing.

When the slave processor 3 receives the interrupt from the master processor 2, the slave processor 3 fetches the instruction number and the processing condition (interface information) stored in the interface register 22 which the instruction not executed by the master processor 2 (step 303). ), Instructs the execution module identification unit 32 to identify the start address of the execution module stored in the instruction execution table 31 corresponding to this instruction number, and executes the identified execution module (step 305).

After that, when the execution of the execution module is completed, the slave processor 3 outputs a notification to that effect to the master processor 2 and returns control to the master processor 2.

The master processor 2 cancels the interruption, reads the instruction stored at the address next to the unexecuted instruction from the instruction memory 1, interprets it, and performs the same processing as described above.

In this embodiment, as described above, when the instruction interpreting section 21 determines that the master processor 2 does not execute the instruction, the interface register 22 stores the unique instruction number and the like of this instruction, And
The execution module identification unit 32 of the slave processor 3
Based on the instruction number stored in the interface register 22, the start address of the execution module stored in the instruction execution table 31 is specified, and the specified execution module is executed. Therefore, the slave processor 3
Reissues an instruction that the master processor 2 did not execute,
The step of reading from the instruction memory 1 and interpreting can be omitted. Therefore, the arithmetic unit of this embodiment can perform arithmetic processing at high speed.

[0032]

As described above, according to the arithmetic unit of the present invention, in the master processor, an execution request of an instruction that is not executed is output to the slave processor, and information specifying the execution module of this instruction is transmitted to the slave processor. Supplied to the processor. Then, in the slave processor, the execution module of the instruction that the master processor does not execute is specified, and this instruction is executed in place of the master processor.

Therefore, it is possible to omit the step of the slave processor reading again the instruction that the master processor did not execute from the memory and interpreting it, and it is possible to speed up the arithmetic processing.

The arithmetic unit of the present invention is preferably applied to a program controller.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a PLC arithmetic unit according to the present invention.

FIG. 2 is a diagram illustrating a process of specifying an instruction module.

FIG. 3 is a flowchart for explaining the operation of this embodiment.

FIG. 4 is a flowchart illustrating an operation of a conventional PLC arithmetic unit.

[Explanation of symbols]

 1 Instruction Memory 2 Master Processor 3 Slave Processor 22 Instruction Interpretation Unit 23 Interface Register 31 Instruction Execution Table 32 Execution Module Specification Unit

Claims (4)

[Claims] 1. An arithmetic unit comprising a master processor and a slave processor, wherein the slave processor executes the instruction when the instruction read from the memory is not executed by the master processor. The processor outputs an execution request for an instruction that it does not execute to the slave processor and supplies information specifying the execution module of this instruction to the slave processor, and the slave processor receives the execution module from the master processor. An arithmetic unit characterized by specifying an execution module of an instruction that the master processor does not execute from the specifying information. 2. An arithmetic unit comprising a master processor and a slave processor, wherein the slave processor executes the instruction when the instruction read from the memory is not executed by the master processor. An instruction interpreting means for interpreting the instruction, and an instruction number storing means for storing a unique instruction number of the instruction when it is determined that the instruction read by the instruction interpreting means does not execute, On the other hand, the slave processor includes an execution module storage means for storing an execution module for an instruction not executed by the master processor, and an execution module storage means for storing the execution module on the basis of an instruction number stored in the instruction number storage means. Execution module specifying means for specifying the stored module and Arithmetic apparatus characterized by comprising a. 3. The operation according to claim 2, wherein the instruction number storage means stores a unique instruction number of an instruction not executed by the master processor and an execution condition when the instruction is executed. apparatus. 4. A programmable controller using the arithmetic unit according to claim 1, 2, or 3.