JPH08242003A - Insulation gate type field effect semiconductor device and its production - Google Patents

Abstract

PURPOSE: To allow a power feeding point to be closer to a channel by forming an Al gate electrode and its oxide end part in alignment with a contact hole for picking-up electrode in a source area or drain area. CONSTITUTION: An aluminum is used for a gate electrode 8 of a TFT, and the electrode 8 is subject to anodization so as to form an aluminum oxide 10 around the electrode 8. As a result, at least the sides of the electrode 8 are covered with an aluminum oxide 10. A contact hole is made through self alignment by using the electrode 8 and end parts of the aluminum oxide 10. Since an insulation film 9 hardly exists on the gate electrode when an area where the film 9 is etched by using the aluminum as a mask is extended over the electrode 8, the edge of a source or drain area becomes the aluminum oxide 10 securely. An electrode 7 for source and drain is connected with a source and drain area 3 while being almost entirely in contact with the end face of the aluminum oxide 10, thereby shortening the distance between the power feeding point of electrode and channel area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and is particularly applicable to a liquid crystal display device, a perfect contact type image sensor device and the like.

[0002]

2. Description of the Related Art Conventionally known insulating gate type field effect semiconductor devices are widely used in various fields. This semiconductor device is formed on a silicon substrate and is used as an IC or an LSI by functionally integrating a large number of semiconductor elements.

On the other hand, although a similar insulating gate type field effect semiconductor device is used, a thin film type insulating gate type field effect semiconductor device (hereinafter referred to as TFT) formed by laminating thin films other than a silicon substrate such as an insulating substrate is a liquid crystal display. It has begun to be actively used in the switching element portion of the pixel of the device, the drive circuit portion, the reading circuit portion of the contact image sensor, and the like.

Since this TFT is formed by laminating a thin film on an insulating substrate by a vapor phase method as described above, it can be formed at a temperature as low as 500 ° C. at the highest, and can be made of inexpensive soda glass or borosilicate. Acid glass or the like can be used as the substrate.

As described above, a transistor can be easily manufactured on a large-area substrate because it can be manufactured on an inexpensive substrate and its maximum size is limited only to the size of an apparatus for forming a thin film by a vapor phase method. It has an advantage that it can be formed, and therefore, it is expected to be used for a liquid crystal display device of a matrix structure having a large number of pixels and a one-dimensional or two-dimensional image sensor, and it is partially realized.

A typical structure of this TFT is schematically shown in FIG.

In FIG. 2, 1 is an insulating substrate made of glass, 2 is a thin film semiconductor made of an amorphous semiconductor, and 3 is a thin film semiconductor.
Is a source / drain region, 7 is a source / drain electrode, and 11 is a gate electrode.

As described above, since the semiconductor layer used in such a TFT is formed by the vapor phase method, compared with the semiconductor layer used in the conventional IC or LSI, holes and electrons are not generated. Since the mobility is considerably small, heat treatment is usually performed to crystallize the semiconductor layer 2.

[0009]

As in the conventional example shown in FIG. 2, a relatively thick silicon nitride film is usually formed on the gate electrode.
An interlayer insulating film 4 such as a silicon oxide film is provided to cover the gate electrode 11, and a contact hole is provided to this interlayer insulating film by a photolithography method. At the contact hole portion, the source / drain electrode 7 and the source / drain region 3 are formed. To be electrically connected. When a power supply point to the source or the drain is provided at such a position, the distance L between each power supply point and the end of the channel becomes considerably long.

As described above, a TFT manufactured by a thin film low temperature process originally has a low carrier mobility, so that even if an impurity is doped, the conductivity is still low.
A resistance occurs at this distance L. Therefore, the frequency characteristics of the TFT are deteriorated and the ON resistance is increased. Also,
As the distance L becomes longer, the area required for one TFT naturally increases, and it has become difficult to provide a predetermined number of TFTs in a limited substrate size.

Therefore, the present invention is an improvement of the TFT in order to shorten the distance L from the feed point to the source or drain region adjacent to the channel region of the insulated gate field effect semiconductor device to the channel end.

[0012]

The TFT of the present invention is characterized in that aluminum is used as a gate electrode, and at least a side surface of the gate electrode is covered with an oxide of aluminum. Further, it is characterized in that a contact hole for a take-out electrode in the source or drain region is provided so as to substantially coincide with the end face of the aluminum oxide on the side surface of the gate electrode.

Further, in order to increase the mobility of carriers in the semiconductor layer, if necessary, a semiconductor film containing silicon containing hydrogen as a main component is formed on a substrate and then the semiconductor film containing silicon as a main component is formed. On the other hand, the value of this mobility is improved by modifying the structure having crystallinity by heat treatment. Further, in order to minimize the distance L from the feeding point, the gate electrode is made of aluminum, and the periphery of the gate electrode is oxidized to form aluminum oxide on at least the side surface.

Furthermore, by utilizing this gate electrode and the aluminum oxide film existing around it, the contact hole for the extraction electrode in the source or drain region is self-aligned so as to be substantially aligned with the ends of the gate electrode and aluminum oxide. It is characterized in that it is formed in a uniform manner.

That is, as shown in the schematic cross-sectional view of the TFT shown in FIG. 1, aluminum oxide 10 is provided on at least the side surface of the gate electrode 8, and the source and drain electrodes are substantially aligned with the end surface of the aluminum oxide. Electrode 7
Are connected to the source / drain region 3. With such a configuration, it is possible to shorten the distance L from the feeding point of the electrode to the channel region.

It is ideal to reduce the distance L to zero completely, although it is ideal for reducing the resistance (almost zero in the figure), but it is a problem in the process technology. For example, the source and drain regions are slightly gated. Since it goes under the electrode, it cannot be completely zero, but a considerable effect can be expected only by shortening it.

Further, although the aluminum oxide film around the gate electrode is formed on the side surface and the upper surface, that is, the portion exposed to the outside in FIG. 1, in the present invention, it is particularly necessary that aluminum oxide is provided all around. Not necessarily
In order to shorten the distance L, it is only necessary to cover it so as to cover at least the vicinity of the side surface. On the other hand, when it is provided all over, the aluminum oxide is hard to be etched when the contact hole is formed, so that it remains as it is. It can be used as part of a mask. Furthermore, since other wiring, for example, the wiring of the source electrode is crossed on the aluminum oxide film, three-dimensional wiring can be easily performed,
The layout for integration becomes simple.

In the present invention, to make the end portions of the gate electrode and the aluminum oxide substantially coincide with the contact holes for the extraction electrodes in the source or drain regions means:
Utilizing the gate electrode and the end of aluminum oxide,
The structure formed as a result of forming the contact hole by the self-alignment is naturally included, and the range formed by the mask misalignment which can be aligned by using the photomask by another method is also included. That is, in the latter case, when only the contact portion is formed on the insulating film 5 as shown in FIG.
The edge of the insulating film 9 and the edge of the aluminum oxide may be misaligned during mask alignment, but such a case is also included.
Further, as in the former case, when aluminum oxide is positively used as a mask, that is, when the range of etching the insulating film is included up to the gate electrode, the insulating film 9 does not exist on the gate electrode and the end of the source or drain region is not formed. Reliably becomes aluminum oxide 10 and the distance L can be shortened.

As a method of forming aluminum oxide around the gate electrode, it can be considered that the gate electrode is formed by anodic oxidation. The anodic oxidation is to oxidize an aluminum gate electrode by an electrochemical reaction by passing a current in an acid solution, but if the formed oxide film is dense and has a high oxidation rate. Of course, other methods can also be used.

The present invention will be described below based on the embodiments of the present invention.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION In this embodiment, an example in which the TFT of the present invention is applied to a liquid crystal electro-optical device having a circuit as shown in FIG. 5 is shown. In this figure, each pixel of the liquid crystal device is provided with an N-channel type thin film transistor 22 and a P-channel type thin film transistor 21 in a complementary structure, and each TFT has its gate electrode connected to a common signal line 50. , The output terminals of the NTFT 22 and the PTFT 21 are connected to the common pixel electrode 43, and the other output terminal 2 of each is connected.
Reference numerals 8 and 35 are connected to the other signal lines 52 and 53 to form an inverter configuration. Also, this PTFT and N
Swap the position of the TFT to create a buffer type structure,
Complementary TFTs may be provided on each pixel electrode.

The manufacturing process when the TFT of the present invention used in the liquid crystal electro-optical device having such a structure is formed as a complementary TFT on a glass substrate will be described with reference to FIGS.

In FIG. 3A, crystallized glass such as AN glass or Neocera glass, or expensive glass such as quartz glass which can withstand a heat treatment of 700 ° C. or less, for example, about 600 ° C., such as Vicol 7913 (made by Corning). Not magnetron on glass 1
A silicon oxide film as the blocking layer 24 was formed to a thickness of 1000 to 3000 Å by RF (radio frequency) sputtering method.

Process conditions are 100% oxygen atmosphere, film formation temperature
The temperature was 150 ° C, the output was 400 to 800W, and the pressure was 0.5Pa. Quartz or single crystal silicon was used as the target material, and the film formation rate at that time was 30 to 100 Å / min.

LPCVD (Low pressure vapor phase) with a silicon film on this
Formed by a sputtering method, a sputtering method or a plasma CVD method.
When formed by the vacuum vapor phase method, the temperature is 100 to 20 ° C above the crystallization temperature.
0 ° C lower 450-550 ° C, e.g. 530 ° C, disilane (Si
₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was supplied to the CVD device to form a film. The pressure in the reaction furnace was 30 to 300 Pa. The film formation rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the NTFT and the PTFT to be approximately the same, boron is used in an amount of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3 using diborane.
It may be added during the film formation as a concentration of.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and argon is mixed with hydrogen in an amount of 20 to 80%. For example, argon is 20% and hydrogen is 80%. The deposition temperature is
150 ° C, frequency 13.56MHz, spatter output 400-800W
And The pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into a PCVD device, and high-frequency power of 13.56 MHz was applied to form a film.

The coating formed by these methods is
It is preferable that oxygen is 7 × 10 ²⁰ cm ⁻³ or less. If the oxygen concentration is high, it is difficult to crystallize the semiconductor layer, so that the temperature of the thermal annealing must be increased or the thermal annealing time must be increased. On the other hand, if the amount is too small, the leak current in the off state increases when the semiconductor layer is irradiated with light by the backlight used in the liquid crystal electro-optical device.
Therefore, in the range of 4 × 10 ¹⁹ to 4 × 10 ²¹ cm ⁻³ , crystallization can be easily performed by thermal annealing at a medium temperature (600 ° C. or lower). On the other hand, the amount of hydrogen in the film was 4 × 10 ²⁰ cm ⁻³ , which was about 1 atom% when compared with 4 × 10 ²² cm ⁻³ of silicon.

In order to further promote crystallization of the source and drain regions, the oxygen concentration is set to 7 × 10 ²⁰ cm ^-3 or less, preferably 7 × 10 ¹⁹ cm ^-3 or less, and a TFT which constitutes a pixel is formed. It is also effective to add oxygen, carbon or nitrogen to only a part of the channel forming region of the above by ion implantation so as to have a concentration of 5 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ to weaken the sensitivity to light. . In this case, especially in the TFT constituting the peripheral circuit, the mixing of oxygen can be reduced, the carrier mobility can be increased, the high-frequency operation can be easily performed, and the TFT around the pixel can be easily operated. The switching TFT can reduce the leak current in the off state.

Thus, the amorphous silicon film 50 is formed.
After making a thickness of 0 to 5000Å, for example 1500Å, 450 to 70
The medium was heat-treated at a temperature of 0 ° C. for 12 to 70 hours in a non-oxide atmosphere. For example, the temperature was kept at 600 ° C. in a nitrogen or hydrogen atmosphere.

Since the silicon oxide film having an amorphous structure is formed on the surface of the substrate below the silicon film, no specific nucleus exists in this heat treatment, and the whole is uniformly annealed by heating. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

The annealing causes the silicon film to shift from an amorphous structure to a highly ordered state, and a part thereof exhibits a crystalline state. In particular, a region having a relatively high degree of order during the film formation of silicon is particularly crystallized and tends to be in a crystalline state. However, since silicon existing between these regions is bonded to each other, the silicon members pull each other. When measured by laser Raman spectroscopy, a peak shifted to a low frequency side from the peak 522 cm ^{-1 of} single crystal silicon is observed. The apparent grain size is 50 to 500 Å, which is similar to that of a microcrystal when calculated from the half-width, but in reality, there are many regions with high crystallinity and they have a cluster structure. It was possible to form a film with a semi-amorphous structure in which silicon was bonded (anchoring) with each other.

In such a coating, for example SIMS
When the distribution in the depth direction was measured by the (secondary ion mass spectrometry) method, oxygen was found to be 3.4 in the lowest region (the surface or a position apart from the surface (inside)) as an additive (impurity).
X 10 ¹⁹ cm ^-3 and nitrogen 4 x 10 ¹⁷ cm ^-3 were obtained. Further, hydrogen was 4 × 10 ²⁰ cm ⁻³ , and was 1 atom% when compared with silicon 4 × 10 ²² cm ⁻³ .

This crystallization has an oxygen concentration of, for example, 3.5 × 1.
At 0 ¹⁹ cm ^-3 , the film thickness of 1000Å is 600 ° C (4
It is possible to perform heat treatment for 8 hours. This is 3 × 10 ²⁰ cm
^If it is set to ^-3 , the film thickness becomes 0.3 to 0.5 μm and it becomes 6
Crystallization by annealing at 00 ° C was possible,
A heat treatment at 650 ° C. was necessary for crystallization at a thickness of 0.1 μm. That is, the thicker the film thickness and the lower the concentration of impurities such as oxygen, the easier the crystallization was.

As a result, the coating exhibits a state in which it may be said that it is substantially free of grain boundary (referred to as GB). Since the carriers can easily move between the clusters through the anchored portions, the carrier mobility is higher than that of polycrystalline silicon in which so-called GB is clearly present. That Ho - Le mobility ^{(μh) = 10~200cm 2 / Vsec} , electron mobility ^{(μe) = 15~300 cm 2 /} Vsec is obtained.

On the other hand, when the film is polycrystallized by a high temperature anneal of 900 to 1200 ° C. instead of the anneal at a medium temperature as described above, the solid phase growth from the nuclei causes the segregation of impurities in the film. , GB has a large amount of impurities such as oxygen, carbon, and nitrogen, and the mobility in the crystal is large, but the barrier in GB is
To prevent the movement of carriers there. As a result, it is difficult to obtain a mobility of 10 cm ² / Vsec or more.

Therefore, in the embodiment of the present invention, for the reasons as described above, a semi-amorphous or silicon semiconductor having a polycrystalline structure can be used if the mobility of carriers can be increased.

In FIG. 3A, a silicon film is subjected to photoetching using a first photomask to form a PTFT region 21 (channel width 20 μm) on the right side of the drawing and an NTFT region 22 on the left side. did.

A silicon oxide film is formed on this as a gate insulating film 27 to a thickness of 500 to 2000Å, for example 1000Å. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During this film formation, a small amount of halogen element such as fluorine may be added to fix sodium ions.

After that, an aluminum film having a thickness of 0.3 μm was formed on the upper side. This was patterned with a second photomask. The gate electrode 26 for PTFT and the gate electrode 25 for NTFT are shown in FIG.
Was formed as shown in FIG. For example, the channel length is 10 μm.

In FIG. 3C, the photoresist 31
Is formed by using a photomask, and boron is added to the PTFT source 28 and the drain 30 at 1 × 10 ¹⁵ cm ^-2.
Was added by the ion implantation method.

Next, as shown in FIG. 3D, the photoresist 3
2 was formed using a photomask. And NTFT
1 x 10 phosphorus for source 35 and drain 33
^It was added by the ion implantation method at a dose amount of ¹⁵ cm ^-2 .

These are performed through the gate insulating film 27. However, in FIG. 3B, the gate electrodes 26, 25
May be used as a mask to remove silicon oxide on the silicon film, and then boron and phosphorus may be directly ion-implanted into the silicon film.

Next, after removing the photoresist 32, a heating anneal was performed again at 650 ° C. for 10 to 50 hours. And the source 28, drain 30, N of the PTFT
Impurities in the source 35 and drain 33 regions of the TFT were activated to produce p ⁺ and n ⁺ .

Channel formation regions 34 and 29 are formed below the gate electrodes 25 and 26 as semi-amorphous semiconductors.

By doing so, a complementary TFT can be manufactured without applying a temperature of 700 ° C. or higher in all steps, even though it is a self-aligning method. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and the process is extremely suitable for the large-pixel liquid crystal display device of the present invention.

Thermal annealing was performed twice in FIGS. 3A and 3D. However, the anneal of FIG. 3A may be omitted depending on the desired characteristics, and both may be used by the thermal anneal of FIG. 3D to shorten the manufacturing time.

In the present invention, since aluminum is used as the gate electrode, the annealing in the step of FIG. 3 (D) causes the hydrogen atoms present in the gate insulating film to have a large number of hydrogen molecules. It was also possible to reduce the interface state density of the gate insulating film and reduce the disappearance of unnecessary carriers at the same time.

In FIG. 4A, the gate electrodes 25, 2
6 was anodized to form aluminum oxide around it. Specifically, as a bath composition, carbon was used as a cathode in a 13.7% sulfuric acid solution, and 30% from a corresponding substrate.
The measurement was performed at a current density of 1 mA / cm ² with a distance of about cm. The thickness of the aluminum oxide is 0.2 to 1 μm, for example, 0.5 μm, and the aluminum oxide is formed in this embodiment.

As the solution used for this anodic oxidation, a strong acid solution such as sulfuric acid, nitric acid or phosphoric acid, or a mixed acid obtained by mixing tartaric acid or citric acid with ethylene glycol, propylene glycol or the like can be typically used. Also, if necessary,
In order to adjust the pH of this solution, a salt or an alkaline solution can be mixed.

First, with respect to 1% of a 3% tartaric acid aqueous solution, 9
This substrate was immersed in an AGW electrolytic solution containing propylene glycol at a ratio of 1., an aluminum gate electrode was connected to an anode of a power source, and direct current power was applied by using carbon as a cathode.

The anodizing conditions were as follows: a constant current mode was applied for 20 minutes at a current density of 1 mA / cm ² , followed by a constant voltage mode for 5 minutes, and aluminum oxide having a thickness of 5000 Å was formed near the side surface of the gate electrode. Formed. When the insulating property of this aluminum oxide was examined using a sample prepared under the same conditions as the oxidation treatment, an aluminum oxide film having a specific resistance of 10 ⁹ Ωm and a withstand voltage of 2 × 10 ⁵ V / cm was obtained. Met.

When the surface of this sample was observed with a scanning electron microscope, the surface was magnified up to about 8000 times and irregularities on the surface could be observed, but minute holes could not be observed and a good insulating film was obtained. Met.

In FIG. 4B, the inter-layer insulator 41 was formed as a silicon oxide film by the above-mentioned sputtering method. The silicon oxide film may be formed by using the LPCVD method or the photo CVD method. For example, it is formed to a thickness of 0.2 to 1.0 μm. After that, as shown in FIG. 4B, a window 42 for an electrode was formed using a photomask. At that time, the position of the contact hole 42 is made as close as possible to the vicinity of the channel in a self-aligning manner by using the RIE method by utilizing the gate electrodes 25 and 26 and the aluminum oxide 40 around the gate electrodes 25 and 26, and the source and drain are connected to the power supply point. The feature of the present invention is that the distance L to the channel region is reduced as much as possible.

Further, aluminum is formed on the whole of these to a thickness of 0.5 to 1 μm by a sputtering method, and leads 52 and 53 are formed by using a photo mask, and PTF is formed.
As the electrodes of the source regions 28 and 35 of T and NTFT, FIG.
It was prepared as in (C).

Further, the surface was coated with an organic resin 44 for flattening, for example, a light-transmitting polyimide resin, and an electrode hole was formed again using a photomask.

As shown in FIG. 4B, the two TFTs have a complementary structure, and the output terminal thereof is connected to the electrode of one pixel of the liquid crystal device as a transparent electrode. Tin oxide film) was formed. It was etched with a photomask to form the electrode 43. This ITO is deposited at room temperature to 150 ℃, and 200 to 40
Fulfilled by annealing at 0 ° C. oxygen or air.

In this way, the PTFT 21 and the NTFT are
22 and the electrode 43 of the transparent conductive film were formed on the same glass substrate 1.

The characteristics of the TFT were that the mobility of PTFT was 20 cm ² / Vsec, Vth was −5.9 V, the mobility of NTFT was 40 cm ² / Vsec, and Vth was +5.0 V.

By using such a semiconductor, it is possible to obtain a large mobility even in a TFT, which is generally impossible. Therefore, for the first time, an active liquid crystal display device in which a complementary TFT is formed in each pixel of the liquid crystal electro-optical device could be manufactured. On-glass peripheral circuits
(A method of forming the same TFT on the same substrate by a similar manufacturing process) has become possible.

In the present embodiment, the TFT of the present invention is applied to the liquid crystal electro-optical device. Therefore, since the frequency characteristic of the TFT is good, a moving image can be easily displayed, and the projection TV, the viewfinder of the video movie, and the wall-mounted TV can be displayed. Etc. can be applied. In addition, as another application, it can be used as a driving element of a one-dimensional or two-dimensional image sensor by taking advantage of good frequency characteristics.
The reading speed is sufficiently compatible with the G4 standard.

As described above, a cell for a liquid crystal electro-optical device is formed by a known method using the formed glass substrate and the substrate on which the opposite electrode made of a stripe-shaped transparent electrode is formed on the other glass substrate. To make. The liquid crystal material is filled in the cell for this liquid crystal electro-optical device.
If TN liquid crystal is used, the distance should be about 10 μm,
It is necessary to form an alignment film on both the transparent conductive films by rubbing.

When FLC (ferroelectric) liquid crystal is used as the liquid crystal material, the operating voltage is ± 20 V and the cell interval is 1.5 to
The thickness may be 3.5 μm, for example 2.3 μm, and an alignment film may be provided only on the counter electrode to perform rubbing treatment.

When the dispersion type liquid crystal or the polymer liquid crystal is used, the alignment film is unnecessary, and the operating voltage is ± 10 to ± 15 V and the cell interval is 1 in order to increase the switching speed.
Thinned to ~ 10μm.

In particular, when the dispersion type liquid crystal is used, since the polarizing plate is not necessary, it is possible to increase the light amount both as the reflection type and the transmission type. Since the liquid crystal does not have a threshold, a large contrast and crosstalk (bad interference with adjacent pixels) are eliminated by adopting the C / TFT type in which a clear threshold voltage of the present invention is defined. I was able to.

[0066]

INDUSTRIAL APPLICABILITY According to the present invention, by using aluminum as a gate electrode material, aluminum oxide by anodizing method of aluminum is provided on the surface, and three-dimensional wiring having a three-dimensional intersection is provided thereon. It has a feature. Further, by providing the source / drain contact holes with the gate electrode and the aluminum oxide around the electrodes to bring the feeding point closer to the channel, it was possible to prevent the frequency characteristics of the device from decreasing and the ON resistance to increase.

Further, in the present invention, since aluminum is used for the gate electrode, hydrogen in the gate oxide film can be reduced to H ₂ → H by the catalytic effect of aluminum during annealing during the element forming process to further reduce hydrogen. The interface state density (Q _SS ) can be reduced as compared with the case where a silicon gate is used, and the device characteristics can be improved.

Further, since the source and drain regions of the TFT are self-aligned and the contact portions of the electrodes for supplying power to the source and drain regions are also defined as self-aligned lines, the area of the element required for the TFT is reduced and the integration degree is reduced. Can be made a factory. Moreover, when used as an active element of a liquid crystal electro-optical device, the aperture ratio of the liquid crystal panel could be increased.

For the C / TFT according to the present invention,
Semi-amorphous or semi-crystal was used as a semiconductor. However, other crystalline semiconductors may be used if possible for the same purpose. In addition, high-speed processing was performed using a self-aligned C / TFT. However, the TFT may be formed by the non-self-aligning method without using the ion implantation method. In addition, it is not a stagger type but an inverted stagger type T
It goes without saying that it may be an FT or other type of TFT.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an insulating gate type field effect semiconductor device of the present invention.

FIG. 2 is a schematic cross-sectional view of a conventional insulating gate type field effect semiconductor device.

FIG. 3 is a manufacturing process of an insulating gate type field effect semiconductor device of the present invention.

FIG. 4 is a manufacturing process of an insulating gate type field effect semiconductor device of the present invention.

FIG. 5 is a circuit diagram of a liquid crystal electro-optical device to which the insulating gate type field effect semiconductor device of the present invention is applied.

[Description of Reference Signs] 1 substrate 2 semiconductor layer 3 source / drain region 6 gate insulating film 7 source / drain electrode 8 gate electrode 10 aluminum oxide

Claims (5)

[Claims] 1. A semiconductor film including (a) a source region and a drain region formed on a substrate having an insulating surface and a channel forming region sandwiched between these regions, and (b) a gate insulating film. A gate electrode made of aluminum provided on the channel forming region; (c) an oxide layer of aluminum formed so as to cover at least a side surface of the gate electrode; (d) the oxide on a side surface of the gate electrode. An interlayer insulating film having a contact hole for a take-out electrode from the source region or the drain region substantially corresponding to an end face of the layer; and (e) extending over the interlayer insulating film taken out through the contact hole. An insulating gate type field effect semiconductor device characterized by being provided with an electrode wiring. 2. The insulated gate field effect semiconductor device according to claim 1, wherein the contact hole has a structure formed by self-alignment using the gate electrode and the oxide layer. 3. The insulating gate type field effect semiconductor device according to claim 1, wherein the oxide layer is obtained by anodic oxidation. 4. The insulated gate field effect semiconductor device according to claim 1, wherein the electrode wiring constitutes a pixel electrode of a liquid crystal device. 5. (a) A step of forming a semiconductor island region on a substrate having an insulating surface, and (b) a step of forming a gate electrode made of aluminum on the semiconductor island region via a gate insulating film. (C) a step of implanting impurity ions into the semiconductor island region to form an impurity region by using the gate electrode as a mask, and (d) an oxide covering at least a side surface of the gate electrode by anodizing the gate electrode. A step of forming a layer, (e) a step of forming an interlayer insulating film covering the semiconductor island region, and (f) taking out from the impurity region substantially coincident with an end face of the oxide layer in the interlayer insulating film. An insulating gate comprising: a step of forming a contact hole for an electrode; and (g) a step of forming an electrode wiring extending on the interlayer insulating film through the contact hole. The method for manufacturing a field effect semiconductor device.