JPH08241950A - Semiconductor device and its mounting method - Google Patents
Semiconductor device and its mounting methodInfo
- Publication number
- JPH08241950A JPH08241950A JP7043061A JP4306195A JPH08241950A JP H08241950 A JPH08241950 A JP H08241950A JP 7043061 A JP7043061 A JP 7043061A JP 4306195 A JP4306195 A JP 4306195A JP H08241950 A JPH08241950 A JP H08241950A
- Authority
- JP
- Japan
- Prior art keywords
- alloy
- package
- pin
- pins
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、パッケージの底面から複数のピンが取り出され、こ
れら複数のピンを介して実装基板に面実装されるタイプ
の半導体装置に適用して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device of a type in which a plurality of pins are taken out from a bottom surface of a package and surface-mounted on a mounting board through the plurality of pins. Regarding effective technology.
【０００２】[0002]
【従来の技術】ＬＳＩで代表される半導体装置は、高集
積化、高機能化が進むにつれて、パッケージから取り出
されるリードの数は益々増加する傾向にある。このよう
な多リード化に適応した代表的なパッケージとして、Ｑ
ＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）が知られ
ている。2. Description of the Related Art In a semiconductor device represented by an LSI, the number of leads taken out from a package tends to increase more and more as the degree of integration and the function thereof increase. As a typical package adapted to such multiple leads, Q
FP (Quad Flat Package) is known.
【０００３】ここで、ＱＦＰは複数のリードをパッケー
ジの周囲から取り出しているので、ＬＳＩを実装基板に
面実装する場合は、パッケージ周囲におけるリードの広
がり分だけ面積を占有してしまうため、実装上の制約を
受けるようになる。Here, since the QFP takes out a plurality of leads from the periphery of the package, when the LSI is surface-mounted on the mounting substrate, the area is occupied by the spread of the leads around the package. Will be subject to restrictions.
【０００４】このため、リードに代えてピンを用いて、
これらピンを底面から取り出すようにしたパッケージと
してＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）構造が提
供されるようになってきた。このＰＧＡを有するＬＳＩ
によれば、複数のピンはパッケージの周囲からではな
く、全面から取り出されるので、ピンを実装基板に挿入
して実装することにより、余分な面積を占有することが
なくなる。Therefore, using pins instead of leads,
A PGA (Pin Grid Array) structure has come to be provided as a package in which these pins are taken out from the bottom surface. LSI with this PGA
According to this, since the plurality of pins are taken out not from the periphery of the package but from the entire surface, it is possible to avoid occupying an extra area by inserting the pins into the mounting board for mounting.
【０００５】このようなＰＧＡにおいて、特にピンを短
く形成して、これらのピンを実装基板に挿入することな
く、その表面に実装するようにした、いわゆる面実装型
のＰＧＡが開発されるようになってきた。このようなＰ
ＧＡは、ショートリード（Ｓｈｏｒｔ ｌｅａｄ）ＰＧ
Ａ、あるいはバットジョイント（Ｂｕｔｔ ｊｏｉｎ
ｔ）ＰＧＡとも称されており、例えば日経ＢＰ社発行、
「ＶＬＳＩパッケージング技術（下）」、１９９３年５
月３１日発行、Ｐ１７３〜Ｐ１７４に記載されている。In such a PGA, a so-called surface mounting type PGA is developed, in which pins are formed particularly short and the pins are mounted on the surface of the mounting substrate without inserting the pins into the mounting substrate. It's coming. Such P
GA is a short lead PG
A, or butt joint
t) Also called PGA, for example, issued by Nikkei BP,
"VLSI Packaging Technology (Bottom)", May 1993.
Issued on March 31, published on pages 173-174.
【０００６】このような面実装型のＰＧＡを有するＬＳ
Ｉによれば、複数のピンは実装基板に挿入されずに半田
付けによって実装基板に面実装されるので、実装基板の
両面を利用することができるため、多ピン化された場合
でも、これらピンを実装基板上へ位置決めするのが容易
になるため、高密度実装に適するようになる。An LS having such a surface mount PGA
According to I, since the plurality of pins are surface-mounted on the mounting board by soldering without being inserted into the mounting board, both sides of the mounting board can be used, and thus even when the number of pins is increased, these pins can be used. Since it becomes easy to position on the mounting substrate, it becomes suitable for high-density mounting.
【０００７】このような面実装型のＰＧＡを有するＬＳ
Ｉにおいて、パッケージの材料としては、セラミック
ス、プラスチック、金属等が用いられており、ピンの材
料としては、Ｆｅ−Ｎｉ系合金のように硬度が高くて変
形しにくい金属が用いられている。一方、ＬＳＩが面実
装される実装基板の材料としては、ベークライト、ガラ
スエポキシ、紙エポキシ等が用いられている。LS having such a surface mount PGA
In I, ceramics, plastics, metals, etc. are used as the material of the package, and a metal having a high hardness and which is hard to be deformed, such as an Fe—Ni alloy, is used as the material of the pin. On the other hand, as the material of the mounting substrate on which the LSI is surface-mounted, bakelite, glass epoxy, paper epoxy or the like is used.
【０００８】[0008]
【発明が解決しようとする課題】前記のような面実装型
のＰＧＡを有するＬＳＩを実装基板に面実装した場合、
パッケージの材料と実装基板の材料との熱膨張係数が異
なるので、時間の経過につれて、パッケージから取り出
されているピンと実装基板との半田接続部（ピンの半田
接続部）がクラックするという問題がある。When an LSI having the above-mentioned surface mounting type PGA is surface mounted on a mounting board,
Since the material of the package and the material of the mounting board have different coefficients of thermal expansion, there is a problem that the solder connection portion (pin solder connection portion) between the pin and the mounting board taken out from the package is cracked over time. .
【０００９】すなわち、ＬＳＩの動作中に熱が発生した
り、あるいは周囲温度が上昇したりすると、これらの温
度変化の繰り返しによって、パッケージと実装基板間の
熱膨張係数の差に基づいて生ずる熱歪が、ピンの半田接
続部に集中するようになるため、この半田接続部が疲労
破断するようになる。これは、より高密度実装を図るた
めにパッケージのサイズを大きくするほど著しくなり、
実装信頼性を低下させることになる。That is, when heat is generated during the operation of the LSI or the ambient temperature rises, the thermal strain caused by the difference in the thermal expansion coefficient between the package and the mounting substrate is caused by the repetition of these temperature changes. However, since it concentrates on the solder connection portion of the pin, the solder connection portion is fatigue fractured. This becomes remarkable as the package size is increased for higher density mounting.
The mounting reliability will be reduced.
【００１０】このようにピンの半田接続部がクラックす
る現象は、実装基板に実装された半導体装置に対して温
度サイクル試験を施すことにより、容易に確認すること
ができる。Such a phenomenon that the solder connection portion of the pin is cracked can be easily confirmed by subjecting the semiconductor device mounted on the mounting substrate to a temperature cycle test.
【００１１】そのような不都合を解決するには、パッケ
ージと実装基板との熱膨張係数を近似させるように材料
を組み合わせれば良いが、これは各々の材料の選択範囲
を制限することになるので好ましくない。また、ピンの
接続部の面積を制限することによって受ける熱歪を軽減
させれば良いが、これはピンの数を制限することになる
ので、実装密度の低下に結びつくため好ましくない。To solve such inconvenience, materials may be combined so as to approximate the thermal expansion coefficient of the package and the mounting board, but this limits the selection range of each material. Not preferable. Further, it is only necessary to reduce the thermal strain received by limiting the area of the connection portion of the pin, but this limits the number of pins, which is not preferable because it leads to a reduction in mounting density.
【００１２】本発明の目的は、パッケージと実装基板と
の熱膨張係数が異なっていても、熱歪を緩和して、ピン
の半田接続部の疲労破断を防止して実装信頼性を向上す
ることが可能な技術を提供することにある。An object of the present invention is to reduce thermal strain even if the package and the mounting substrate have different coefficients of thermal expansion, prevent fatigue breakage of the solder connection portion of the pin, and improve the mounting reliability. Is to provide the technology that can.
【００１３】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１４】[0014]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
【００１５】（１）本発明の半導体装置は、パッケージ
の底面から複数のピンが取り出され、これら複数のピン
がろう材によって実装基板に接続されることにより面実
装される半導体装置において、前記ピン及びろう材はと
もにＰｂ−Ｓｎ合金が用いられて、前記ろう材がピンよ
りも低い融点を有する成分比からなる。(1) In the semiconductor device of the present invention, a plurality of pins are taken out from the bottom surface of the package, and the plurality of pins are surface-mounted by connecting the plurality of pins to a mounting substrate by a brazing material. The Pb-Sn alloy is used for both the brazing material and the brazing material, and the brazing material has a component ratio having a melting point lower than that of the pin.
【００１６】（２）本発明の半導体装置の実装方法は、
表面に半導体チップが固着されるとともに、底面に前記
半導体チップ表面のパッド電極と導通する導電層が形成
されたパッケージを用意する工程と、前記パッケージの
導電層にＰｂ−Ｓｎ合金からなるワイヤの一端を接続し
た後このワイヤを所定の長さに切断してピンを形成する
工程と、前記ピンの他端を前記Ｐｂ−Ｓｎ合金よりも低
い融点を有するＰｂ−Ｓｎ合金からなるろう材によって
実装基板の導電層に接続する工程と、を含んでいる。(2) The method of mounting a semiconductor device according to the present invention is
A step of preparing a package in which a semiconductor chip is fixed to the surface and a conductive layer which is electrically connected to a pad electrode on the surface of the semiconductor chip is formed on the bottom surface; and one end of a wire made of a Pb-Sn alloy in the conductive layer of the package After connecting the wires, the wire is cut into a predetermined length to form a pin, and the other end of the pin is mounted by a brazing material made of a Pb-Sn alloy having a melting point lower than that of the Pb-Sn alloy. Connecting to the conductive layer of.
【００１７】[0017]
【作用】上述した（１）の手段によれば、本発明の半導
体装置は、パッケージの底面から複数のピンが取り出さ
れ、これら複数のピンがろう材によって実装基板に接続
されることにより面実装される半導体装置において、前
記ピン及びろう材はともにＰｂ−Ｓｎ合金が用いられ
て、前記ろう材がピンよりも低い融点を有する成分比か
らなるので、パッケージと実装基板との熱膨張係数が異
なっていても、熱歪を緩和して、ピンの半田接続部の疲
労破断を防止して実装信頼性を向上することが可能とな
る。According to the above-mentioned means (1), in the semiconductor device of the present invention, a plurality of pins are taken out from the bottom surface of the package, and the plurality of pins are connected to the mounting substrate by the brazing material, thereby surface mounting. In the semiconductor device described above, a Pb—Sn alloy is used for both the pin and the brazing filler metal, and the brazing filler metal has a component ratio having a melting point lower than that of the pin, so that the thermal expansion coefficient of the package is different from that of the mounting substrate. However, it is possible to reduce the thermal strain, prevent the fatigue fracture of the solder connection portion of the pin, and improve the mounting reliability.
【００１８】上述した（２）の手段によれば、本発明の
半導体装置の実装方法は、表面に半導体チップが固着さ
れるとともに、底面に前記半導体チップ表面のパッド電
極と導通する導電層が形成されたパッケージを用意する
工程と、前記パッケージの導電層にＰｂ−Ｓｎ合金から
なるワイヤの一端を接続した後このワイヤを所定の長さ
に切断してピンを形成する工程と、前記ピンの他端を前
記Ｐｂ−Ｓｎ合金よりも低い融点を有するＰｂ−Ｓｎ合
金からなるろう材によって実装基板の導電層に接続する
工程と、を含んでいるので、パッケージと実装基板との
熱膨張係数が異なっていても、熱歪を緩和して、ピンの
半田接続部の疲労破断を防止して実装信頼性を向上する
ことが可能となる。According to the above-mentioned means (2), in the method for mounting a semiconductor device of the present invention, the semiconductor chip is fixed to the surface and the conductive layer is formed on the bottom surface to be electrically connected to the pad electrode on the surface of the semiconductor chip. And a step of forming a pin by connecting one end of a wire made of a Pb-Sn alloy to a conductive layer of the package and then cutting the wire into a predetermined length. The step of connecting the end to the conductive layer of the mounting board by a brazing material made of a Pb-Sn alloy having a melting point lower than that of the Pb-Sn alloy, so that the package and the mounting board have different thermal expansion coefficients. However, it is possible to reduce the thermal strain, prevent the fatigue fracture of the solder connection portion of the pin, and improve the mounting reliability.
【００１９】以下、本発明について、図面を参照して実
施例とともに詳細に説明する。Hereinafter, the present invention will be described in detail with reference to the drawings along with embodiments.
【００２０】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００２１】[0021]
【実施例】図１は本発明の実施例による半導体装置を示
す断面図で、ＬＳＩに適用した例で示している。本実施
例の半導体装置は、ベース基板１の表面にＬＳＩチップ
２がＡｇろうのようなろう材で固着され、チップ２の表
面に形成されている複数のパッド電極３とベース基板１
の表面に形成されている導電層４間には、各々Ａｕ線の
ようなワイヤ５がボンディングされている。ベース基板
１にはスルーホール（図示せず）が設けられており、各
導電層４はスルーホール配線を介してベース基板１の底
面に形成されている複数の導電層６と導通している。Ｌ
ＳＩチップ２、ボンディングワイヤ５及びベース基板１
の表面は例えばエポキシ樹脂のような樹脂体７によって
覆われ、この樹脂体７及びベース基板１はパッケージ８
を構成している。1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, which is an example applied to an LSI. In the semiconductor device of this embodiment, the LSI chip 2 is fixed to the surface of the base substrate 1 with a brazing material such as Ag solder, and the plurality of pad electrodes 3 formed on the surface of the chip 2 and the base substrate 1 are formed.
A wire 5 such as an Au wire is bonded between the conductive layers 4 formed on the surface of each. Through holes (not shown) are provided in the base substrate 1, and each conductive layer 4 is electrically connected to a plurality of conductive layers 6 formed on the bottom surface of the base substrate 1 via through hole wiring. L
SI chip 2, bonding wire 5, and base substrate 1
Is covered with a resin body 7 such as an epoxy resin, and the resin body 7 and the base substrate 1 are package 8
Is composed.
【００２２】ベース基板１の底面の複数の導電層６は例
えばＡｕ層からなり、各導電層６にはＰｂ−Ｓｎ合金か
らなるピン９がその一端を接続することにより取り出さ
れている。各ピン９は柔軟性に富んだ、例えばＰｂ：９
０％とＳｎ：１０％との成分比からなるＰｂ−Ｓｎ合金
（融点：約２２７℃）が用いられている。各ピン６は後
述のような方法によって各導電層６に接続される。The plurality of conductive layers 6 on the bottom surface of the base substrate 1 are made of, for example, Au layers, and a pin 9 made of a Pb-Sn alloy is taken out from each conductive layer 6 by connecting one end thereof. Each pin 9 is highly flexible, for example Pb: 9
A Pb—Sn alloy (melting point: about 227 ° C.) having a composition ratio of 0% and Sn: 10% is used. Each pin 6 is connected to each conductive layer 6 by a method described later.
【００２３】一方、各ピン９の他端はこのピン９よりも
低い融点を有する成分比のＰｂ−Ｓｎ合金からなるろう
材１０によって、実装基板１１の導電層１２に接続され
ている。ろう材１０は例えばＰｂ：４０％とＳｎ：６０
％との成分比からなる合金（融点：約１８３℃）が用い
られる。以上のようにして、半導体装置は実装基板１１
に面実装される。On the other hand, the other end of each pin 9 is connected to the conductive layer 12 of the mounting substrate 11 by a brazing material 10 made of a Pb-Sn alloy having a composition ratio lower than that of the pin 9. The brazing material 10 is, for example, Pb: 40% and Sn: 60
An alloy (melting point: about 183 ° C.) having a composition ratio of 100% is used. As described above, the semiconductor device is mounted on the mounting substrate 11
Surface mounted.
【００２４】ベース基板１の材料としては、セラミック
ス、プラスチック、金属等が用いられており、また、実
装基板１１の材料としては、ベークライト、ガラスエポ
キシ、紙エポキシ等が用いられている。Ceramics, plastics, metals, etc. are used as the material of the base substrate 1, and bakelite, glass epoxy, paper epoxy, etc. are used as the material of the mounting substrate 11.
【００２５】次に、本実施例の半導体装置の実装方法を
説明する。Next, a method of mounting the semiconductor device of this embodiment will be described.
【００２６】まず、図２に示すように、予め表面に複数
の導電層４とともに、底面に各導電層４と導通する導電
層６が形成されたベース基板１を用意して、表面に複数
のパッド電極３が形成されているＬＳＩチップ２をＡｇ
のようなろう材でその表面に固着する。First, as shown in FIG. 2, a base substrate 1 having a plurality of conductive layers 4 formed on its surface and a conductive layer 6 electrically connected to each conductive layer 4 on its bottom surface is prepared in advance, and a plurality of surfaces are formed on the surface. Ag of the LSI chip 2 on which the pad electrode 3 is formed
Stick to the surface with a brazing material such as.
【００２７】次に、図３に示すように、ＬＳＩチップ２
の表面の複数のパッド電極３とベース基板１の対応する
導電層４間にＡｕ線のようなワイヤ５をボンディングす
る。Next, as shown in FIG. 3, the LSI chip 2
A wire 5 such as an Au wire is bonded between the plurality of pad electrodes 3 on the surface of and the corresponding conductive layer 4 of the base substrate 1.
【００２８】続いて、図４に示すように、ＬＳＩチップ
２、ボンディングワイヤ５及びベース基板１の表面にエ
ポキシ樹脂をトランスファモールドして、樹脂体７によ
って覆う。これによってパッケージ８を構成する。Subsequently, as shown in FIG. 4, epoxy resin is transfer-molded on the surfaces of the LSI chip 2, the bonding wires 5 and the base substrate 1 and covered with a resin body 7. This constitutes the package 8.
【００２９】次に、図５に示すように、例えばＰｂ：９
０％とＳｎ：１０％との成分比からなるＰｂ−Ｓｎ合金
（融点：約２２７℃）のワイヤ１３を用いて、このワイ
ヤ１３をキャピラリー１４によって供給して、ベース基
板１の底面の各導電層６に対して接続することにより、
ピン９を形成する。ワイヤ１３の接続は次のようにして
行われる。Next, as shown in FIG. 5, for example, Pb: 9.
A wire 13 made of a Pb—Sn alloy (melting point: about 227 ° C.) having a composition ratio of 0% and Sn: 10% is used, and this wire 13 is supplied by a capillary 14 so that each conductive layer on the bottom surface of the base substrate 1 is electrically conductive. By connecting to layer 6,
Form the pin 9. The wire 13 is connected as follows.
【００３０】まず、図６（ａ）に示すように、キャピラ
リー１４からワイヤ１３の先端を引き出した状態で、図
６（ｂ）に示すように、この先端をバーナー等によって
ワイヤ１３の融点以上の温度で加熱して溶融させて、球
状部１３Ａを形成する。次に、図６（ｃ）に示すよう
に、キャピラリー１４によってワイヤ１３を下降させ
て、その球状部１３Ａをベース基板１の導電層６に接触
させて、キャピラリー１４によって熱圧着させるととも
に超音波ボンディングを行って接続する。この方法によ
れば、柔軟性に富んだワイヤ１３の特性を利用して、ま
た酸化による影響を除いて、ワイヤ１３を安定にベース
基板１の導電層６に接続することができる。First, as shown in FIG. 6 (a), with the tip of the wire 13 pulled out from the capillary 14, as shown in FIG. 6 (b), this tip is heated to a temperature above the melting point of the wire 13 by a burner or the like. The spherical portion 13A is formed by heating and melting at a temperature. Next, as shown in FIG. 6C, the wire 13 is lowered by the capillary 14, the spherical portion 13A is brought into contact with the conductive layer 6 of the base substrate 1, and thermocompression bonding is performed by the capillary 14 and ultrasonic bonding is performed. And connect. According to this method, the wire 13 can be stably connected to the conductive layer 6 of the base substrate 1 by utilizing the characteristics of the wire 13 having high flexibility and removing the influence of oxidation.
【００３１】続いて、図６（ｄ）に示すように、キャピ
ラリー１４を一定高さに上昇させた後、図６（ｅ）に示
すように、カッター１５によってワイヤ１３を切断す
る。これにより、各導電層６に一端が接続された所定の
長さのピン９が、図５のように得られる。Subsequently, as shown in FIG. 6 (d), the capillary 14 is raised to a certain height, and then the wire 13 is cut by the cutter 15 as shown in FIG. 6 (e). As a result, a pin 9 having a predetermined length, one end of which is connected to each conductive layer 6, is obtained as shown in FIG.
【００３２】次に、図７に示すように、予め例えばＰ
ｂ：４０％とＳｎ：６０％との成分比からなるＰｂ−Ｓ
ｎ合金（融点：約１８３℃）のペースト１６を、表面に
Ａｕのような導電層１２を介してスクリーン印刷した実
装基板１１を用意する。Next, as shown in FIG. 7, for example, P
b: 40% and Sn: 60% Pb-S composed of the composition ratio
An n-alloy (melting point: about 183 ° C.) paste 16 is screen-printed on the surface via a conductive layer 12 such as Au to prepare a mounting substrate 11.
【００３３】続いて、図８に示すように、そのような実
装基板１１の上方にパッケージ８を配置して、各ピン９
の他端を各ペースト１６上に位置決めした状態で、実装
基板１１をリフロー炉内を通過させて加熱処理を行っ
て、ペースト１６をろう材１０となして各ピン９を前記
した成分比のＰｂ−Ｓｎ合金によって、いわゆる半田付
けによって接続する。このとき、リフロー炉による加熱
処理の温度は、ろう材１０の融点（約１８３℃）以上
で、かつピン９の融点（約２２７℃）以下に設定するよ
うにする。これによって、各ピン９の半田付け時にピン
９自身の溶融を避けることができる。以上によって、実
装基板１１上に面実装された図１のような半導体装置を
得ることができる。Subsequently, as shown in FIG. 8, the package 8 is arranged above the mounting board 11 and each pin 9 is arranged.
In a state where the other end of each is positioned on each paste 16, the mounting substrate 11 is passed through a reflow furnace to be subjected to heat treatment, and the paste 16 serves as a brazing material 10 to form each pin 9 in the Pb of the above-mentioned component ratio. -Sn alloy is used for connection by so-called soldering. At this time, the temperature of the heat treatment by the reflow furnace is set to the melting point of the brazing filler metal 10 (about 183 ° C.) or higher and the melting point of the pin 9 (about 227 ° C.) or lower. This makes it possible to avoid melting of the pins 9 themselves when soldering the pins 9. As described above, the semiconductor device as shown in FIG. 1 which is surface-mounted on the mounting substrate 11 can be obtained.
【００３４】このような面実装構造によれば、パッケー
ジ８と実装基板１１との熱膨張係数が異なっていても、
ＬＳＩの動作中に熱が発生したり、あるいは周囲温度が
上昇したりして、パッケージ８と実装基板１１間の熱膨
張係数の差に基づいて熱歪が生じても、ピン９が柔軟性
に富んだＰｂ−Ｓｎ合金からなるため、熱歪はこのピン
９によって吸収されるようになる。この結果、熱歪は緩
和されてピン９の先端部分の半田接続部には集中しない
ので、このピン９の半田接続部に疲労破断は生じない。
これによって、実装信頼性を向上することができるの
で、パッケージのサイズを大きくしてより高密度実装を
図ることが可能となる。According to such a surface mounting structure, even if the thermal expansion coefficients of the package 8 and the mounting substrate 11 are different,
Even if heat is generated during the operation of the LSI or the ambient temperature rises and thermal strain occurs due to the difference in the coefficient of thermal expansion between the package 8 and the mounting substrate 11, the pin 9 becomes flexible. Since it is made of a rich Pb-Sn alloy, thermal strain is absorbed by the pin 9. As a result, the thermal strain is alleviated and is not concentrated on the solder connection portion of the tip portion of the pin 9, so that the solder connection portion of the pin 9 is not fatigue fractured.
As a result, the mounting reliability can be improved, and the package size can be increased to achieve higher density mounting.
【００３５】このような本実施例によれば次のような効
果が得られる。According to this embodiment, the following effects can be obtained.
【００３６】（１）パッケージ８の底面から取り出され
た複数のピン９は、柔軟性に富んだＰｂ−Ｓｎ合金から
なり、各ピン９はこれよりも低い融点を有するＰｂ−Ｓ
ｎ合金からなるろう材１０によって実装基板１１に接続
されるので、熱歪が発生してもピン９によって吸収され
るようになるため、パッケージ８と実装基板１１との熱
膨張係数が異なっていても、熱歪を緩和して、ピンの半
田接続部の疲労破断を防止して実装信頼性を向上するこ
とが可能となる。(1) The plurality of pins 9 taken out from the bottom surface of the package 8 are made of a highly flexible Pb-Sn alloy, and each pin 9 has a melting point lower than that of Pb-S.
Since it is connected to the mounting board 11 by the brazing material 10 made of an n alloy, the thermal expansion coefficient is absorbed by the pin 9 even if thermal strain occurs, so that the package 8 and the mounting board 11 have different thermal expansion coefficients. Also, it becomes possible to alleviate thermal strain, prevent fatigue fracture of the solder connection part of the pin, and improve the mounting reliability.
【００３７】（２）パッケージ８の底面から引き出した
Ｐｂ−Ｓｎ合金からなる各ピン９を、ピン９より低い融
点を有するＰｂ−Ｓｎ合金からなるろう材１０によって
実装基板１１に接続するので、ピン９を溶融させること
なく接続することができるため、ピン９の柔軟性を損な
うことなく半導体装置を面実装することができる。(2) Since each pin 9 made of Pb-Sn alloy extracted from the bottom surface of the package 8 is connected to the mounting board 11 by the brazing material 10 made of Pb-Sn alloy having a lower melting point than the pin 9, Since 9 can be connected without melting, the semiconductor device can be surface-mounted without impairing the flexibility of the pin 9.
【００３８】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００３９】例えば、前記実施例では、ピン及びろう材
に用いるＰｂ−Ｓｎ合金の成分比は一例を示したが、こ
の例に限らず、ろう材がピンよりも低い融点を有する成
分比のＰｂ−Ｓｎ合金からなっていれば良い。その望ま
しい範囲としては、ろう材においてはほぼ８５％以下の
Ｐｂ成分を有するＰｂ−Ｓｎ合金を、ピンにおいてはほ
ぼ８５％以上のＰｂ成分を有するＰｂ−Ｓｎ合金をあげ
ることができる。For example, in the above embodiment, the component ratio of the Pb-Sn alloy used for the pin and the brazing filler metal is shown as an example, but the present invention is not limited to this example, and the brazing filler metal has a melting point lower than that of the pin. It may be made of --Sn alloy. Preferable ranges include a Pb-Sn alloy having a Pb content of about 85% or less in the brazing material and a Pb-Sn alloy having a Pb content of about 85% or more in the pin.
【００４０】また、前記実施例ではパッケージ及び実装
基板の各材料としては特定の材料に例をあげて説明した
が、これに限らず同等の材料を用いることができる。Further, in the above-described embodiment, the material of each of the package and the mounting substrate has been described by taking a specific material as an example. However, the material is not limited to this and equivalent materials can be used.
【００４１】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である面実装
型のＰＧＡを有する半導体装置に適用した場合について
説明したが、それに限定されるものではない。本発明
は、少なくともピンの半田接続部の破断を改善すること
を目的とする条件のものには適用できる。In the above description, the case where the invention made by the present inventor is mainly applied to a semiconductor device having a surface mounting type PGA, which is a field of application which is the background of the invention, has been described, but the invention is not limited thereto. . INDUSTRIAL APPLICABILITY The present invention can be applied to at least the condition for improving the breakage of the solder connection portion of the pin.
【００４２】[0042]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００４３】（１）パッケージの底面から取り出された
複数のピンは、柔軟性に富んだＰｂ−Ｓｎ合金からなる
ので、熱歪が発生してもピンによって吸収されるように
なるため、パッケージと実装基板との熱膨張係数が異な
っていても、熱歪を緩和して、ピンの半田接続部の疲労
破断を防止して実装信頼性を向上することが可能とな
る。(1) Since the plurality of pins taken out from the bottom surface of the package are made of a highly flexible Pb-Sn alloy, they are absorbed by the pins even if thermal strain occurs, so that the pins are not packaged. Even if the coefficient of thermal expansion is different from that of the mounting board, it is possible to alleviate thermal strain, prevent fatigue fracture of the solder connection portion of the pin, and improve mounting reliability.
【００４４】（２）パッケージの底面から引き出したＰ
ｂ−Ｓｎ合金からなる各ピンを、ピンより低い融点を有
するＰｂ−Ｓｎ合金からなるろう材によって実装基板に
接続するので、ピンの柔軟性を損なうことなく半導体装
置を面実装することができる。(2) P drawn from the bottom of the package
Since each pin made of the b-Sn alloy is connected to the mounting board by the brazing material made of the Pb-Sn alloy having a melting point lower than that of the pin, the semiconductor device can be surface-mounted without impairing the flexibility of the pin.
【図１】本発明の実施例による半導体装置を示す断面図
である。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施例による半導体装置の実装方法の
一工程を示す断面図である。FIG. 2 is a cross-sectional view showing a step of the method for mounting the semiconductor device according to the embodiment of the present invention.
【図３】本発明の実施例による半導体装置の実装方法の
他の工程を示す断面図である。FIG. 3 is a cross-sectional view showing another step of the method for mounting the semiconductor device according to the embodiment of the present invention.
【図４】本発明の実施例による半導体装置の実装方法の
その他の工程を示す断面図である。FIG. 4 is a cross-sectional view showing another step of the method for mounting a semiconductor device according to the example of the present invention.
【図５】本発明の実施例にによる半導体装置の実装方法
のその他の工程を示す断面図である。FIG. 5 is a cross-sectional view showing another step of the method for mounting a semiconductor device according to the example of the present invention.
【図６】本発明の実施例による半導体装置の実装方法の
その他の工程を示すもので、（ａ）乃至（ｅ）は断面図
である。FIG. 6 shows another step of the method for mounting a semiconductor device according to the embodiment of the present invention, in which (a) to (e) are sectional views.
【図７】本発明の実施例による半導体装置の実装方法の
その他の工程を示す断面図である。FIG. 7 is a cross-sectional view showing another step of the method for mounting a semiconductor device according to the example of the present invention.
【図８】本発明の実施例による半導体装置の実装方法の
その他の工程を示す断面図である。FIG. 8 is a cross-sectional view showing another step of the method for mounting a semiconductor device according to the example of the present invention.
１…ベース基板、２…ＬＳＩチップ、３…パッド電極、
４、６…ベース基板の導電層、５…ボンディングワイ
ヤ、７…樹脂体、８…パッケージ、９…ピン、１０…Ｐ
ｂ−Ｓｎ合金からなるろう材、１１…実装基板、１２…
実装基板の導電層、１３…Ｐｂ−Ｓｎ合金からなるワイ
ヤ、１３Ａ…ワイヤの球状部、１４…キャピラリー、１
５…カッター、１６…ペースト。1 ... Base substrate, 2 ... LSI chip, 3 ... Pad electrode,
4, 6 ... Conductive layer of base substrate, 5 ... Bonding wire, 7 ... Resin body, 8 ... Package, 9 ... Pin, 10 ... P
Brazing material made of b-Sn alloy, 11 ... Mounting substrate, 12 ...
Conductive layer of mounting substrate, 13 ... Wire made of Pb—Sn alloy, 13A ... Wire spherical portion, 14 ... Capillary, 1
5 ... Cutter, 16 ... Paste.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 三輪 孝志 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Miwa 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center
Claims (5)
出され、これら複数のピンがろう材によって実装基板に
接続されることにより面実装される半導体装置におい
て、前記ピン及びろう材はともにＰｂ−Ｓｎ合金が用い
られて、前記ろう材がピンよりも低い融点を有する成分
比からなることを特徴とする半導体装置。1. In a semiconductor device in which a plurality of pins are taken out from the bottom surface of a package and are surface-mounted by connecting the plurality of pins to a mounting substrate by a brazing material, the pins and the brazing material are both Pb-Sn. A semiconductor device, wherein an alloy is used, and the brazing material has a composition ratio having a melting point lower than that of the pin.
いＰｂ−Ｓｎ合金が用いられることを特徴とする請求項
１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the brazing material is a Pb—Sn alloy having a Pb component smaller than that of the pin.
を有するＰｂ−Ｓｎ合金が用いられるとともに、前記ピ
ンはほぼ８５％以上のＰｂ成分を有するＰｂ−Ｓｎ合金
が用いられることを特徴とする請求項１または２に記載
の半導体装置。3. The brazing material is made of a Pb-Sn alloy having a Pb content of about 85% or less, and the pin is made of a Pb-Sn alloy having a Pb content of about 85% or more. The semiconductor device according to claim 1 or 2.
に、底面に前記半導体チップ表面のパッド電極と導通す
る導電層が形成されたパッケージを用意する工程と、前
記パッケージの導電層にＰｂ−Ｓｎ合金からなるワイヤ
の一端を接続した後このワイヤを所定の長さに切断して
ピンを形成する工程と、前記ピンの他端を前記Ｐｂ−Ｓ
ｎ合金よりも低い融点を有するＰｂ−Ｓｎ合金からなる
ろう材によって実装基板の導電層に接続する工程と、を
含むことを特徴とする半導体装置の実装方法。4. A step of preparing a package in which a semiconductor chip is fixed to a surface and a conductive layer which is electrically connected to a pad electrode on the surface of the semiconductor chip is formed on a bottom surface, and a Pb-Sn alloy is formed on the conductive layer of the package. A step of connecting one end of a wire made of Pb-S to a wire and cutting the wire into a predetermined length to form a pin;
and a step of connecting to a conductive layer of a mounting substrate with a brazing material made of a Pb-Sn alloy having a melting point lower than that of the n alloy.
金からなるワイヤの一端を超音波ボンディングによって
接続することを特徴とする請求項４に記載の半導体装置
の実装方法。5. The method for mounting a semiconductor device according to claim 4, wherein one end of a wire made of a Pb—Sn alloy is connected to the conductive layer of the package by ultrasonic bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7043061A JPH08241950A (en) | 1995-03-02 | 1995-03-02 | Semiconductor device and its mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7043061A JPH08241950A (en) | 1995-03-02 | 1995-03-02 | Semiconductor device and its mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08241950A true JPH08241950A (en) | 1996-09-17 |
Family
ID=12653358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7043061A Pending JPH08241950A (en) | 1995-03-02 | 1995-03-02 | Semiconductor device and its mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08241950A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011105598A1 (en) * | 2010-02-24 | 2011-09-01 | 千住金属工業株式会社 | Copper column and process for producing same |
| US9491859B2 (en) | 2012-05-23 | 2016-11-08 | Massachusetts Institute Of Technology | Grid arrays with enhanced fatigue life |
-
1995
- 1995-03-02 JP JP7043061A patent/JPH08241950A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011105598A1 (en) * | 2010-02-24 | 2011-09-01 | 千住金属工業株式会社 | Copper column and process for producing same |
| JP2011176124A (en) * | 2010-02-24 | 2011-09-08 | Senju Metal Ind Co Ltd | Copper column and method of manufacturing the same |
| US8841559B2 (en) | 2010-02-24 | 2014-09-23 | Senju Metal Industry Co., Ltd. | Copper column |
| US9491859B2 (en) | 2012-05-23 | 2016-11-08 | Massachusetts Institute Of Technology | Grid arrays with enhanced fatigue life |
| US10433429B2 (en) | 2012-05-23 | 2019-10-01 | Massachusetts Institute Of Technology | Method of enhancing fatigue life of grid arrays |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6091141A (en) | Bump chip scale semiconductor package | |
| KR100239406B1 (en) | Surface mounted semiconductor package and method of manufacturing the same | |
| US6164523A (en) | Electronic component and method of manufacture | |
| US5976964A (en) | Method of improving interconnect of semiconductor device by utilizing a flattened ball bond | |
| US7449786B2 (en) | Semiconductor device having improved adhesion between bonding and ball portions of electrical connectors | |
| JPH02123685A (en) | Method of bonding wire containing gold with solder | |
| US6921016B2 (en) | Semiconductor device and method of manufacturing the same, circuit board, and electronic equipment | |
| KR970018287A (en) | Semiconductor Chip Bonding Device | |
| JPH08510358A (en) | Interconnection of integrated circuit chips and substrates | |
| JP3851797B2 (en) | Ball grid array package and circuit board used therefor | |
| JP2007504648A (en) | Capillary used for wire bonding and wire bonding of insulated wires | |
| JPH11121543A (en) | Chip scale package | |
| JP3550355B2 (en) | Pin standing board | |
| JPH08241950A (en) | Semiconductor device and its mounting method | |
| JP3887993B2 (en) | Connection method between IC chip and circuit board | |
| JPH0150108B2 (en) | ||
| JPH1084011A (en) | Semiconductor device, manufacture thereof and semiconductor device mounting method | |
| JP3997665B2 (en) | Connection method between semiconductor element and circuit board | |
| JPS62150836A (en) | Semiconductor device | |
| JP3210456B2 (en) | Method of forming ball on metal wire | |
| JPH05326601A (en) | Wire bonding method | |
| TWI508248B (en) | Copper on organic solderability preservative (osp) interconnect and enhanced wire bonding process | |
| JPH1050915A (en) | Semiconductor device and its manufacture | |
| JPH08195466A (en) | Semiconductor device | |
| JPH09148334A (en) | Bump, semiconductor chip, package having the bumps, mounting method and semiconductor device |