JPH08240645A - Circuit for reading internal state of ic and testing it by small number of pins - Google Patents

Abstract

PURPOSE: To realize a circuit which reads out the internal state of the high-speed IC by a small number of pins and makes a test by the large-capacity IC by providing a low-cost large capacity test IC on one side, and a purposed-function high-speed IC on the other side. CONSTITUTION: In addition to a purposed-function circuit, high-speed IC, having a built-in scan chain circuit 210 wherein registers in the IC are connected like shift registers in a scan mode and the contents of the registers are outputted one by one as data signals in series synchronously with a scan clock, is provided on one side. Besides, large-capacity IC having, as built-in components, a shift register 110 for holding data which fetches data signals at a shift register clock, a bus circuit 120 which delivers an output of this shift register to but readout data in conformity with a bus-machine word for specifying a range of readout and a scan chain circuit control part 130 which generates the scan mode, the scan clock and the shift register clock being synchronous, is provided on the other side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a test bus circuit built in one side and a low cost IC for checking the contents of the register of the IC having the built-in target function, and the other side having the target function. The present invention relates to a circuit for reading and testing the internal state of an IC with a small number of pins, which is provided with a high-speed IC capable of reading the contents of the register of the IC with a small number of pins.

[0002]

2. Description of the Related Art When designing a circuit for making an IC by using a gate array, it is necessary to provide a test circuit for testing a target circuit in addition to a circuit for realizing a target function. There is. As a test circuit, a circuit configuration is generally used in which the output of a register used in a target circuit is output to a bus line through a gate, and the contents of the bus line are output from pins of an IC for testing. ing.

[0003]

When the test circuit as described above is built in an IC for realizing a desired function requiring high-speed operation, the number of pins of the IC increases due to the bus line. The circuit scale becomes large because of the test circuit. In general, since a gate array that operates at high speed is expensive, it is appropriate to use the gate array with a number of gates within about 2000 gates and a smaller number of pins. Therefore, for circuits that require high-speed operation, use a high-speed gate array,
A circuit that does not require high-speed operation but has a large circuit scale and uses a large number of IC pins, for example, a test circuit,
Although it cannot operate at high speed, it is suitable to be built in a part of the gate array which is cheap, for example, about 500,000 gates. The present invention uses a plurality of gate arrays to provide a low-cost large-capacity IC for testing on one side and a target function on the other side in order to realize a circuit requiring high-speed operation at a low cost. It is an object of the present invention to provide a high-speed IC having a built-in IC, and to realize a circuit for reading the internal state of the high-speed IC with a small number of pins and testing with a large-capacity IC.

[0004]

In order to achieve the above object, the present invention is as follows. That is,
In addition to the circuit for the desired function, the registers used in the IC are linked like a shift register in the scan mode, and the contents of the registers are serialized as serial data signals in synchronization with the scan clock. A high-speed IC containing the output scan chain circuit 210 is provided on one side. Further, the data holding shift register 110 that takes in the data signal output from the high-speed IC with the shift register clock generated based on the bus clock synchronized with the scan clock, and the output range of the data holding shift register 110 A bus circuit 120 that outputs bus read data in accordance with a bus machine word that specifies a scan machine circuit, and a scan chain circuit control unit 130 that generates a scan mode, a scan clock, and a shift register clock that operate in synchronization with the bus clock as a basic clock. A built-in large-capacity IC is provided on the other side.

The scan chain circuit 210 incorporated in the high-speed IC connects a plurality of registers 211, 212, and 21m forming a circuit for a desired function like one shift register, so that each register is connected. A signal for a desired function and an output of a register to be connected or an output of the most advanced register 211 for the last register 21m are input to the data input, and selected by a scan mode signal and input to each register. Multiplexers 221, 222, and 22m are provided, and a clock signal for a desired function and a scan clock signal for performing a shift operation of a register to be connected are input to the clock input of each register and selected by a scan mode signal. Multiplexers 231, 232, 2 input to each register
3m is provided and the most advanced register 2 in scan mode
A gate 241 for outputting the output of 11 as a data signal to the output terminal of the high speed IC is provided.

The data holding shift register 110 incorporated in the large-capacity IC takes in the data signal output from the high-speed IC at the shift register clock which operates in synchronization with the scan clock using the bus clock as the basic clock. A register 111 at the front end is provided, and except for the register 11m at the rear end, registers 111, 112, and 11m that perform a shift operation with a shift register clock as an input of the next register in which the outputs of the registers 111 and 112 are connected.
Is provided.

It should be noted that the high-speed IC is a high-speed gate array 200
The large capacity IC may be the large capacity gate array 100.

[0008]

In the circuit for reading out and testing the internal state of the IC with a small number of pins as described above, the method of outputting the output of the register in the high speed IC to the bus line through the gate as in the conventional circuit is The number of output pins required for the number of bits of the line is only one data signal pin that outputs the contents of the register in series. By reducing the number of pins used in the high-speed IC, the package can be made smaller and the price can be reduced. There is. In addition, by incorporating a test circuit that can operate at low speed in a low-priced large-capacity IC, the capacity (scale) of the high-priced high-speed IC can be reduced, and the combined price of the large-capacity IC and the high-speed IC can be reduced. It has a reducing effect. In addition, the scan chain circuit is built into the high-speed IC,
By looping the scan chain, the internal register state can be returned to the original state without externally supplying data, and pins for supplying external data are not required, so the package can be made smaller. , It has the effect of reducing the price. In addition, high-speed IC and large capacity I
There are three input / output pins between C, scan mode, scan clock, and data, which have the effect of reducing the package size and cost. Further, by providing a scan chain circuit control unit, a data holding shift register for holding read data of the high speed IC and a bus circuit for reading the contents of the data holding shift register in the large capacity IC, the large capacity IC and the high speed IC can be realized. It has the effect of reducing the combined price and realizing a read circuit for the internal state of a high-speed IC.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit block diagram of the present invention. The circuit shown here is in addition to the circuit for the intended function,
A high-speed gate including a scan chain circuit 210 in which the registers used in the IC are connected like a shift register in the scan mode, and the contents of the registers are sequentially output as serial data signals in synchronization with the scan clock. The array 200 is provided, and the high speed gate array 200 is provided.
A data holding shift register 110 that takes in a data signal output from the device with a shift register clock generated based on a bus clock that is synchronized with a scan clock, and a bus that specifies an output range of the data holding shift register 110 A large capacity that includes a bus circuit 120 that outputs bus read data according to a machine word and a scan chain circuit control unit 130 that generates a scan mode, a scan clock, and a shift register clock that operate in synchronization with the bus clock as a basic clock. A gate array 100 is provided and configured.

FIG. 2 shows a detailed block diagram of the present invention.
Among them, the scan chain circuit 210 incorporated in the high-speed gate array 200 is composed of a plurality of registers 211, 212, 21m forming a circuit for a desired function.
To connect like a shift register, the data input of each register, the signal for the intended function,
For the output of the register to be connected or the last register 21m, the output of the most advanced register 211 is used as an input, and multiplexers 221, 222, 22m for selecting the scan mode signal and inputting to each register are provided, and the clock input of each register is provided. In addition, a multiplexer 23 that receives a clock signal for a desired function and a scan clock signal for executing a shift operation of a register to be connected, selects a scan mode signal and inputs the selected signal to each register 23
1, 232, and 23m are provided, and a gate 241 is provided which outputs the output of the most advanced register 211 as a data signal to the output terminal of the high speed gate array 200 in the scan mode.

On the other hand, the data holding shift register 110 built in the large-capacity gate array 100 operates in synchronization with the scan clock by using the data signal output from the high-speed gate array 200 with the bus clock as the basic clock. A state-of-the-art register 111 that captures at the shift register clock is provided, except for the last register 11m,
Registers 111, 112, and 11m that perform a shift operation with a shift register clock are provided as inputs to the next register that connects the outputs of the registers 111 and 112.

The operation of the above circuit will be described with reference to a timing chart in FIG. The high speed gate array 200 stops the circuit for the intended function before the scan operation to be performed below. Large-capacity gate array 1 by bus machine word
A request to start scanning is input to 00. The scan chain control circuit 130 of the large capacity gate array 100 sends to the high speed gate array 200 a scan mode signal indicating that a scan operation is being executed and a data signal as a scan result. A scan clock signal that specifies the output timing is output. In the high speed gate array 200, the scan mode signal and the scan clock signal are used to independently connect unrelated internal registers in series and operate them independently, and output the contents as a data signal to the large capacity gate array 100. When the internal registers of the high speed gate array 200 are connected in series, the output of the most advanced register 211 is output as a data signal and at the same time the last register 21 is output.
Since the registers are connected in a loop state because they are connected as the data input of m, when the outputs of the data signals of all the registers are completed, the state of each register returns to the state before the data reading. The large capacity gate array 100 reads the output data signal of the high speed gate array 200 into the data holding shift register 110 at the shift register clock synchronized with the scan clock. The large-capacity gate array 100 outputs the contents of the registers of the high-speed gate array 200, which are read in series, as parallel data, and outputs the data in parallel as bus read data according to a bus machine word that specifies a reading range.

In the above description, one of the high-speed gate arrays 200 has a relatively low price and does not operate at a high speed, and the other has a high-speed gate array 200 that has a relatively high price and a small capacity.
However, the present invention is not limited to a gate array, and one of them is a large-capacity IC which is relatively low price but not high speed, and the other is a high-speed IC which is relatively high price but small capacity. As a whole, it is possible to combine both of them in a well-balanced manner to provide an overall IC that realizes a low-cost, high-speed, large-capacity circuit configuration as a whole.

[0014]

Since the present invention is configured as described above, it has the following effects. That is, in a circuit for reading and testing the internal state of the IC of the present invention with a small number of pins, a high-speed IC like a conventional circuit is used.
In the method of outputting the output of the register inside to the bus line through the gate, the number of output pins required for the number of bits of the bus line is only one data signal pin that outputs the contents of the register in series. By reducing the number of pins used in the IC, the size of the package can be reduced and the cost can be reduced. In addition, by incorporating a test circuit that can operate at low speed in a low-priced large-capacity IC, it is possible to reduce the capacity (scale) of the high-priced high-speed IC.
It has the effect of reducing the combined price. Further, the high-speed IC has a built-in scan chain circuit, and by looping the scan chain, the internal register state can be returned to the original state without giving data from the outside. Since there is no need for a pin to give a package, it has an effect of reducing the package size and the price. The number of input / output pins between the high-speed IC and the large-capacity IC is three, that is, the scan mode, the scan clock, and the data, which has the effect of reducing the package size and cost. Further, by providing a scan chain circuit control unit, a data holding shift register for holding read data of the high speed IC and a bus circuit for reading the contents of the data holding shift register in the large capacity IC, the large capacity IC and the high speed IC can be realized. This has the effect of reducing the combined price and realizing a read circuit for the internal state of a high-speed IC.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of the present invention.

FIG. 2 is a detailed block diagram of the present invention.

FIG. 3 is a timing diagram of an embodiment of the present invention.

[Explanation of symbols]

100 Large-capacity gate array 110 Data holding shift register 111, 112, 11m, 211, 212, 21m
Register 120 Bus circuit 130 Scan chain circuit control unit 200 High speed gate array 210 Scan chain circuit 221, 222, 22m, 231, 232, 23m
Multiplexer 241 gate

Claims (4)

[Claims] 1. In addition to a circuit for a desired function,
Registers used in the IC are connected in the scan mode like a shift register, and a scan chain circuit (210) that outputs the contents of the registers as serial data signals one after another in synchronization with the scan clock is incorporated. A high-speed IC is provided, and a data holding shift register (1) that takes in a data signal output from the high-speed IC with a shift register clock generated based on a bus clock synchronized with a scan clock
10) and a bus circuit (12) for outputting the output of the data holding shift register (110) to bus read data according to a bus machine word designating a reading range.
0) and a scan chain circuit control unit (130) that generates a scan mode, a scan clock and a shift register clock that operate in synchronization with a bus clock as a basic clock, and a large-capacity IC is provided. A circuit for reading and testing the internal state of the IC with a small number of pins. 2. A scan chain circuit (210) built in a high speed IC connects a plurality of registers (211, 212, 21m) forming a circuit for a desired function like one shift register. In order to do so, the data input of each register is connected to the signal for the intended function and the output of the register to be connected or the last register (21m).
For the above, a multiplexer (221, 222, 22m) for selecting the scan mode signal and inputting to each register is provided with the output of the most advanced register (211) as an input, and the clock input of each register has the desired function. For inputting the clock signal for scanning and the scan clock signal for executing the shift operation of the register to be connected, the multiplexer (231, 232, 23m) for selecting the scan mode signal and inputting to each register is provided. The gate (241) for outputting the output of the register (211) at the tip as a data signal to the output terminal of the high-speed IC is provided, and the internal state of the IC according to claim 1 is read by a few pins. The circuit to test. 3. A shift register (110) for holding data, which is built in a large capacity IC, operates a data signal output from a high speed IC in synchronization with a scan clock using a bus clock as a basic clock. A state-of-the-art register (111) that captures with a clock is provided, and each register (11
A register (111, 112, 11m) that performs a shift operation with a shift register clock is provided as an input of the next register that is connected with the output of (1, 112), and the above is provided. A circuit to read and test the internal state with a small number of pins. 4. A high speed gate array for a high speed IC (200)
A circuit for reading and testing the internal state of the IC according to claim 1, claim 2 or claim 3, wherein the large capacity IC is a large capacity gate array (100).