JPH0823999B2 - Data recall method in semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device in which a volatile semiconductor memory section and a non-volatile semiconductor memory section are combined.

<Prior Art, Problem to be Solved by the Invention> A conventional semiconductor memory device is a mask that is a non-volatile memory that retains stored contents even when power is turned off.
ROM (Read Only Memory), EEPROM (Electrical Erasable Programmable Read Only)
Memory) and DRAM (Dynamic Random Access Memory), which is a volatile memory whose contents are lost when the power is turned off.

By the way, the mask ROM and the EEPROM, which are nonvolatile memories, can retain the stored data for a long time even when the power is turned off. However, in the case of a mask ROM, data cannot be rewritten after data is written in a wafer process, and in the case of an EEPROM, data can be rewritten, but the data write / erase time is as long as about 10 msec. , Because the number of times of writing / erasing is limited,
There is a problem that it is not suitable for the purpose of constantly rewriting data. On the other hand, the volatile memory DRAM has a short data rewriting time of 100 msec or less and has no limit on the number of times of rewriting, but there is a problem that stored data is lost when the power is turned off.

Therefore, only recently, the present applicant has proposed a versatile semiconductor memory device capable of constantly rewriting data at high speed during use and retaining the rewritten data for a long time when the power is off.

As shown in FIG. 5, this semiconductor memory device has one MOS transistor T1 (hereinafter simply referred to as “transistor T1”) as a DRAM part, and one electrode terminal (storage node) 3 at the source of this transistor T1. , And one floating gate type transistor MT (hereinafter, simply referred to as “transistor MT”) as an EEPROM section. The source 10 of the transistor T1 is connected to the storage node 3 of the capacitor C, and the drain 9 of the transistor MT is connected via a mode selection transistor T2 (hereinafter simply referred to as "transistor T2") as a switch. The control gate 5 of is connected. The transistor T2 is
It is assumed that the gate terminal (mode selection gate) 7 is on / off controlled by applying a positive bias V7 or a zero bias. Incidentally, FIG. 10 shows a sectional structure of this semiconductor memory device. As shown in this figure, the source 2 and the drain 9 of the transistor MT are composed of two diffusion regions under the floating gate 4, and the tunnel oxide film 4a is formed.
The one covered by is the source 2 and the other is the drain 9. The gate electrode 6 of the transistor T1 is connected to the word line, and the drain 1 is connected to the bit line BL.

This semiconductor memory device operates as follows when the transistor T2 is off, that is, when the mode selection gate 7 is zero-biased.

First, as shown in FIG. 6, the DRAM section becomes an electrically equivalent equivalent circuit. Then, when writing data to the DRAM portion, as shown in the upper part of FIG. 8A, the cell selection gate voltage Vsg is applied to the gate terminal 6 to turn on the transistor T1, and the drain terminal 1 is supplied with the power supply voltage. Apply Vcc or zero bias. In response to this, the potential of the storage node 3 becomes Vcc or 0. That is, the data in the DRAM section becomes "1" or "0".

On the other hand, when writing data to the EEPROM section, first,
As shown in the middle part of FIG. 8A, the gate terminal 6 and the drain terminal 1 of the transistor T1 are biased to zero and the DRAM is
Of the transistor MT, the source terminal 2 of the transistor MT is zero-biased, while the program voltage Vpp is applied to the other electrode (plate electrode) terminal 8 of the capacitor C.
Is applied (step 1). Then, as shown in the upper part of FIG. 7 (step 1), the tunnel oxide film 4a is irrespective of whether the data in the DRAM part is "0" or "1".
Electrons are accumulated in the floating gate 4 through
The threshold value of the transistor T2 becomes high (erased state). At this time, since the transistor T2 is in the OFF state, the charge in the storage node 3 of the capacitor C does not escape, and therefore the data in the DRAM section does not change when the EEPROM is in the erased state. However, the capacity C of the capacitor is designed to be sufficiently larger than the gate capacity (capacitance between the terminals 5 and 2) C ₅₂ or C ₅ (capacitance between the terminal 5 and the substrate) of the transistor MT. I shall.

Next, as shown in the lower part of FIG.
The source terminal 2 of MT is set to the program voltage Vpp, while the plate electrode 8 of the capacitor C is set to zero bias. Then, as shown in the lower part of FIG. 7 (step 2), the content stored in the EEPROM section changes according to the data state "0" or "1" of the DRAM section. For explanation, the coupling ratio Rc of the transistor MT is However, C _{45 is} the capacitance between the floating gate 4 and the control gate 5, C _{4 is} the capacitance between the floating gate 4 and the substrate, and C _{42 is} the capacitance between the floating gate 4 and the source 2. The voltage applied to the film 4a is (a) in the case of DRAM data “0”, V ₀ = Rc · Vpp, and (b) in the case of DRAM data “1”, V ₁ = Rc (Vpp−Vcc). That is, in the case of the DRAM data “0”, a voltage higher by ΔV = V ₀ −V ₁ = RcVcc is applied to the tunnel oxide film 4a than in the case of the DRAM data “1”. Here, in the case of (a) DRAM “0”, since the voltage applied to the tunnel oxide film 4 a is high, the electrons accumulated in the floating gate 4 are extracted to the source 2. As a result, even if the potential of the floating gate 4 is increased and the transistor MT is turned on, the transistor T2 is in the off state, so that electrons do not flow out to the drain 9. In this way, many electrons are extracted and the threshold value of the transistor MT becomes low (write state).

(B) In the case of DRAM "1", since the voltage applied to the tunnel oxide film 4a is low, electrons remain stored in the floating gate 4. Therefore, the transistor MT
The threshold value of 1 remains high (erased state).

In this way, in response to “0” or “1” of the data in the DRAM block, the EEPR
The stored contents of the OM can be put in a written state (a state where the threshold value is low) or an erased state (a state where the threshold value is high).

Next, the case where the transistor T2 is in the ON state, that is, the case where the positive bias V7 is applied to the mode selection gate 7 will be described.

As shown in the upper part of FIG. 8 (b), the DRAM section operates in the same manner as in the off state by opening the source terminal 2 of the transistor MT and zero-biasing the plate terminal 8 of the capacitor C. To do.

On the other hand, when writing data to the EEPROM section, as shown in the lower part of FIG. 8 (b) and in FIG.
The drain terminal 1 and the cell selection gate terminal 6 are zero-biased to prevent the DRAM part from operating, and the transfer bias V2 is applied to the source terminal 2 of the transistor MT, while the plate terminal 8 of the capacitor C is zero-biased. To do.

In this way, as in the case where the transistor T2 is in the off state, the data “0” or “1” in the DRAM section is dealt with.
The stored contents of the EEPROM section can be put in a written state or an erased state. Note that, as shown in FIG. 9, since the drain 9 of the transistor MT and the storage node 3 of the capacitor C are equivalently connected, the charge of the storage node 3 is changed to the drain of the transistor MT during writing. 9
Lost through. That is, the data in the DRAM unit is not stored, and is transferred to the EEPROM unit.

As described above, this semiconductor memory device operates as a DRAM in which data can be constantly rewritten at high speed when used, and also transfers data from the DRAM section to the EEPROM section or the DRAM section.
The data in the EEPROM section can be rewritten while the data in the section is preserved. When the power is off, data can be stored as EEPROM for a long period of time, and can be used for many purposes.

The present invention provides a data recall method for recalling data written in an EEPROM section to a DRAM section in the semiconductor memory device.

<Means for Achieving the Object> The data recall method in the semiconductor memory device of the present invention comprises one MOS transistor and one capacitor having one electrode terminal connected to the source of this MOS transistor. A volatile semiconductor memory section and a non-volatile semiconductor memory section composed of one floating gate type transistor are provided, and the drain of the floating gate type transistor is connected to the source of the MOS transistor and one electrode terminal of the capacitor through a switch. Data recall method for returning the data written in the non-volatile semiconductor memory section to the volatile semiconductor memory section in a semiconductor memory device constituted by connecting the control gates of the floating gate type transistors And the above floating gate type The non-volatile semiconductor memory unit is utilized by utilizing the fact that the floating gate type transistor becomes non-conductive or conductive depending on whether the threshold value of the transistor is higher or lower than the potential of the capacitor storage node which is the control gate. The data written in is returned to the volatile semiconductor memory unit.

<Embodiment> Hereinafter, a data recall method in the semiconductor memory device of the present invention will be described in detail with reference to an embodiment. The fifth
It is assumed that the same semiconductor memory device as shown in the figure is rewritten, the same reference numerals are given to the respective components, and the description thereof will be omitted.

FIG. 11 shows the timing of the voltage applied to each of the terminals 2, 1, 8, 6, and 7 when rewriting the EEPROM section of the semiconductor memory device. As shown in FIG. 11, during the rewriting period, the drain (D) terminal 1 and the gate electrode (SG ₂ ) terminal 6 of the transistor T1 are always GND (grounded).
State and keep the DRAM section from operating,
The mode selection gate (SG ₁ ) 7 of the transistor T2 is set to the GND state and the transistor T2 is turned off so that the charge of the storage node 3 of the capacitor C is not released. And
First, the plate electrode (CG) terminal 8 of the capacitor C
Is kept at the GND state, and the pulse voltage Vpp ₁ is applied to the source (S) terminal 2 of the transistor MT (step 1). next,
The source terminal 2 is kept in the GND state, and the pulse voltage Vpp ₂ is applied to the plate electrode terminal 8 (step 2). When the pulse voltages Vpp ₁ and Vpp ₂ are applied, a high electric field is applied to the tunnel oxide film 4a, and Fowler-Nordheim (Fowler-
Nordheim) Current is generated by tunneling. This tunnel current Ifn is related to the shift of the threshold voltage Vth of the EEPROM section as follows.

First, the tunnel current Ifn injected from the source 2 to the floating gate 4 via the tunnel oxide film 4a is | Ifn | = S.A.Eox.exp (-B / | eox |) (1). In addition, S is the area of the tunnel part, A and B are constants, and Eox
Is the electric field applied to the tunnel oxide film 4a (tunnel electric field)
Is represented. When the pulse voltage Vpp _{1 is} applied, Eox>
0, Ifn> 0 and Eox <0, Ifn when pulse voltage Vpp _{2 is} applied
<0.

Data “1” or “0” in the DRAM section, that is, storage node 3
The tunnel electric field corresponding to the presence or absence of electric charge is
Given that o ₁ and Eo ₀ , the difference ΔEo between the tunnel electric fields is expressed by the following equation (2).

Where Tox is the thickness of the tunnel oxide film 4a, Ci is the capacitance between the storage node 3 and the floating gate 4, and Cs is DR.
The storage capacitance of the AM portion, Cfs, shows the capacitance due to the overlapping of the floating gate 4 and the source 2. Equation (2) is
It is shown that the difference ΔEo of the tunnel electric field between the case of the DRAM data “1” and the case of the DRAM data “0” is negative.

In addition, the positive charge Δ that moves to the floating gate
Q ₅ is expressed by the following equation (3) when the pulse voltage application time is Δt.

ΔQf = Ifn · Δt (3) The change ΔVth in the threshold voltage Vth of the EEPROM section due to the charge transfer is expressed by the following equation (4).

ΔVth = −ΔQf / Ci (4) In this way, the tunnel current Ifn shown in the equation (1) is related to the change in the threshold voltage Vth. By the way, the tunnel current Ifn has a strong dependence on the tunnel electric field Eox, and the tunnel current remarkably increases even with a small electric field increase due to data “0” or “1” in the DRAM part. Each case will be described. In step 1 (Eox> 0), as shown in FIG. 2C, in the case of data “1” in the DRAM part, the tunnel current
Ifn is very small, and there is almost no change in the threshold voltage Vth of the EEPROM. On the other hand, as shown in FIG. 2A, in the case of data “0” in the DRAM part, a high electric field is applied by | ΔEo |, and the tunnel current in the positive direction significantly increases. As a result, The threshold voltage Vth of the EEPROM part shifts in the negative direction. When this is actually calculated, the calculation result shown in FIG. 3 is obtained. That is, (i) In the case of data “0” in the DRAM section When the threshold voltage Vth of the initial EEPROM section is Vth = 4.0V (“H” state), as the pulse voltage Vpp ₁ increases, the Vth of the EEPROM section becomes low. Become. Vth of EEPROM section is ≤0.0 when Vpp ₁ ≥12V
It becomes 4V and does not depend on the initial state, and begins to match the result when the initial Vth = 0.

(Ii) In the case of data “1” in the DRAM section When the pulse voltage Vpp ₁ ≦ 12V, the Vth in the EEPROM section changes little and Vth ≧ 3.72V.

In step 2 (Eox <0), as shown in FIG. 2 (b), when the data of the DRAM section is “0”, the tunnel current | I
fn | is very small, and there is almost no change in the threshold voltage Vth of the EEPROM. On the other hand, as shown in FIG. 2D, in the case of the data “1” in the DRAM portion, a high electric field is applied by | ΔEo |, and the tunnel current in the negative direction significantly increases. The threshold voltage Vth of the EEPROM shifts in the positive direction. When this was actually calculated, the calculation results shown in FIG. 4 were obtained. That is, (i) In the case of data “0” in the DRAM section, the initial Vth after step 1 is in the “L” state, and if Vth = 0, the change in Vth is small when the pulse voltage Vpp ₂ ≦ 12V,
Vth ≦ 0.15V.

(Ii) In the case of data "1" in the DRAM section When Vth = 0 in the initial stage, the Vth of the EEPROM section increases as the pulse voltage Vpp ₂ increases. The Vth of the EEPROM section becomes Vth ≧ 3.68V when the pulse voltage is Vpp ₂ ≧ 12V, does not depend on the initial state, and begins to match even when the initial Vth = 4.0V.

In this way, the shift of the threshold voltage Vth of the EEPROM section that occurs in response to the data state “0” or “1” of the DRAM section is
It is a reasonable value for reading the EPROM data and making a DRAM helicopt.

In this way, when the data in the DRAM is “0”, the Vth in the “H” state of the EEPROM is changed to the “L” state in step 1, while the Vth in the “L” state remains the “L” state. After that, since the "L" state is not changed in step 2, compared to the case where the Vth in the "L" state is once changed to the "H" state and then changed to the "L" state again, It is possible to eliminate the waste of rewriting. On the other hand, in the case of the data "1" of the DRAM part, the Vth of the EEPROM part is not changed in step 1. Then, in step 2, EE
While changing the Vth in the "L" state of the PROM section to the "H" state,
Since the Vth in the "H" state is kept in the "H" state, the number of times of rewriting is the same as when the high level method is used. Therefore, the number of times of rewriting of the EEPROM section can be reduced as a whole when backing up to the EEPROM section, and the reliability can be improved when the LSI is realized.

Of course, the pulse voltages Vpp ₁ and Vpp ₂ in steps 1 and 2 may be applied in the reverse order.

Also, when the data written in the EEPROM section is called to the DRAM section, it is performed as follows. First, as shown in FIGS. 1A and 1B, with the plate electrode 8 and the source terminal 2 grounded, the bit line BL connected to the drain 1 of the transistor T1 is precharged (voltage Vcc).
After that, the voltage Vw ₁ (Vw ₁ ≧ 7V when Vcc = 5V) is applied to the cell selection gate 6 and the mode selection gate 7 to turn on both the transistors T1 and T2. Where EEPRO
When the Vth of the M portion is in the “L” state, as shown in FIG. 1A, the positive charge accumulated in the bit line BL is a transistor.
It is pulled out from the drain terminal 1 side to the source terminal 2 side via each channel of T1, T2, MT. Along with this, the voltage of the storage node drops until it matches Vth of the EEPROM section, and the state of data “0” in the DRAM section is set. Note that the transistors T1 and T2 may be turned on at the same time, or the transistor T1 may be turned on first to temporarily store charges in the storage node 3 and then turn on the transistor T2. On the other hand, when Vth of EEPROM part is in “H” state,
As shown in FIG. 1 (b), since the transistor MT is in the off state, the positive charge accumulated in the bit line BL is accumulated in the accumulation node 3 and becomes the state of the data "1" of the DRAM part. . In this way, the data written in the EEPROM section is DR
AM helicopter can be called.

<Effect of the Invention> As described in detail above, according to the present invention,
The MOS transistor includes a volatile semiconductor memory section including a MOS transistor and a capacitor having one electrode terminal connected to the source of the MOS transistor, and a nonvolatile semiconductor memory section including a floating gate type transistor. In the semiconductor memory device constituted by connecting the drain of the floating gate type transistor via a switch to the source of the capacitor and one electrode terminal of the capacitor, and connecting the control gate of the floating gate type transistor,
A data recall method for returning the data written in the PROM section to the DRAM section can be obtained.

[Brief description of drawings]

1 (a) and 1 (b) are diagrams for explaining the operation of the semiconductor memory device when recalling stored contents, and FIG. 2 is a diagram for explaining the operation of the semiconductor memory device at the time of rewriting, and FIG.
FIG. 4 and FIG. 4 are views showing changes in the threshold voltage of the EEPROM section due to application of a pulse voltage, FIG. 5 is a circuit diagram of the semiconductor memory device, and FIG. 6 is a circuit showing a DRAM part of the semiconductor memory device. 7 and 8 are diagrams for explaining the operation of the EEPROM section of the semiconductor memory device, FIGS. 8 (a) and 8 (b) are diagrams showing bias application conditions of the semiconductor memory device, and FIG. 9 is the semiconductor memory device. FIG. 10 is a circuit diagram showing an EEPROM portion of the device, FIG. 10 is a sectional view showing a structure of the semiconductor memory device, and FIG. 11 is a timing diagram showing a rewriting method of the semiconductor memory device. Explanation of symbols 1,9 ... drain, 2,10 ... source, 3 ... storage node, 4 ... floating gate, 4a ... tunnel oxide film, 5 ... control gate, 6 ... cell select gate, 7 ......
Mode selection gate, 8: Plate electrode, C: Capacitor, MT: Floating gate transistor, T1
…… MOS transistor, T2 …… Mode selection transistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 27/105 29/788 29/792 H01L 29/78 371 27/10 441 (56) References Kai 58-119667 (JP, A) JP 58-142565 (JP, A) JP 60-185294 (JP, A) JP 62-266793 (JP, A) JP 63-84165 ( JP, A) JP-A-63-209097 (JP, A) JP-A-2-27594 (JP, A)

Claims (1)

[Claims] 1. A volatile semiconductor memory section comprising one MOS transistor and one capacitor having one electrode terminal connected to the source of this MOS transistor, and a non-volatile semiconductor comprising one floating gate type transistor. A memory portion is provided, and the drain of the floating gate type transistor is connected to the source of the MOS transistor and one electrode terminal of the capacitor via a switch, and the control gate of the floating gate type transistor is connected. In a semiconductor memory device, data written in the non-volatile semiconductor memory unit is returned to the volatile semiconductor memory unit.
A recall method, wherein the floating gate type transistor is turned off or turned on depending on whether a threshold value of the floating gate type transistor is higher or lower than a potential of a capacitor storage node which is a control gate. Utilizing, the data written in the nonvolatile semiconductor memory unit is returned to the volatile semiconductor memory unit,
Data recall method in semiconductor memory device.